Features
•80C52 Compatible
– 8051 Instruction Compatible
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit T ime r/ Counte rs
– 256 bytes Scratch Pad RAM
– 11 Interrupt Sources With 4 Priority Levels
•ISP (In-System Programming) Using Standard VCC Power Supply
•Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
•Boot ROM Contains Serial Loader for In-System Programming
•High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
– In X2 Mode (6 Clocks/Machine Cycle)
20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
•128K bytes On-chip Flash Program/Data Memory
– 128 bytes Page Write with auto-erase
– 100k Write Cycles
•On-chip 8192 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048, 4096, 8192 bytes)
•Dual Data Pointer
•Extended stack pointer to 512 bytes
•Variable Length MOVX for Slow RAM/Peripherals
•Improved X2 Mode with Independant Selection for CPU and Each Peripheral
•Keyboard Interrupt Interface on Port 1
•SPI Interface (Master/Slave Mode)
•8-bit Clock Prescaler
•Programmable Counter Array with:
– High Speed Output
–Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
•Asynchronous Port Reset
•Two Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator
•Low EMI (inhibit ALE)
•Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag
•Power Control Modes: Idle Mode, Power-down Mode
•Power Supply: 2. 7V to 5.5V
•Temperature Ranges: Industrial (-40 to +85°C)
•Packages: PLCC44, VQFP44
8-bit Flash
Microcontroller
AT89C51RE2
27663E–8051–10/08
AT89C51RE2
Description
AT89C51 RE2 i s a hi gh pe r forman ce CM O S Fla sh v ers ion o f t he 80C51 CMO S si ngl e ch ip 8- bi t
microcontroller. It contains a 128 Kbytes Flash memory block for program.
The 128 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with
the ISP c apability or with softwar e. The programm ing voltag e is interna lly generated from the
standard VCC pin.
The AT89 C51RE 2 re tai ns all features of the Atm el 80C 52 wi th 256 by tes of inte rnal RAM , a 10-
source 4-level interrupt controller and three timer/counters.
In addition, the AT89C51RE2 has a Programmable Counter Array, an XRAM of 8192 bytes, a
Hardw are Wa tchd og Tim er, S PI and Key boa rd, tw o s eria l c han nels th at f aci lita tes mu ltip roce s-
sor co mmunic ation (E UART), a speed improv ement me chanism (X2 mod e) and an ex tended
stack mode that allows the stack to be extended in the lower 256 bytes of XRAM.
The fully static design of the AT89C51RE2 allows to reduce syst em power consumption by
bringing the clock frequency down to any value, even DC, without loss of data.
The AT89C51RE2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler
for furth er re ductio n in power consu mpti on . In the Idle mod e the CPU i s froz en whil e th e peri ph-
erals and the interrupt system are still operating. In the power-down mode the RAM is saved and
all other functions are inoperative.
The added featu res of the AT89 C51RE2 mak e it more powe rful for appl ications that need puls e
width modulation, high speed I/O and counting capabilities such as alarms, motor control,
corded pho nes, smart car d reade rs.
Table 1. Memory Size and I/O pins
AT89C51RE2 Flash (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O
PLCC44
VQFP44 128K 8192 8192 + 256 34
3
7663E–8051–10/08
AT89C51RE2
Block Diagram
Figure 1. Block Diagram
Time r 0 INT
RAM
256x8
T0
T1 RxD_0
TxD_0
WR
RD
EA
PSEN
ALE/
XTALA2
XTALA1
EUART
CPU
Time r 1
INT1
Ctrl
INT0
(2)
(2)
C51
CORE
(2) (2) (2) (2)
Port 0
P0
Port 1
Port 2
Port 3
P1
P2
P3
XRAM
8192 x 8
IB-bus
PCA
RESET
PROG
Watch
Dog
PCA
ECI
Vss
VCC
(2)(2) (1)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(1)
Timer2
T2EX
T2
(1) (1)
Flash
128Kx8
Keyboard
(1)
Keyboard
MISO
MOSI
SCK
SS
(3): Alternate function of Port 6
(3) (3)
Port4
P4
(1) (1)(1)(1)
BOOT
4K x8
ROM
Regulator
POR / PFD
Port 5
P5
Parallel I/O Ports &
External Bus SPI
POR
PFD
XTALB2
XTALB1(1)
EUART_1
RxD_1
TxD_1
TWI
SDA
SCL
47663E–8051–10/08
AT89C51RE2
Pin Configurations
43 42 41 40 3944 38 37 36 35 34
P1.4/CEX1
P1.0/T2/XTALB1
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
Rx_OCD
VCC
P0.0/AD0
P0.2/AD2
P0.3/AD3
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE
PSEN
EA
P6.1/TxD_1/SCL
P2.7/A15
P2.5/A13
P2.6/A14
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD_0
P6.0/RxD_1/SDA
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
Tx_OCD
1213 17161514 201918 2122
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
VQFP44
PLCC44
AT89C51RE2
AT89C51RE2
18 19 23222120 262524 27 28
5 4 3 2 1 6 44 43 42 41 40
P1.4/CEX1
P1.0/T2
P1.1/T2EX/SS
P1.3/CEX0
P1.2/ECI
Rx_OCD
VCC
P0.0/AD0
P0.2/AD2
P0.1/AD1
P0.4/AD4
P0.6/AD6
P0.5/AD5
P0.7/AD7
ALE
PSEN
EA
P6.1/TxD_1/SCL
P2.7/A15
P2.5/A13
P2.6/A14
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
P2.4/A12
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD_0
P6.0/RxD_1/SDA
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P0.3/AD3
Tx_OCD
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
5
7663E–8051–10/08
AT89C51RE2
Table 2. Pin Description
Mnemonic
Pin Number
Type Name and FunctionLCC VQFP 1.4
VSS 22 16 I Ground: 0V refe rence
Vss1 39 I Optional Ground: Contac t the Sales Of fice for gr ound connect ion.
VCC 44 38 I Power Supply: This is the power supply voltage for normal, idle and power-down operation
P0.0-P0.7 43-36 37-30 I/O Port 0 : Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in
order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order
address and data bus during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes
during EPROM programming. External pull-ups are required during program verification
during which P0 outputs the code bytes.
P1.0-P1.7 2-9 40-44
1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally pulled low will source current because of the internal pull-ups.
Port 1 also receives the low-order address byte during memory programming and
verification.
Alternate functions for TSC8x54/58 Port 1 include:
240I/OT2 (P1.0): Timer/Counter 2 external count input/Clockout
341 IT2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
442 IECI (P1.2): External Clock for the PCA
543I/OCEX0 (P1.3): Capture/Compare External I/O for PCA module 0
644I/OCEX1 (P1.4): Capture/Compare External I/O for PCA module 1
71I/OCEX2 (P1.5): Capture/Compare External I/O for PCA module 2
82I/OCEX3 (P1.6): Capture/Compare External I/O for PCA module 3
93I/OCEX4 (P1.7): Capture/Compare External I/O for PCA module 4
P2.0-P2.7 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally pulled low will source current because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this
application, it uses strong internal pull-ups emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming and
verification:
P2.0 to P2.5 fo r R B d e vi ces
P2.0 to P2.6 fo r R C d e v i ce s
P2.0 to P2.7 fo r R D d e v i ce s.
P3.0-P3.7 11,
13-19 5,
7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current because of the internal pull-ups.
Port 3 also serves the special features of the 80C51 family, as listed below.
11 5 I RXD_0 (P3.0): Serial input port
13 7 O TXD_0 (P3.1): Serial output port
14 8 I INT0 (P3.2): External interrupt 0
67663E–8051–10/08
AT89C51RE2
15 9 I INT1 (P3.3): External interrupt 1
16 10 I T0 (P3.4): Timer 0 external input
17 11 I T 1 (P3. 5): Timer 1 external input
18 12 O WR (P3.6): External data memory write strobe
19 13 O RD (P3.7): External data memory read strobe
P6.0-P6.1 12,34 6, 28
Port 6: Port 6 is an 2-bit bidirectional I/O port with internal pull-ups. Port 6 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 6 pins that are externally pulled low will source current because of the internal pull-ups.
Port 6 also serves some special features as listed below.
12 6 I RXD_1 (P6.0): Serial input port
12 6 I/O SDA (P6.0) : TWI Serial Data
SDA is the bidirectional TWI data line.
34 28 O TXD_1 (P6.1) : Serial output port
34 28 I/O
SCL ( P6.1) : TWI Serial Clock
SCL output the serial clock to slave peripherals.
SCL input the serial clock from master.
Reset 10 4 I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capac i to r to VCC. This pin is an output when the hardware watchdog forces a system reset.
ALE/PROG 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external
timing or clocking. Note that one ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG) during Flash programming. ALE
can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during
internal fetches.
PSEN 32 26 O Program Store ENable: The read strobe to external program memory. When executing
code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory.
PSEN is not activated during fetches from internal program memory.
EA 35 29 I External Access Enable: EA must be externally held low to enable the device to fetch code
from external program memory locations 0000H to FFFFH (RD). If security level 1 is
programmed, EA will be internally latched on Reset.
XTAL1 21 15 I Crys tal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
XTAL2 20 14 O Crys tal 2: Output from the inverting oscillator amplifier
Tx_OCD 23 17 O Tx_OCD: On chip debug Serial output port
Rx_OCD 1 39 I Rx_OCD: On chip debug Serial input port
Mnemonic
Pin Number
Type Name and FunctionLCC VQFP 1.4
7
7663E–8051–10/08
AT89C51RE2
SFR Mapping The Special Function Registers (SFRs) of the AT89C51RE2 fall into the following categories:
• C51 core registers: ACC, B, DPH, DPL, PSW, SP
• I/O port registers: P0, P1, P2, P3, P4, P5, P6
• T im er registe rs: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP 2L,
RCAP2H
• Serial I/O port registers: SADDR_0, SADEN_0, SBUF_0, SCON_0, SADDR_1, SADEN_1,
SBUF _1, SCON_1,
• PCA (Programmable Counter Array) registers: CCON, CCAPMx, CL, CH, CCAPxH,
CCAPxL (x: 0 to 4)
• Power and clock control registers: PCON, CKAL, CKCON0_1
• Hardware Watchdog Timer registers: WDTRST, WDTPRG
• Interrupt system registers: IE0, IPL0, IPH0, IE1, IPL1, IPH1
• Keyboard Interface registers: KBE, KBF, KBLS
• 2-wire Interface registers: SSCON, SSCS, SSDAT, SSADR
• SPI registers: SPCON, SP STR, SPDAT
• BRG (Baud Rate Generator) registers: BRL_0, BRL_1, BDRCON_0, BDRCON_1
• Memory register: FCON, FSTA
• Clock Prescaler register: CKRL
• Others: AUXR, AUXR1, CKCON0, CKCON1, BMSEL
87663E–8051–10/08
AT89C51RE2
Table 3. C51 Core SFRs
MnemonicAddName 76543210
ACC E0h Accumulator
B F0h B Register
PSW D0h Program St atus Word CY AC F0 RS1 RS0 OV F1 P
SP 81h S tack Pointer
DPL 82h Data Pointer Low byte
DPH 83h Data Pointer High byte
Table 4. System Management SFRs
MnemonicAddName 76543210
PCON 87h Power Control SMOD1_0 SMOD0_0 - POF GF1 GF0 PD IDL
AUXR 8Eh Auxiliary Register 0 - - M0 XRS2 XRS1 XRS0 EXTRA
MAO
AUXR1 A2h Auxiliary Register 1 EES SP9 U2 - GF2 0 - DPS
CKRL97hClock Reload Register --------
BMSEL 92h Bank Memory Select MBO2 MBO1 MBO0 - FBS 2 FBS1 FBS0
CKCON0 8Fh Clock Control Register 0 TWIX2 WDX2 PCAX2 SIX2_0 T2X2 T1X2 T0X2 X2
CKCON1AFhClock Control Register 1 ------SIX2_1SPIX2
Table 5. In terr upt S FRs
MnemonicAddName 76543210
IEN0 A8h Interrupt Enable Control 0 EA EC ET2 ES ET1 EX1 ET0 EX0
IEN1 B1hInterrupt Enable Control 1 ----ES_1ESPIETWIEKBD
IPH0 B7h Interrupt Priority Control High 0 - P PCH PT2H PSH PT1H PX1H PT0H PX0H
IPL0 B8h Interrupt Pr iority Control Low 0 - PPCL PT2L PSL PT1L PX1L PT 0L PX0L
IPH1 B3hInterrupt Priority Control High 1----PSH_1SPIHIE2CHKBDH
IPL1 B2hInterrupt Priority Control Low 1----PSL_1SPILIE2CLKBDL
Table 6. Port SFRs
MnemonicAddName 76543210
P0 80h 8-bit Port 0
P1 90h 8-bit Port 1
P2 A0h 8-bi t Port 2
P3 B0h 8-bi t Port 3
P4 C0h 8-bit Port 4
9
7663E–8051–10/08
AT89C51RE2
P5 E8h 8-bi t Port 5
P6 F8h2-bit Port 5 ------
Table 6. Port SFRs
MnemonicAddName 76543210
Table 7. Flash and EEPROM Data Memory SFR
MnemonicAddName 76543210
FCON D1h Flash Contr o ller Control FPL3 FPL2 F PL1 F PL0 FPS F MO D2 FMOD1 FMOD0
FSTA D3h Flash Controller Status FMR FSE FLOAD FB USY
Table 8. Timer SFRs
MnemonicAddName 76543210
TCON 88h Timer/Counter 0 and 1 Control TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
TMOD 89h Timer/Counter 0 and 1 Modes GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
TL0 8Ah Timer/Counter 0 Low Byte
TH0 8Ch Timer/Counter 0 High Byte
TL1 8Bh Timer/Counter 1 Low Byte
TH1 8Dh T imer/Counter 1 High Byte
WDTRST A6h WatchDog Timer Reset
WDTPRGA7hWatchDog Timer Program -----WTO2WTO1WTO0
T2CON C8h T imer/Counter 2 control TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
T2MOD C9h Timer/Counter 2 Mode ------T2OEDCEN
RCAP2H CBh T imer/Counter 2 Reload/Capture
High byte
RCAP2L CAh T imer/Counter 2 Reload/Capture
Low byte
TH2 CDh Timer/Counter 2 High Byte
TL2 CCh Timer/Counter 2 Low Byte
Table 9. PCA SFRs
Mnemo
-nicAddName 76543210
CCON D8h PCA Timer/Counter Control CF CR - CCF4 CCF3 CCF2 CCF1 C CF0
CMOD D9h PCA Timer/Counter Mode CIDL WDTE - - - CPS1 CPS0 E CF
CL E9h P CA Timer/Counter Low byte
10 7663E–8051–10/08
AT89C51RE2
CH F 9h PCA Timer/Counter High byte
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
DAh
DBh
DCh
DDh
DEh
PCA Timer/Counter Mode 0
PCA Timer/Counter Mode 1
PCA Timer/Counter Mode 2
PCA Timer/Counter Mode 3
PCA Timer/Counter Mode 4
-
ECOM0
ECOM1
ECOM2
ECOM3
ECOM4
CAPP0
CAPP1
CAPP2
CAPP3
CAPP4
CAPN0
CAPN1
CAPN2
CAPN3
CAPN4
MAT0
MAT1
MAT2
MAT3
MAT4
TOG0
TOG1
TOG2
TOG3
TOG4
PWM0
PWM1
PWM2
PWM3
PWM4
ECCF0
ECCF1
ECCF2
ECCF3
ECCF4
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
FAh
FBh
FCh
FDh
FEh
PCA Compare Capture Module 0 H
PCA Compare Capture Module 1 H
PCA Compare Capture Module 2 H
PCA Compare Capture Module 3 H
PCA Compare Capture Module 4 H
CCAP0H7
CCAP1H7
CCAP2H7
CCAP3H7
CCAP4H7
CCAP0H6
CCAP1H6
CCAP2H6
CCAP3H6
CCAP4H6
CCAP0H5
CCAP1H5
CCAP2H5
CCAP3H5
CCAP4H5
CCAP0H4
CCAP1H4
CCAP2H4
CCAP3H4
CCAP4H4
CCAP0H3
CCAP1H3
CCAP2H3
CCAP3H3
CCAP4H3
CCAP0H2
CCAP1H2
CCAP2H2
CCAP3H2
CCAP4H2
CCAP0H1
CCAP1H1
CCAP2H1
CCAP3H1
CCAP4H1
CCAP0H0
CCAP1H0
CCAP2H0
CCAP3H0
CCAP4H0
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EAh
EBh
ECh
EDh
EEh
PCA Compare Capture Module 0 L
PCA Compare Capture Module 1 L
PCA Compare Capture Module 2 L
PCA Compare Capture Module 3 L
PCA Compare Capture Module 4 L
CCAP0L7
CCAP1L7
CCAP2L7
CCAP3L7
CCAP4L7
CCAP0L6
CCAP1L6
CCAP2L6
CCAP3L6
CCAP4L6
CCAP0L5
CCAP1L5
CCAP2L5
CCAP3L5
CCAP4L5
CCAP0L4
CCAP1L4
CCAP2L4
CCAP3L4
CCAP4L4
CCAP0L3
CCAP1L3
CCAP2L3
CCAP3L3
CCAP4L3
CCAP0L2
CCAP1L2
CCAP2L2
CCAP3L2
CCAP4L2
CCAP0L1
CCAP1L1
CCAP2L1
CCAP3L1
CCAP4L1
CCAP0L0
CCAP1L0
CCAP2L0
CCAP3L0
CCAP4L0
Table 10. Serial I/O Port SFRs
MnemonicAddName 7 6 543210
SCON_0 98h Serial Control 0 FE/SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
SBUF_0 99h Serial Data Buffer 0
SADEN_0 B9h Slave Add ress Mas k 0
SADDR _0 A9h Slave Address 0
BDRCON_0 9Bh Baud Rate Control 0 BRR_0 TBCK_0 RBCK_0 SPD_0 SRC_0
BRL_0 9Ah Baud Rate Reload 0
SCON_1 C0h Serial Control 1 FE_1/SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
SBUF_1 C1h Serial Data Buffer 1
SADEN_1 BAh Slave Address Mask 1
SADDR _1 AAh Slave Address 1
BDRCON_1 BCh Baud Rate Control 1 SMOD1_1 SMOD0_1 BRR_1 TBCK_1 RBCK_1 SPD_1 SRC_1
BRL_1 BBh Baud Rate Reload 1
Table 9. P CA SF Rs (Cont inued)
Mnemo
-nicAddName 76543210
11
7663E–8051–10/08
AT89C51RE2
Table 11. SPI Controller SFRs
MnemonicAddName 76543210
SPCON C3h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPSCR C4h SPI Status SPIF OVR MODF SPTE UARTM SPTEIE MODFIE
SPDAT C5h SPI Data SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0
Table 12. Two-W ire Inter fac e Control ler SFRs
Mnemonic Add Name 7 6 5 4 3 2 1 0
SSCON 93h Synchronous Serial control SSCR2 SSPE SSSTA SSSTO SSI SSAA SSCR1 SSCR0
SSCS 94h Synchronous Serial Status SSC4 SSC3 SSC2 SSC1 SSC0 0 0 0
SSDAT 95h Synchronous Serial Data SSD7 SSD6 SSD5 SSD4 SSD3 SSD2 SSD1 SSD0
SSADR 96h Synchronous Serial Address SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSGC
Table 13. Keyboard Interface SFRs
MnemonicAddName 76543210
KBLS 9Ch Keyboard Level Selector KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
KBE 9Dh Keyboard Input Enable KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
KBF 9Eh Keyboard Flag Register KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
12 7663E–8051–10/08
AT89C51RE2
Table below shows all SFRs with their address and their reset value.
Table 14. SFR Mapping
Bit
addressable Non Bit addressable
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
F8h P6
XXXX XX11 CH
0000 0000 CCAP0H
XXXX XXXX CCAP1H
XXXX XX X X CCAP2H
XXXX XXXX CCAP3H
XXXX X XX X CCAP4H
XXXX XXXX FFh
F0h B
0000 0000 F7h
E8h P5
1111 1111 CL
0000 0000 CCAP0L
XXXX XXXX CCAP1L
XXXX XX X X CCAP2L
XXXX XXXX CCAP3L
XXXX X XX X CCAP4L
XXXX XXXX EFh
E0h ACC
0000 0000 E7h
D8h CCON
00X0 0000 CMOD
00XX X000 CCAPM0
X000 0000 CCAPM1
X000 0000 CCAPM2
X000 0000 CCAPM3
X000 0000 CCAPM4
X000 0000 DFh
D0h PSW
0000 0000 FCON
0000 0000 FSTA
xxxx x000 D7h
C8h T2CON
0000 0000 T2MOD
XXXX XX00 RCAP2L
0000 0000 RCAP2H
0000 0000 TL2
0000 0000 TH2
0000 0000 CFh
C0h
U2(AUXR1.5)
=0 SCON_1
0000 0000 SBUF_1
0000 0000 SPCON
0001 0100 SPSCR
0000 0000 SPDAT
XXXX X XX X C7h
U2(AUXR1.5)
=1 P4
1111 1111
B8h IPL0
X000 000 SADEN_0
0000 0000 SADEN1
0000 0000 BRL_1
0000 0000 BDRCON_1
XXX0 0 000 BFh
B0h P3
1111 1111 IEN1
XXXX 0000 IPL1
XXXX 0000 IPH1
XXXX 0111 IPH0
X000 0000 B7h
A8h IEN0
0000 0000 SADDR_0
0000 0000 SADDR_1
0000 0000 CKCON1
XXXX XX00 AFh
A0h P2
1111 1111 AUXR1
000x 11x0 WDTRST
XXXX XXXX WDTPRG
XXXX X000 A7h
98h SCON_0
0000 0000 SBUF_0
XXXX XXXX BRL_0
0000 0000 BDRCON_0
XXX0 0000 KBLS
0000 0000 KBE
0000 0000 KBF
0000 0000 9Fh
90h P1
1111 1111 BMSEL
0000 0YYY SSCON
0000 0000 SSCS
1111 1000 SSDAT
1111 1111 SSADR
1111 1110 CKRL
1111 1111 97h
88h TCON
0000 0000 TMOD
0000 0000 TL0
0000 0000 TL1
0000 0000 TH0
0000 0000 TH1
0000 0000 AUXR
XX00 1000 CKCON0
0000 0000 8Fh
80h P0
1111 1111 SP
0000 0111 DPL
0000 0000 DPH
0000 0000 PCON
00X1 0000 87h
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
Reserved
13
7663E–8051–10/08
AT89C51RE2
Enhanced
Features In comparison to the original 80C52, the AT89C51RE2 implements s ome new features, which
are:
• X2 option
• Dual Data Pointer
• Extend ed RAM
• Extend ed stack
• Programmable Counter Array (PCA)
• Hardwar e Watchdog
• SPI i nterfac e
• 4-lev el interr upt prior i ty sy st em
• power-off flag
• ONCE mode
• ALE disabling
• Enhanced features on the UART and the timer 2
X2 Feature The AT89C51RE2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’
provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically the operating frequency by 2 in operating
and idle mode s.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
Description The clock for the whole circuit and peripherals is first divided by two before being used by the
CPU core and the peripherals.
This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is
bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%.
Figure 2 sh ows the cloc k gen eration b lock di agram . X2 b it is va lidate d on th e risin g edge of the
XTAL1÷2 to avoi d glitches when s witchi ng from X2 to STD mode. F igure 3 s hows the switchin g
mode waveforms.
Figure 2. Clock Generation Diagram
XTAL1 2
CKCON0
X2
8 bit Prescaler
FOSC
FXTAL 0
1
XTAL1:2 FCLK CPU
FCLK PERIPH
CKRL
14 7663E–8051–10/08
AT89C51RE2
Figure 3. Mode Switching Waveforms
The X 2 bit in the CK CON0 regis ter (see Table 15) a llows a sw itch from 12 cl ock period s per
instru cti on to 6 cl oc k pe riods and vice versa. At res et, the spee d is set acco r din g to X2 bi t of the
Fuse Configuration Byte (FCB). By default, Standard mode is active. Setting the X2 bit activates
the X2 feature (X2 mode).
The T0X2, T1X2, T2X2, UartX2, PcaX2, and WdX2 bits in the CKCON0 register (See Table 15.)
and SPI X2 bit in the CKCON1 registe r (see Tabl e 16) all ows a sw itch from standa rd per ipheral
speed (1 2 c lock perio ds per pe riphe ra l c lo ck c ycle ) to fast pe riphe ra l s pee d (6 c loc k per io ds per
peripheral clock cycle). These bits are active only in X2 mode.
XTAL1:2
XTAL1
CPU clock
X2 bit
X2 ModeSTD Mode STD Mode
FOSC
15
7663E–8051–10/08
AT89C51RE2
Table 15. CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = X000 000’HSB. X2’b (See “Fuse Configuration Byte: FCB”)
Not bit address ab le
76543210
TWIX2 WDX2 PCAX2 SIX2_0 T2X2 T1X2 T0X2 X2
Bit
Number Bit
Mnemonic Description
7TWIX2
2-wire cloTBck
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect)
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
6WDX2
Watchdog Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5PCAX2
Programmable Counter Array Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
4 SIX2_0
Enhanced UART0 Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
3T2X2
Timer2 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2T1X2
Timer1 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
1T0X2
Timer0 Clock
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
0X2
CPU Clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and all the
peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding
Hardware Secu rity Byte (HSB), Default setting, X2 is cleared.
16 7663E–8051–10/08
AT89C51RE2
17
7663E–8051–10/08
AT89C51RE2
Table 16. CKCON1 Register
CKCON1 - Clock Control Register (AFh)
Reset Val ue = XXXX XX00 b
Not bit address ab le
76543210
------SIX2_1SPIX2
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3-Reserved
2-Reserved
1 SIX2_1
Enhanced UART1 Clock (Mode 0 and 2)
(This control bit is validated when the CPU clock X2 is set; when X2 is low , this bit has no
effect).
Cleared to select 6 clock periods per peripheral clock cycle. Set to select 12 clock
periods per peripheral clock cycle.
0 SPIX2
SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit
has no effect).
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
18 7663E–8051–10/08
AT89C51RE2
Dual Data
Pointer Register
DPTR
The additional data pointer can be used to speed up code execution and reduce code size.
The dual DP TR struc ture is a way by which the chi p will spec ify the ad dress of an external da ta
memory locat ion . T here a re two 1 6- bit DPTR r eg ist ers that address the ex ternal me mor y , and a
single bit called DPS = AUXR1.0 (see Table 17) that allows the program code to switch between
them (Refer to Figure 4).
Figure 4. Use of Dual Pointer
Ext e rn a l D a ta M e mo ry
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
19
7663E–8051–10/08
AT89C51RE2
Table 17. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
Reset Value: XX0X XX0X0b
Not bit address ab le
Note: *Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
ASSEMBLY LANGUA G E
; Block move using dual data pointers
; Modifies DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @ DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST addres s
76543210
EES SP9 U2 - GF2 0 - DPS
Bit
Number Bit
Mnemonic Description
7EES
Enable Extended Stack
This bit allows the selection of the stack extended mode.
Set to enable the extended stack
Clear to disable the extended stack (default value)
6SP9
Stack Pointer 9th Bit
This bit has no eff ect when the EES bit is cleared.
Set when the stack pointer belongs to the XRAM memory space
Cleared when the stack pointer belongs to the 256bytes of internal RAM.
5U2
P4 bit addressable
Clear to map SCON_1 register at C0h sfr address
Set to map P4 port register at C0h address.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF2 This bit is a gen e r a l pur pose user f la g. *
20 Always cleared.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
20 7663E–8051–10/08
AT89C51RE2
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a sh ort (2 byte s) an d fas t (12 c loc ks) w ay to man ipula te the DPS bi t in the AUXR1 SF R.
However, note that the INC instruction does not directly force the DPS bit to a particular state,
but simply toggles it. In simple routines, such as the block move example, only the fact that DPS
is toggled in the proper sequence matters, not its actual value. In other wor ds, the block move
routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-
tion (INC AUXR1), the routine will exit with DPS in the opposite state.
21
7663E–8051–10/08
AT89C51RE2
Memory Architecture
AT89C51RE2 featu res se veral on-chip memories:
• Flash memory:
containing 128 Kbytes of program memory (user space) organized into 128 bytes pages.
•Boot ROM:
4K bytes for boot loader.
• 8K bytes internal XRAM
Physical memory
organisation
Figure 5. Physical mem ory or ganis ati on
128K bytes
Flash memory
FM0
Hardware Security (1 byte)
Column Latches (128 bytes)
user space
4K bytes
ROM
1FFFFh
00000h
RM0
Fuse C on f i gurat i on Byte ( 1 byte ) FCB
HSB
256 byt es
IRAM
XRAM
8K bytes
22 7663E–8051–10/08
AT89C51RE2
Expanded RAM
(XRAM) The AT89C51RE2 provides additional Bytes of random access memory (RAM) space for
increased data parameter handling and high level language usage.
AT89C51RE2 devices have expanded RAM in external data space configurable up to 8192bytes
(see Table 18.).
The AT89C51RE2 has internal data memory that is mapped into four separate segments.
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
addressable.
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable
only.
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
EXTRAM bit cleared in the AUXR register (see Table 18).
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addres sing only. T he Upper 128 byte s occupy the sam e
address space as the SFR. That means they have the same address, but are physically sepa-
rate from SFR space.
Figure 6. Internal and External Data Memory Address
When an instruc tion ac cess es an inter nal lo catio n above addres s 7Fh, the CPU knows whet her
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction.
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,
accesses the SFR at location 0A0h (which is P2).
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide
a part of the available XRAM as explained in Table 18. This can be useful if external
peripherals are mapped at addresses already used by the internal XRAM.
XRAM
Upper
128 bytes
Internal
Ram
Lower
128 bytes
Internal
Ram
Special
Function
Register
80h 80h
00
0FFh to 1FFFh 0FFh
00
0FFh
External
Data
Memory
0000
00FFh up to 1FFFh
0FFFFh
indirect accesses direct accesses
direct or indirect
accesses
7Fh
23
7663E–8051–10/08
AT89C51RE2
• With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in
combination with any of the registers R0, R1 of the selected bank or DPTR. An access to
XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM =
0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H
rather than external memory. An access to external data memory locations higher than the
accessible size of the XRAM will be performed with the MOVX DPTR instructions in the
same way as in the standard 80C51, with P0 and P2 as data/address busses, and P3.6 and
P3.7 as write and read timing signals. Accesses to XRAM above 0FFH can only be done by
the use of DPTR.
• With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard
80C51.MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any
output port pins can be used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs
the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order
eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either
read or write signals on P3.6 (WR) and P3.7 (RD).
The stac k pointe r (SP) may be lo cated any where in the 256 bytes RAM (lower and upper RAM)
internal da ta m emo ry. T h e s tack may be located in th e 25 6 l ower by te s o f the XRA M by activ at-
ing the extended stack mode (see EES bit in AUXR1).
The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are
extended from 6 to 30 clock periods. This is useful to access external slow peripherals.
24 7663E–8051–10/08
AT89C51RE2
Registers Table 18. AUXR Regi ster
AUXR - Auxiliary Register (8Eh)
Reset Value = XX01 1100 b
Not bit address ab le
76543210
- - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse length
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods.
4-2 XRS2:0
XRAM Size
XRS2 XRS1 XRS0 XRAM size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes
0 1 1 1024 bytes
1 0 0 1792 bytes
1 0 1 2048 bytes
1 1 0 4096 bytes
1 1 1 8192 bytes (default)
1EXTRAM
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external me m ory.
Programmed by hardware after Power-up regarding Hardware Security Byte (HSB),
default setting, XRAM selected.
0AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is
used.
25
7663E–8051–10/08
AT89C51RE2
Extended Stack The lowest bytes of the XRAM may be used to allow extension of the stack pointer.
The extended stack allows to extend the standard C51 stack over the 256 bytes of internal RAM.
When the extended stack mode is activated (EES bit in AUXR1), the stack pointer (SP) can
grow in the lower 256 bytes of the XRAM area.
The stack extens ion consi sts in a 9 bit s stac k poin ter where the ninth bi t is locate d in SP9 (bit 6
of AUXR1). The SP9 then indicates if the stack pointer belongs to the internal RAM (SP9
cleared) or to the XRAM memory (SP9 set).
To ensure ba ck wa rd com pati bi lity wi th st and ard C51 archi tec ture, the exten ded m ode is dis able
at chip reset.
Figure 7. Stack modes
Figure 8. AUXR1 register
AUXR1- Auxiliary Register 1(0A2h)
00h
FFh
0000h
FFFFh
256 bytes
IRAM 00h
FFh
Logical MCU
Address
256 SP values
rollover within 256B of IRAM 00h
FFh
0000h
256 bytes
IRAM 00h
FFh 512 SP Values
rollover in:
00FFh
00h
FFh
256B of IRAM
+
lower 256B of XRAM
XRAM
SP Value
FFFFh
Logical MCU
Address
XRAM
SP Value
Standard C51 Stack mode EES = 0 Extended Stack mode Stack EES = 1
SP9=1
SP9=0
76543210
EES SP9 U2 - GF2 0 - DPS
Bit
Number Bit
Mnemonic Description
7EES
Enable Extended Stack
This bit allows the selection of the stack extended mode.
Set to enable the extended stack
Clear to disable the extended stack (default value)
26 7663E–8051–10/08
AT89C51RE2
Reset Val ue = 00XX 00X 0b
Not bit address ab le
6SP9
Stack Pointer 9th Bit
This bit has no eff ect when the EES bit is cleared.
Set when the stack pointer belongs to the XRAM memory space
Cleared when the stack pointer belongs to the 256bytes of internal RAM. Set and
cleared by hardware. Can only be read.
5U2
P4 bit addressable
Clear to map SCON_1 register at C0h sfr address
Set to map P4 port register at C0h address.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3GF2 This bit is a gen e r a l pur pose user f la g. *
20 Always cleared.
1-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
Bit
Number Bit
Mnemonic Description
27
7663E–8051–10/08
AT89C51RE2
Flash Memo ry
General
Description The Flash mem ory increases EPROM and ROM fun ctionality wit h in-cir cuit electric al erasure
and programming. It contains 128K bytes of program memory organized in 1024 pages of 128
bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows
devices to alter their own program memory in the actual end product under software control. A
default serial loader (bootloader) program allows ISP of the Flash.
The programming does not require external high programming voltage. The necessary high pro-
gramming voltage is generated on-chip using the standard VCC pins of the microcontroller.
Features • Flash internal program memory.
• Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory
space. This configuration provides flexibility to the user.
• Default loader in Boot Flash allows programming via the serial port without the need of a
user prov ide d load er.
• Up to 64K byte external program memory if the internal program memory is disabled (EA =
0).
• Programming and erase voltage with standard 5V or 3V VCC supply.
Flash memory
organization AT89C51RE2 featu res se veral on-chip memories:
•Flash memory FM0:
containing 128 Kbytes of program memory (user space) organized into 128 bytes pages.
• Boot ROM RM0:
4K bytes for boot loader.
• 8K bytes internal XRAM
28 7663E–8051–10/08
AT89C51RE2
Physical memory
organisation Figure 9. Phy sic al mem or y organi sati on
On-Chip Flash
memory The AT89C51RE2 implements up to 128K bytes of on-chip program/code memory. Figure 9 and
Figure 1 0 shows the p artit ionin g of in ternal a nd ext ernal progra m/cod e memo ry spaces acco rd-
ing to EA value.
The memory partitioning of the 8051 core microcontroller is typical a Harvard architecture where
program and data areas are held in separate memory areas. The program and data memory
areas use the same physical address range from 0000H-FFFFH and a 8 bit instruction
code/data format.
To access more than 64kBytes of code memory, without modifications of the MCU core, and
development tools, the bank switching method is used.
The internal program memory is expanded to 128kByte in the ´Expanded Configuration’, the
data memory remains in the ´Normal Configuration´. The program memory is split into four 32
kByte ban ks (named Bank 0-2). The MCU core sti ll address es up to 64kByte s where th e upper
32Kbytes can be selected between 3 32K bytes bank of on-chip flash memory. The lower 32K
bank is used a s common area for inte rrupt subroutines, bank switching and functions calls
between banks.
The AT8 9C51R E2 als o imp lements an extra u pper 32K bank (Bank 3) t hat allow s ex ternal c ode
execution.
128K bytes
Flash memory
FM0
Hardware Security (1 byte)
Column Latches (128 bytes)
user space
Extra Row FM0 (128 bytes) 4K bytes
ROM
1FFFFh
00000h
RM0
Fuse Configuration By te( 1 by t e ) FCB
HSB
29
7663E–8051–10/08
AT89C51RE2
Figure 10. Program/Code Memory Organization EA=1
0000h
7FFFh
8000h
FFFFh
8000h
FFFFh
8000h
FFFFh
8000h
FFFFh
32K
Common
upper 32K
Bank 0 upper 32K
Bank 1 upper 32K
Bank 2
upper 32K
Bank 3
Optional
External
Memory
On-Chip flash code memory
Ext ernal code memory
00000h
07FFFh
08000h
0FFFFh
10000h
17FFFh
18000h
1FFFFh
Logical MCU
Address Physical Flash
Address Logical MCU
Address Logical MCU
Address
Physica l Flash
Address Physi cal Flash
Address Logical MCU
Address
30 7663E–8051–10/08
AT89C51RE2
When EA =0, the o n-chip flash memor y is dis abled and the MCU c ore can ad dress only up to
64kByte of external me mory (none of the on-chip flas h memory FM0 banks or RM0 can be
mapped and executed).
Figure 11. Program/Code Memory Organization EA=0
0000h
FFFFh
64K
Common
On-Chip flash code memory
External code memory
00000h
0FFFFh
Logical MCU
Address External Phys ical Memor y
Address
31
7663E–8051–10/08
AT89C51RE2
On-Chip ROM
bootloader The On-c hip ROM boot loader (RM0) is enable only for ISP operati ons after r eset (bootlo ader
execution). The RM0 memory area belongs to a logical addressable memory space called ‘Bank
Boot’.
RM0 cannot be acti vated from the On- chip flash memory. It means that it is not possible acti-
vate the Bank Boot area by software (it prevents any RM0 execution and flash corruption from
the user application).
RM0 logical area consists in an independent code execution memory area of 4K bytes starting
at logical 0x0000 address (it allows the use of the interrupts in the bootloader execution).
0000h
7FFFh
8000h
FFFFh
8000h
FFFFh
8000h
FFFFh
8000h
FFFFh
Bank 0
On-Chip flash code memory
Ext ernal code memory
00000h
07FFFh
08000h
0FFFFh
10000h
17FFFh
18000h
1FFFFh
Logical MCU
Address Physical
Address Logica l MCU
Address Logical MCU
Address
Physical
Address Physical
Address Logical MCU
Address
Bank 1 Bank 2 Bank 3
Logical MCU
Address ROM
Address
Bank
BOOT
(Ext)
0000h
On-Chip ROM memory (RM0) 1000h
0000h
1000h
32 7663E–8051–10/08
AT89C51RE2
Boot process The BRV2-0 b its of the FC B (see Table 2 0 on page 34) , the EA pi n value upon r eset and the
presence of the external hardware conditions, allow to modify the default reset vector of the
AT89C51RE2.
The Hardw are conditions (EA = 1, PSEN = 0) dur ing the Reset falling edge force the on- chip
bootload er execution . This a llows an a pplication to be buil t that will nor mally execu te the end
user’s code but can be manually forced into default ISP operation. The hardware conditions
allows to force the enter in ISP mode whatever the configurations bits.
Figure 12. Boot Reset vector configuration
EA pin Hardware conditions BRV2-0 MCU reset vector
0 X X External Code at address 0x0000
1
YES X RM0 at address 0x0000 (ATMEL Bootloader)
NO
1 1 1 FM0 at address 0x00 00 with bank0 mapped
1 1 0 FM0 at address 0xFFFC in Bank 0
1 0 1 FM0 at address 0xFFFC in Bank 1
1 0 0 FM0 at address 0xFFFC in Bank 2
0 1 1 RM0 at address 0x0000 (ATMEL Bootloader)
0 1 0 Reserved
(FM0 at address 0x0000 with bank 0 mapped)
0 0 1
0 0 0
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FM0 Memory
Architecture The FM0 flash memory is made up of 5 blocks:
1. The memory array (user space) 128K bytes
2. The Extra Row also called FM0 XAF
3. The Har dware se curi ty bits (HS B)
4. The Fuse Configuration Byte (FCB)
5. The column latch
User Space This space is composed of a 128K bytes Flash memory organized in 1024 pages of 128 bytes. It
contains the user’s appli cation code. This block ca n be access i n Read/write mode fr om FM0
and boot memor y area. ( Wh en acce ss in wr ite mode from FM 0, the CPU co re enter ps eud o idle
mode).
Extra Row (XRow or
XAF) This row is a part of FM0 and has a size of 128 bytes. The extra row (XAF) may contain informa-
tion for boot loader usage.This block can be access in Read/write mode from FM0 and boot
memory area. (When access in write mode from FM0, the CPU core enter pseudo idle mode).
Hardware security Byte
(HSB) The Hardware security Byte is a part of FM0 and has a size of 1 byte.
The 8 bits ca n be rea d/wri tten by softw ar e (f rom FM0 or RM0) and written by hardwa re in para l-
lel mode.
The HSB bits can be written to ‘0’ without any restriction (increase the security level of the chip),
but ca n be writte n to ‘1’ only when th e corre spond ing mem ory area o f the lock bi ts was full chi p
erased.
Table 19. Hardware Security Byte (HSB)
76543210
- - - - - FLB2 FLB1 FLB0
Bit
Number Bit
Mnemonic Description
7-Unused
6-4 - Reserved
3-Unused
2-0 FLB2-0 FM0 Memory Lock Bits
See Table 32 on page 52
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Fuse Configuration Byte
(FCB) The Fuse configuration byte is a part of FM0.
The 8 bits read/written by software (from FM0 or RM0) and written by hardware in parallel mode.
Table 20. Fuse Configuration Byte (FCB)
76543210
X2 - - - - BRV2 BRV1 BRV0
Bit
Number Bit
Mnemonic Description
7X2
X2 Mode
Programmed (‘0’ value) to force X2 mode (6 clocks per instruction) after reset
Unprogrammed (‘1’ value) to force X1 mode, St andard Mode, after reset (Default)
6-3 - Unused
2-0 BRV2-0-
Boot Reset Vector
These bits allow to configure the reset vector of the product according to the following
values:
1 1 1: Reset at address 0x0000 of FM0 with Bank0 mapped
1 1 0: Reset at address 0xFFFC of Bank 0
1 0 1: Reset at address 0xFFFC of Bank 1
1 0 0: Reset at address 0xFFFC of Bank 2
0 1 1: Reset at address 0x0000 of RM0 (Internal ROM bootloader execution)
0 1 0: Reserved for further extension but same as 1 1 1
0 0 1: Reserved for further extension but same as 1 1 1
0 0 0: Reserved for further extension but same as 1 1 1
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Column latches The column latches, also part of FM0, has a size of one page (128 bytes).
The column latches are the entrance buffers of the three previous memory locations (user array,
XROW, Hardware security byte and Fuse Configuration Byte).
This block is write only from FM0, RM0.
Cross Memory Access
Description overview The FM0 memory can be programmed from RM0 without entering idle mode.
Programming FM0 from FM0 makes the CPU core entering “pseudo idle” mode.
In the pseudo idle mode, the code execution is halted, the peripherals are still running (like stan-
dard idle mode) but all i nterrupt are delay ed to the end of this mode. T here are fours way s of
exiting pseudo idle mode:
• At the end of the regular flash programming operation
• Reset the chip by external reset
• Reset the chip by hardware watchdog
• Reset the chip by PCA watchdog
Programming FM0 from external memory code (EA=0 or EA=1,with Bank3 active) is impossible.
If a reset o ccurs dur in g fl ash pr og rammi ng t he ta rg et pa ge c oul d be incom pl etel y e rase d or pro-
grammed, but any other memory location (FM0, RAM, XRAM) remain unchanged.
The Table 21 shows all software flash access allowed.
Table 21. Cross Memory Access
Code executing from
Action FM0
(user Flash) RM0
(boot ROM)
FM0
(user Flash)
Read ok Denied
Load column latch ok N.A.
Write ok (pseudo idle mode) N.A.
RM0
(boot ROM)
Read ok ok
Load column latch ok N.A.
Write ok N.A.
External memory
EA = 0
or
EA=1, Bank3
Read (1)
1. Depends of general lock bits configuration
N.A. Not applicable
Denied
Load column latch Denied N.A.
Write Denied N.A.
36 7663E–8051–10/08
AT89C51RE2
Access and
Operations
Descriptions
FM0 FLASH Registers
The CPU in ter fac es to the flash m emory thr oug h th e FC ON regis te r, AU XR1 r egi ste r and F S TA
register.
These registers are used to map the columns latch, HSB, FCB and extra row in the working data
or code space.
BMSEL Register Table 22. BMSEL Register
BMSEL Register (S:92h)
Bank Memory Select
Reset Value= 0000 0YYYb (where YYY depends on BRV2:0 value in Fuse Configuration Byte)
76543210
MBO2 MBO1 MBO0 FBS2 FBS1 FBS0
Bit Number Bit
Mnemonic Description
7-5 MBO2:0
Memory Bank Operation
These bits select the target memory bank for flash write or read operation. These bits
allows to read or write the on-chip flash memory from one upper 32K bytes to another
one.
0 X X: The on-chip flash operation target banked is the same as FBS2:0
1 0 0: The target memory bank is forced to Bank0
1 0 1: The target memory bank is forced to Bank1
1 1 0: The target memory bank is forced to Bank2
1 1 1: The target memory bank is forced to Bank3 (optional External bank)
4-3 Reserved
2-0 FBS2:0
Fetch Bank Se le c t ion
These bits select the upper 32K bytes execution bank:
FBS1:0 can be read/write by software.
FBS2 is read-only by software (the Boot bank can not be mapped from FM0)
0 0 0 Bank0
0 0 1 Bank1
0 1 0 Bank2
0 1 1 Bank3 (optionnal external bank)
1 X X Boot Bank (Read only)
Upon reset FBS2:0 is initialized according to BRV2:0 configuration bits in FCB.
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FCON Register Table 23. FC ON Regi ster
FCON Register (S:D1h)
Flash Control Register
Reset Value= 0000 0000b
76543210
FPL3 FPL2 FPL1 FPL0 FPS FMOD2 FMOD1 FMOD0
Bit Number Bit
Mnemonic Description
7-4 FPL3:0 Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD2:0. (see
Table 26.)
3FPS
Flash Map Program Space
When this bit is set:
The MOVX @DPTR, A instruction writes in the columns latches space
When this bit is cleared:
The MOVX @DPTR, A instruction writes in the regular XDATA memory space
2-0 FMOD2:0 Flash Mode
These bits allow to select the target memory area and operation on FM0
See Table 25.
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FSTA Register Table 24. F S TA Regi st er
FSTA Register (S:D3h)
Flash Status Register
Reset Value = ‘R’x xx x0 00b
Where ‘R’ depends on the reset conditions: If RM0 is executed after Reset R=1, if FM0 is exe-
cuted after reset R=0
76543210
FMR - - - - FSE FLOAD FBUSY
Bit Number Bit
Mnemonic Description
7FMR
Flash Movc Redirection
When code is executed from RM0 (and only RM0), this bit allow the MOVC instruction to
be redirected to FM0.
Clear this bit to allow M O VC instruct ion to read FM0
Set this bit to allow MOVC instruction to read RM0
This bit can be written only from RM0 (on-chip ROM bootloader execution).
6-3 - unused
2FSE
Flash sequence error
Set by hardware when the flash activation sequencers FCON 5X and MOV FCON AX) is
not correct (See Error Report Section)
Clear by software or clear by hardware if the last activation sequence was correct
(previous error is canceled)
1FLOAD
Flash Columns latch loaded
Set by hardware when the first data is loaded in the column latches.
Clear by hardware when the activation sequence succeeds (flash write success, or reset
column latch success)
0 FBUSY
Flash Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be changed by software.
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Mapping of the
Memory Space By default, the user space is accessed by MOVC A, @A+DPTR instruction for read only. Setting
FPS bit in FCON register takes precedence on the EXTRAM bit in AUXR register.
The other memory spac es (u ser, ex tr a row, ha rd war e se cu rity ) are ma de ac ces si ble in the code
segment by programming bits FMOD2:0 in FCON register in accordance with Table 25. A
MOVC instruction is then used for reading these spaces.
Thanks to the columns latches access, it is possible to write FM0 array, HSB and extra row
blocks. The column latches space is made accessible by setting the FPS bit in FCON register.
Writing is possible from 0000 h to FFFFh, address bits 6 to 0 are used to select an address within
a page while bits 14 to 7 are used to select the programming address of the page.
Table 25. .FM0 blocks select bits
FMOD2 FMOD1 FMOD0 Adressable Spac e
0 0 0 FM0 array(0000h-FF FFh)
0 0 1 Extra Row(00h-80h)
0 1 0 Er a se FM 0
0 1 1 Column latches reset
100HSB
101FCB
110
Reserved
111
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AT89C51RE2
Launching flash
commands (activation
sequence)
FPL3:0 bits in FCON register are used to secure the launch of programming. A specific
sequence must be written in these bits to unlock the write protection and to launch the operation.
This seque nce is 5xh foll owed by Axh. Table 26 s ummarizes the me mory spaces to progr am
according to FMOD2:0 bits.
Table 26. FM0 Programming Sequences
Note: 1. The sequence 5xh and Axh must be executed without instructions between them otherwise
the programming is not executed (see flash status register).
2. The sequence 5xh and Axh can be executed with the different FMOD0, FMOD1 values, the
last FMOD1:0 value latches the destination target.
3. When the FMOD2 bit is set (corresponding to the serial number field code) no write operation
can be performed.
4. Only the bits corresponding to the previously “full erase” memory space can be written to one.
Wri te to FCON
OperationFPL3:0 FPS FMOD2 FMOD1 FMOD0
FM0 5 X 0 0 0 No action
A X 0 0 0 Write the column latches in FM0
XAF
FM0
5 X 0 0 1 No action
AX001
Write the column latches in FM0
extra row space
Erase FM0 5 X 0 1 0 No action
A X 0 1 0 Full erase FM0 memory area
Reset
FM0
Column
Latches
5 X 0 1 1 No action
A X 0 1 1 Reset the FM0 column latches
HSB
5 X 1 0 0 No action
AX100
Write the hardware Security byte
(HSB) See (4)
FCB
5 X 1 0 1 No action
AX101
Write the Fuse Configuration Byte
(FCB)
Reserved 5X110
No action
AX110
Reserved 5X111
AX111
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Loading the Column
Latches Any number of data from 0 byte to 128 bytes can be loaded in the column latches. The data writ-
ten in the column latches can be written in a none consecutive order. The DPTR allows to select
the address of the byte to load in the column latches.
The page address to be written (target page in F M0) is given by the last address loaded in the
column latches and when this page belongs to the upper 32K bytes of the logical addressable
MCU spac e, th e tar get me mory ban k se lecti on i s perfo rmed upon the M BO2: 0 value duri ng th e
last add ress loade d.
When 0 byt e is loaded in the c olum n la tches the activ atio n se quence (5x h, Axh in FCO N) does
not launch any operations. The FSE bit in FSTA register is set.
When a cur rent flas h write op eration is on-go ing (FB USY is set) , it is impo ssib le to load the col-
umns latches before the end of flash programming process (the write operation in the columns
latches is not performed, and the previous columns latches content is not overwritten).
When programming is launched, an automatic erase of the entire memory page is first per-
formed, then p rogr amming is effe ct ively done. T hus no pa ge or b lock era se is needed and o nly
the loade d data are programm ed in the correspo nding page . The unloa ded dat a of the ta rget
memory page are programmed at 0xFF value (automatic page erase value).
The following procedure is used to load the column latches and is summarized in Figure 13:
• Disable interrupt and map the column latch space by setting FPS bit.
• Select the target memory bank (for page address larger than 32K)
• Map the co lum n latch
• Reset the column latch
• Load the DPTR with the address to write.
• Load Accumulator register with the data to write.
• Execute the MOVX @DPTR, A instruction, and only this one (no MOVX @Ri, A).
• If needed loop the last three instructions until the page is completely loaded.
• Unmap the column latch if needed (it can be left mapped) and Enable Interrupt
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Figure 13. Column Latches Loading Procedure
Note: The l as t page address us ed w hen lo adi ng the c olu mn latch is the one used to sel ec t th e page pro-
gramming address.
Note: The value of MB02:0 during the last load gives the upper 32K bytes bank target selection.
Note: The exe cu tio n o f this sequence w hen BUSY flag is set l ead s to the no-execu tion of the write in the
column latches (the previous loaded data remains unchanged).
Wr iting the Flash
Spaces
User The following procedure is used to program the User space and is summarized in Figure 14:
• Load up to one page of data in the column latches from address 0000h to FFFFh (see
Figure 13.).
• Disable the interrupts.
• Launch the programming by writing the data sequence 50h followed by A0h in FCON
register.
The end of the programming indicated by the FBUSY flag cleared.
• Enable the interrupts.
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Extra Row The following procedure is used to program the Extra Row space and is summarized in
Figure 14:
• Load data in the column latches from address FF80h to FFFFh.
• Disable the interrupts.
• Launch the programming by writing the data sequence 51h followed by A1h in FCON
register.
The end of the programming indicated by the FBUSY flag cleared.
• Enable the interrupts.
Figure 14. Flash and Extra row Programming Procedure
Hardware Security Byte
(HSB) The following procedure is used to program the Hardware Security Byte space and is
summarized in Fi gure 15:
• Set FPS and map Hardware byte (FCON = 0x0C)
• Save and dis ab le the interru pts.
• Load DPTR at address 0000h
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
Flash
Programming
Save & Disable IT
EA= 0
Launch Programming
FCON= 50h
FCON= A0h
End Programming
Restore IT
Column Latches Loading
see Figure 13
FBusy
Cleared?
Clear Mode
FCON = 00h
XROW
Programming
Save & Disable IT
EA= 0
Launch Programming
FCON= 51h
FCON= A1h
End Programming
Restore IT
Column Latches Loading
see Figure 13
FBusy
Cleared?
Clear Mode
FCON = 00h
44 7663E–8051–10/08
AT89C51RE2
• Launch the programming by writing the data sequence 54h followed by A4h in FCON
register.
The end of the programming indicated by the FBusy flag cleared.
• Restore the interrupts
.
Figure 15. Hardware Security Byte Programming Procedure
Fuse Configuration Byte
(FCB) The following procedu re is used to p rogram the F use Config uration Byte spac e and is
summarized in Fi gure 16:
• Set FPS and map FCB (FCON = 0x0D)
• Save and dis ab le the interru pts.
• Load DPTR at address 0000h
• Load Accumulator register with the data to load.
• Execute the MOVX @DPTR, A instruction.
HSB
Programming
Launch Programming
FCON= 54h
FCON= A4 h
End Programming
RestoreIT
FBusy
Cleared?
Clear Mode
FCON = 00h
Data Load
DPTR= 00h
ACC= Data
Exec: MOVX @DPTR, A
FCON = 0Ch
Save & Disable IT
EA= 0
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AT89C51RE2
• Launch the programming by writing the data sequence 55h followed by A5h in FCON
register.
The end of the programming indicated by the FBusy flag cleared.
• Restore the interrupts
.
Figure 16. Fuse Configuration Byte Programming Procedure
Reset of columns
latches space No automatic reset of the columns latches is performed after a successful flash write
process. Resetting the columns latches during a flash write process is mandatory. User
shall impleme nt a reset of the column latch before each column latch load sequence.
FCB
Programming
Launch Programming
FCON= 55h
FCON= A5h
End Programming
RestoreIT
FBusy
Cleared?
Clear Mode
FCON = 00h
Data Load
DPTR= 00h
ACC= Data
Exec: MOVX @DPTR, A
FCON = 0Dh
Save & Disable IT
EA= 0
46 7663E–8051–10/08
AT89C51RE2
In addition, the user application can reset the columns latches space manually. The fol-
lowing procedure is used to reset the columns latches space
Launch the programming by writing the data sequence 53h followed by A3h in FCON
register (from FM0 and RM0).
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Errors Report /
Miscellaneous states
Flash Busy flag The FBUSY flag indicates on-going flash write operation.
The busy flag is set by hardware, the hardware clears this flag after the end of the programming
operation.
Flash Prog ra mming
Sequence Error When a wrong sequence is detected the FSE in FSTA is set.
The following events are considered as not correct activation sequence:
- The two “MOV FCON,5x and MOV FCON, Ax” were not consecutive, or the second instruction
differs from “MOV FCON Ax” (for example, an interrupt occurs during the sequence).
- The sequence (write flash or reset column latches) occurred with no data loaded in the column
latches
The FSE bit can be cleared:
- By software
- By hardware when a correct programming sequence occurs.
Note: Wh en a good se que nc e occurs just a fter an inc or rec t s eque nc e, th e prev io us er ror is l os t.
The user so ftware application should take car e to check the FS E bit before initiatin g a new
sequence.
Power Down Mode
Request In Power Down mo de, the on -chip fla sh memo ry is desel ected (to reduc e power con sumption ),
this leads to the lost of the columns latches content.
In this case, if columns latches were previously loaded they are reset: FLOAD bit in FSTA regis-
ter should be reset after power down mode.
If a power down mode is requested during flash programmin g (FBUSY=1), all power down
sequence instructions should be ignored until the end of flash process.
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AT89C51RE2
Reading the Flash
Spaces
User The following procedure is used to read the User space:
• Read one byte in Accumulator by executing MOVC A,@A+DPTR
Note: FCON is supposed to be reset when not needed.
Depending of the MBO2:0 bits, the MOVC A,@A+DPTR can address a specific upper 32K bytes
bank. It allows to read the 32K bytes upper On-chip flash memory from one bank to another one.
When read from the bootloader area, the user memory shall be mapped before any read access
by setting the FMR bit of the FSTA register.
By default, when the bootloader is entered by hardware conditions, the ROM area is mapped for
MOVC A ,@A+DPTR operations . It is neces sary to remap the user mem ory before each read
access.
Extra Row (XAF) The following procedure is used to read the Extra Row space and is summarized in Figure 17:
• Map the Extra Row space by writing 01h in FCON register.
• Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h
to 007Fh.
• Clear FCON to unmap the Extra Row.
Figure 17. XAF Reading Procedure
Hardware Security Byte The following procedure is used to read the Hardware Security space and is summa-
rized in Figure 18:
• Map the Hardware Security space by writing 04h in FCON register.
• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h.
• Clear FCON to unmap the Hardware Security Byte.
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Figure 18. HSB Reading Procedure
Fuse ConfigurationByte The fol lowing proc edure is used to r ead the Fus e Conf igurat ion byte and i s summari zed
in Figure 18:
• Map the FCB by writing 05h in FCON register.
• Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 & DPTR= 0000h.
• Clear FCON to unmap the Hardware Security Byte.
HSB Reading Procedure
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Operation Cross Memory Access
Space addressable in read and write are:
•RAM
• ERAM (Expanded RAM access by movx)
• XRAM (eXternal RAM)
• FM0 (user flash)
• Hardwar e byte
•XROW FM0
•Boot RM0
• Flash Column latch
The table below provide the different kind of memory which can be accessed from different code
location.
Table 27. Cross Memory Access
Sharing Instructions
Table 28. Ins tr uct ion s shared
Note: by cl: using Column Latch
Action RAM XRAM
ERAM boot RM0 FM0 HSB FCB XAF FM0
boot RM0 Read ok ok ok ok ok ok ok
Wri te ok ok - ok (RWW) ok (RWW) ok (RW W) ok (RWW)
FM0 Read ok ok - ok ok ok ok
Write ok ok - ok (idle) ok ok ok
External
memory
EA = 0
or BANK3
Read ok ok - - - - -
Write ok ok - - - - -
Action RAM XRAM RM0 CL FM0 FM0 HSB XAF FM0
Read MOV MOVX
A,@DPTR MOVC A,
@A+DPTR -MOVC A,
@A+DPTR MOVC A,
@A+DPTR MOVC A,
@A+DPTR
Write MOV MOVX
@DPTR,A -MOVX
@DPTR,A by CL
FM0 by CL
FM0 by CL
FM0
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Table 29. Write M OVX @DPTR,A
Table 30. MOVC A, @A+DPTR executed from External code EA=0
Table 31. MOVC A, @A+DPTR executed from External code EA=1, PC>=0x8000, FBS=Bank3
FPS of
FCCON EA XRAM
ERAM CL FM0
0 X winner
11winner
0winner
FMOD2:0 FBS
(Fetch) MBO
(Target) MOVC A,@A+DPTR
X X X Read External Code
FMOD2:0 MBO
(Target) DPTR MOVC A,@A+DPTR
XX < 0x8000 Depends on FLB2:0
Can Returns Random value, for secured part.
X >= 0x8000 External code read
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Flash Protection from Parallel Programmin g
The three lock bits in Hardware Security Byte (see "In-System Programming" section) are pro-
grammed according to Table 32 provide different level of protection for the on-chip flash memory
FM0.
They are set by default to level 4
Table 32. Program Lock Bit FLB2-0
Program Lock bits
U: unprogrammed
P: programmed
WARNING: Security level 2 and 3 should only be programmed after verification.
Program Lock Bits
Protection Description
Security
level FLB0 FLB1 FLB2
1 U U U No program lock features enabled.
2PUU
MOVC instruction executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset,
and further parallel programming of the Flash is disabled.
ISP allows only flash verification (no write operations are allowed) but IAP from
internal code still allowed.
3UPU
Same as 2, also verify through parallel programming interface is disabled and
ISP read operation not allowed.
4 U U P Same as 3, also external execution is disabled (external bank not accessible)
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Bootloader Architecture
Introduction The bootloader manages a communication between a host platform running an ISP tool and a
AT89C51RE2 target.
The bootloader implemented in AT89C51RE2 is designed to reside in the dedicated ROM bank.
This memory area can only be executed (fetched) when the processor enters the boot process.
The imp lementat ion of the bootl oade r is based on s tandard set of librar ies incl uding INTE L hex
based protocol, standard communication links and ATMEL ISP command set.
Figure 19. Bootloade r Func tio nal Descri ption
On the above diagram, the on-chip bootloader processes are:
• ISP Communication Management
The purpose of this process is to manage the communication and its protocol between the on-
chip bootloader and a external device. The on-chip ROM implement a serial protocol (see sec-
tion Bo otl oad er P rotoc ol ). T h is p roce ss trans la te se rial c om mun ic ati on frame (UA RT) i nto Fl as h
memory access (read, write, erase...).
• Memory Management
This process manages low level access to Flash memory (performs read and write access).
ISP Communication
Management
Specific Protocol
Communication
Management
Memory
External Host with
Memory
Bootloader
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AT89C51RE2
Bootloader
Description
Entry points After reset only one bootloader entry point is possible. This entry point stands at address 0x0000
of the boot ROM memory. This entry point executes the boot process of the bootloader.
The bootloader entry point can be selected through two processes:
At reset, if the hardware conditions are appl ied, the bootloader entry point is accessed and
executed.
At reset, if the hardware conditions are not set and the BRV2-0 is programmed ‘011’, the boot-
loader entry point is accessed and the bootprocess is started.
Boot Process
Description The boot process consists in three main operations:
• The hardware boot process request detection
• The communication link detection (Uart or OCD)
• The start-up of the bootloader
Hardware boot process
request detection The hardware boot process request is detected when the hardware conditions (under reset,
EA=1 an d PSEN=0) are r eceived by the proces sor or when no hard ware conditi on is applied
and the BRV2:0 is configured ‘011’.
Commun icati on li nk
detection Two interfaces are available for ISP:
•UART0
• OCD UART
Hardware
Boot Process
RESET
BRV=’011’
PC = RM0 @0x0000h
Communication link
Start Bootloader
Start Application
BRV=’100’
EA=1
PSEN=0
Yes
No
Yes
No
detector / initialiser
Yes
No BRV=’101’
Yes
No BRV=’110’
Yes
No
PC = FM0 Bank2
@0xFFFCh
PC = FM0 Bank1
@0xFFFCh
PC = FM0 Bank0
@0xFFFCh
PC = FM0 Bank0
@0xFFFCh
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The communication link detection is done by a circular polling on all the interfaces. On
AT89C51RE2, the ISP interfaces are all based on simple UART mechanisms (Rx, Tx).
The Rx line def ault s tate i s ‘1’ when no co mmunic ation is in progres s. A transi tion fr om ‘ 1’ to ‘0 ’
on the Rx line indic ates a start of frame.
Once one of the interface detects a starts of frame (‘0’) on its Rx line, the interface is selected
and configuration of the communication link starts.
Figure 20. Communication link Detection
Notes: 1. SF: Start of Frame (‘0’ = detected; ‘1’ = not detected)
2. In AT89C51RE2 implementation, Interface 1 refers to UART0 and Interface 2 refers to the
OCD UART interface.
Yes
No
Interf ace 1
SF = 0
Yes
No
Interf ace 2
SF = 0
Detection
Start
Interface 1
Initialisation
Interface 2
Initialisation
Start Bootloader
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AT89C51RE2
ISP Protocol
Description
Physical Layer The UART used to transmit information has the following configuration:
• Character: 8-bit data
• Parity: none
• Stop: 1 bit
• Flow control: none
• Baud rate: autobaud is performed by the bootloader to compute the baud rate chosen by the
host.
Frame Description The Serial Protocol is based on the Intel Extended Hex-type records.
Intel Hex records consist of ASCII characte rs used to represent hexadecimal values and are
summar ized bel ow.
Table 33. Intel Hex Type Frame
• Record Mark:
– Record Mark is the start of frame. This field must contain’:’.
• Record length:
– Record length specifies the number of Bytes of information or data which follows the
Record Type field of the record.
• Load Offset:
– Load Offset specifies the 16-bit starting load offset of the data Bytes, therefore this
field is used only for
– Data Program Record.
• Record Type:
– Record Type specifies the command type. This field is used to interpret the
remaining information within the frame.
• Data/Info:
– Data/Info is a variable length field. It consists of zero or more Bytes encoded as pairs
of hexadecimal digits. The meaning of data depends on the Record Type.
• Checksum:
– Checksum is the two’s complement of the 8-bit Bytes that result from converting
each pair of ASCII hexadecimal digits to one Byte of binary, thus including all field
from the Record Length field to the last Byte of the Data/Info field. Therefore, the
sum of all the ASCII pairs in a record after converting to binary , including all field from
the Record Length field to the Checksum field, is zero.
Record Mark ‘:’ Record length Load Offset Record Type Data or Info Checksum
1 byte 1 byte 2 bytes 1 bytes n byte 1 byte
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Protocol
Overview An initialization step must be performed after each Reset. After microcontroller reset, the boot-
loader waits for an autobaud sequence (see Section “Autobaud Performances”).
When the co mmunicati on is initialized the protocol depen ds on the record ty pe issued by the
host.
Communication
Initialization The host initiates the communication by sending a ’U’ character to help the bootloader to com-
pute the baudrate (autobaud).
Figure 21. Initialization
Autobaud
Performances The bootloader supports a wide range of baud rates. It is also adaptable to a wide range of oscil-
lator fr equencies. T his is ac complished by measur ing the bit-ti me of a s ingle bit in a recei ved
character. This information is then used to program the baud rate in terms of timer counts based
on the oscill ator fre quen cy .
Command Data Stream Protocol
All commands are sent usin g the same flow . To increase performance, the echo has been
removed from the bootloader response.
Figure 22. Command Flow
Each command flow may end with:
Host Bootloader
“U” Performs Autobaud
Init Communication
If (not received “U”) “U”
Communication Opened
Else Sends Back ‘U’ Character
Bootloader
":"
Sends first character of the
Frame If (not received ":")
Sends frame (made of 2 ASCII Gets frame, and sends back echo
for each received Byte
Host
Else
":" Sends echo and start
reception
charac ters per Byte )
Echo analy sis
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AT89C51RE2
• “X”: If checksum error
• “L”: If read security is set
• “P”: If program security is set
• “.”: If command ok
• byte + “.”: read byte ok
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Reading/Blank
checking memory To start the reading or blank checking operation,
Requests from Host
Answers from
Bootloader The boot loader can answer to a read command with:
• ‘Address = data ‘& ‘CR’ &’LF’ the number of data by line depends of the bootloader.
• ‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
• ‘L’ & ‘CR’ & ‘LF’ if the Security is set
The bootloader answers to blank check command:
• ‘.’ & ‘CR’ &’LF’ when the blank check is ok
• ‘First Address wrong’ ‘CR’ & ‘LF’ when the blank check is fail
• ‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
• ‘L’ & ‘CR’ & ‘LF’ if the Security is set
Changing
memory/page To change the memory selected and/or the page, the Host can send two commands.
• Select New Page to keep the same memory.
• Select Memory to change the Memory and page
Requests from Host
Answers from
Bootloader The boot loader can answer to a read command with:
• ‘. ‘& ‘CR’ &’LF’ if the command is done
• ‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
Command Record
Type Record
Length Offset Data[0] Data[1] Data[2] Data[3] Data[4]
Read selected memory 04h 05h 0000h Start Address End Address 00h
Blank Check selected memory 01h
Command Record
Type Record
Length Offset Data[0] Data[1]
Select New Page 02h 02h start
address Page (4
bits) + 0h 00h
Select Memory 04h 02h 0000 h Memory
space Page
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Programming/Erasing
memory
Requests from Host
Answers from
Bootloader The boot loader answers with:
• ‘.’ & ‘CR’ &’LF’ when the data are programmed
• ‘X’ & ‘CR’ & ‘LF’ if the checksum is wrong
• ‘P’ & ‘CR’ & ‘LF’ if the Security is set
Starting application The application can only be started by a Watchdog reset.
No answer is returned by the bootloader.
Requests from Host
Command Record
Type Record
Length Offset Data[0] Data[1] Data[2] Data[3] Data[4]
Program selected mem ory 00h nb of
data start
address xxxxx
Erase selected memory 04h 05h 0000h 00h FFh 00h 00h 02h
Command Record Type Record
Length Offset
Start application with watchdog 01h 00h 0000h
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ISP Commands description
Select Memory Space The ‘Select Memory Space’ c ommand allows to route all read, write commands to a selected
area. For each area (Family) a c ode is defined. This code corresponds to the memory area
encoded value in the INTEL HEX frame.
The area supported and there coding are listed in the table below.
Table 34. Memory Families & coding
The Bo otloade r inform ation and the sign ature are as are rea d only. T he val ue in the co ding co l-
umn is the value to report in the corresponding protocol field.
Note: * the coding number doesn’t include any information on the authorized address range of the fam-
ily. A summary of these addresses is available in appendix (See “Address Mapping” on page 67.)
Memory/Information Family coding* name
FLASH 0 MEM_FLASH
SECURITY 7 MEM_PROTECT
CONFIGURATION 8 MEM_CONF
BOOTLOADER 3 MEM_BOOT
SIGNATURE 6 MEM_SIGNATURE
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Select Page The ‘Select Page’ command allows to define a page number in the selected area. A page is
defined as a 64K linear memory space (According to the INTEL HEX format). It doesn’t corre-
sponds to a physical bank from the processor.
The following table summarizes the memory spaces for which the select page command can be
applied.
Table 35. Memory space & Select page
Memory/Information Family Comments/Restrictio n
FLASH page 0 (0->64K) and 1(64k->128k) available
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Write commands The following table summarizes the memory spaces for which the write command can be
applied.
Table 36. Memory space & Select page
In case of write command to other area, nothing is done.
The bootloader returns a Write protection (‘P’) if the SECURITY do not allow any write operation
from the bootloa der .
FLASH The program/data Flash memory area can be programm ed by the bootloader by data pages of
up to 128bytes.
If the Fla sh mem ory secur ity lev el is a t least ‘2’ (FLB2 :0 = ‘1 10’), no write op erati on can b e per-
formed through the bootloader.
Table 37. Flash Write Authorization Summary
CONFIGURATION The FCB configuration byte can always be w ritten, whatever are the securit y levels.
SECURITY The Security byte can always be written with a value that enables a protection higher than the
previous one.
If attempting to write a lower security, no action is performed and the bootloader returns a pro-
tection error code (‘P’)
Table 38. Security Write Authorization Summary
Memory/Inf ormation Fa m ily Comments/Restri c tion
FLASH need security level check
SECURITY only a higher level can be write
CONFIGURATION
Command
Security level (HSB)
FLB2:0
111 110 101 011
Write Allowed Forbidden Forbidden Forbidden
write f r om
FLB2:0
Security level (HSB)
to FLB2:0
111 110 101 011
111 Allowed Allowed Allowed Allowed
110 Forbidden Allowed Allowed Allowed
101 Forbidden Forbidden Allowed Allowed
011 Forbidden Forbidden Forbidden Allowed
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Erasing commands The erasing command is supported by the following areas:
Table 39. Memory space & Erase
Nothing is done on the other areas.
FLASH The erasing command on the Flash memory:
• erases the four physical flash memory banks (from address 0000h to 1FFFFh).
• the HSB (Hardware Security Byte) is set at NO_PROTECTION:
– FLB2.0 = ‘111’
Memory/Inf ormation Fa m ily Comments/Restri c tion
FLASH need security level check
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Blank Checking
commands The blank checking command is supported by the following areas
Table 40. Memory space & Erase
Nothing is done on the other areas.
The first not erased address is returned if the blank check is failed.
FLASH The blank checking command on the Flash memory can be done from address 0000h to
1FFFFh.
The blank check operation is only possible if the HSB (Hardware Security Byte) has a security
level lower than or equal to ‘2’ (FLB2.0 = ‘110’)
Table 41. Flash Blank check Authorization Summary
Memory/Inf ormation Fa m ily Comments/Restri c tion
FLASH need security level check
Command
Security level (HSB)
FLB2:0
111 110 101 011
Blank Check Allowed Allowed Forbidden Forbidden
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AT89C51RE2
Reading commands The reading command is supported by the following areas:
Table 42. Memory space & Select page
FLASH The reading command on the Flash memory can be done from address 000h to 1FFFFh. The
read operation is only possible if the HSB (Hardware Security Byte) has a security level lower
than or equal to ‘2’ (FLB2.0 = ‘110’)
Table 43. Flash Read Authorization Summary
CONFIGURATION The CONFIGURATION family can always be read.
SECURITY The SECURITY family can always be read.
BOOTLOADER All the field from the BOOTLOARED family can be read from the bootloader. Each bootloader
information shall be read unitary. Accesses must be done byte per byte according to the address
definition
SIGNATURE All the fie ld fr om t he S IG NA TURE family c an be re ad from the boot loa der . E ach s i gna tur e info r-
mation s hall be read unit ary. Accesse s must be done byte per by te according to the address
definition
Memory/Inf ormation Fa m ily Comments/Restri c tion
FLASH need security level check
SECURITY
CONFIGURATION
BOOTLOADER
SIGNATURE
Command
Security level (HSB)
FLB2:0
111 110 101 011
Read Allowed Allowed Forbidden Forbidden
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Start Application The start application command is used to quit the bootloader and start the application loaded.
The start application is performed by a watchdog reset.
The best way to start the applic ation from a user defined entry point is to configure the FCB
(Fuse Configuration Byte) before launching the watchdog. Then, depending on the configuration
of the BRV2:0 field, the hardware boots from the selected memory area.
ISP Command
summary
UART Protocol frames
Address Mapping Table 45. Memory Families, Addresses & Coding
Attem pting an access with any other ‘cod ing’, ‘page num ber’ or ‘Addre ss’ results in no ac tion
and no answer from the bootloader.
Table 44. Summary of frames from Host
Command Record
Type Record
Length Offset Data[0] Data[1] Data[2] Data[3] Data[4]
Program selected mem ory 00h nb of data start
address xxxxx
Start application with watchdog 01h 00h 0000h x xxxx
Select New Page 02h 02h start
address Page (4
bits) + 0h 00hxxx
Select Memory
04h
02h 0000h Memory
space Page x x x
Read selected memory
05h 0000h Start Address End Address 00h
Blank Check selected memory 01h
Erase Selected memory 00h FFh 00h 00h 02h
Memory/Parameter coding Address Page number Memory/Information
Family
FLASH 0 0 up to 0x1FFFF 0 up to 1 F LAS H
HSB 7 0 0 SECURITY
FCB 8 0 0 CONFIGURATION
Bootloader revision
3
00h
0 BOOTLOADERBoot id1 01h
Boot id2 02h
Manuf. code
6
30h
0 SIGNATURE
Family code 31h
Product name 60h
Product rev 61h
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AT89C51RE2
Timers/Counters The AT89C51RE2 implements two general-purpose, 16-bit Timers/Counters. Such are identified
as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes
as a Time r or an ev ent Coun ter. Whe n operati ng as a Ti mer, the T imer/Co unter ru ns for a pro-
gramm ed lengt h of time, then issues an i nterrupt reques t. When op erating as a Counter, th e
Timer/Counter counts negative transitions on an external pin. After a preset number of counts,
the Counter issues an interrupt request.
The various operating modes of each Timer/Counter are described in the following sections.
Timer/Counter
Operations A basic opera tion is Timer regi sters THx and TLx (x = 0, 1) connected in ca scade to form a 16-
bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 46) turns the Timer on
by allowing the selec ted input to increment TLx. When TLx overflows it increments THx; when
THx ove rflow s it sets the Time r overf low flag ( TFx) in TCON re gister . Setting the TRx does no t
clear the THx and TLx Timer registe rs. Timer regi sters ca n be accessed to obtain the current
count or to enter preset values. They can be read at any time but TRx bit must be cleared to pre-
set their values, otherwise the behavior of the Timer/Counter is unpredictable.
The C/Tx# control bit selects Timer operation or Counter operation by selecting the divided-
down peripheral clock or external pin Tx as the source for the counted signal. TRx bit must be
cleared when changing the mode of operation, otherwise the behavior of the Timer/Counter is
unpredictable.
For Timer operatio n (C/Tx# = 0), the Timer register counts the d ivided-down per ipheral clock.
The Time r re gister i s inc remente d on ce ev ery per ipher al cyc le (6 pe riphe ral cl ock p erio ds). Th e
Timer clock rate is FPER/6, i.e. FOSC/12 in standard mode or FOSC/6 in X2 mode.
For Coun ter ope ration (C /Tx# = 1), th e Timer re gister c ounts the ne gativ e transit ions on the Tx
external input pi n. The external input is sampled every peri pheral cycles. W hen the sample is
high in one cycle and low in the next one, the Counter is incremented. Since it takes 2 cycles (12
periphe ral cloc k periods ) to recogn ize a nega tive tr ansition , the maxim um count r ate is FPER/12,
i.e. FOSC/24 in standard mode or FOSC/12 in X2 m o de . T h e re ar e no r es tr ic ti o ns o n t h e d ut y cyc le
of the external inp ut signal , but to ensure that a given lev el is sampled at least once before it
changes, it should be held for at least one full peripheral cycle.
Timer 0 T imer 0 functions a s either a Timer or event Counter in four modes of opera tion. Figure 23 to
Figure 26 show the logical configuration of each mode.
Timer 0 is controlled by the four lower bits of TMOD register (see Figure 47) and bits 0, 1, 4 and
5 of TCON register (see Figure 46). TMOD register selects the method of Timer gating (GATE0),
Timer or Cou nter oper ation (T/ C0#) and mode of operat ion (M 10 and M00). T CON regis ter pro-
vides Timer 0 control functions: overflow flag (TF0), run control bit (TR0), interrupt flag (IE0) and
interrupt type control bit (IT0).
For normal T imer operation (GATE0 = 0), setting TR0 all ows TL0 to be incremented by the
selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer operation.
Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an interrupt
request.
It is important to stop Timer/Counter before changing mode.
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Mode 0 (13-bit Timer) Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0 register)
with a m odu lo 32 p re scal er i mpl em ente d with th e lowe r fi ve b its o f TL 0 r e gist er (see F i gure 2 3).
The upper three bits of TL0 register are indeterminate and should be ignored. Prescaler overflow
increments TH0 register.
Figure 23. Timer/Counter x (x = 0 or 1) in Mode 0
Mode 1 (16-bit Timer) Mode 1 conf igures Timer 0 as a 16-bi t Tim er with TH0 a nd TL0 r egist ers conn ected in ca scad e
(see Figure 24). The selected input increments TL0 register.
Figure 24. Timer/Counter x (x = 0 or 1) in Mode 1
FTx
CLOCK
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
÷ 6 Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(5 bits)
THx
(8 bits)
INTx#
Tx
See the “Clock” section
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FTx
CLOCK ÷ 6
See the “Clock” section
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AT89C51RE2
Mode 2 (8-bit Timer
with Auto-Reload) Mode 2 con figur es Timer 0 as an 8- bit Ti mer (TL0 r egis ter) that a utomati call y reload s from TH0
registe r (see Fig ure 25) . TL0 over flow sets TF0 fl ag in TC ON regis ter and reloa ds TL0 w ith the
conten ts of TH0, wh ich is pres et by soft ware. Whe n the inte rrupt re quest is serviced, ha rdware
clears TF0. The reload leaves TH0 unchanged. The next reload value may be changed at any
time by writing it to TH0 register.
Figure 25. Timer/Counter x (x = 0 or 1) in Mode 2
Mode 3 (Two 8-bit
Timers) Mode 3 configures T imer 0 such that registers TL0 and TH0 operate as separ ate 8-bit Timers
(see Figure 26). This mode is provided for applications requiring an additional 8-bit Timer or
Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD register, and TR0 and
TF0 in T CON regi ster in the norma l manne r. TH0 i s lock ed into a Timer funct ion (cou nting FPER
/6) and ta ke s o ve r use of t he Ti mer 1 int er rupt ( TF 1) and run con tr ol (TR1 ) b its. T h us , ope ratio n
of Timer 1 is restricte d when Timer 0 is in mode 3.
Figure 26. Timer/Counter 0 in Mode 3: Two 8-bit Counters
TRx
TCON reg
TFx
TCON reg
0
1
GATEx
TMOD reg
Overflow Timer x
Interrupt
Request
C/Tx#
TMOD reg
TLx
(8 bits)
THx
(8 bits)
INTx#
Tx
FTx
CLOCK ÷ 6
See the “Clock” sect ion
TR0
TCON.4
TF0
TCON.5
INT0#
0
1
GATE0
TMOD.3
Overflow Timer 0
Interrupt
Request
C/T0#
TMOD.2
TL0
(8 bits)
TR1
TCON.6
TH0
(8 bits) TF1
TCON.7
Overflow Timer 1
Interrupt
Request
T0
FTx
CLOCK ÷ 6
FTx
CLOCK ÷ 6
See the “Clock” section
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Timer 1 Timer 1 is identical to Timer 0 excepted fo r Mode 3 which is a hold-count mode. The following
comments help to understand the differences:
• Timer 1 functions as either a Timer or event Counter in three modes of operation. Figure 23
to Figure 25 show the logical configuration for modes 0, 1, and 2. Timer 1’s mode 3 is a
hold-count mode.
• T imer 1 is controlled by the four high-order bits of TMOD register (see Figure 47) and bits 2,
3, 6 and 7 of TCON register (see Figure 46). TMOD register selects the method of Timer
gating (GATE1), Ti mer or Counter operation (C/T1#) and mode of operation (M11 and M01).
TCON register provides Timer 1 control functions: overflow flag (TF1), run control bit (TR1),
interrupt flag (IE1) and interrupt type control bit (IT1).
• Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best suited for
this purpose.
• For normal Timer operation (GATE1 = 0), setting TR1 allows TL1 to be incremented by the
selected input. Setting GA TE1 and TR1 allows external pin INT1# to control T imer operation.
• Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating an
interrupt request.
• When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit (TR1).
For this situation, use T imer 1 only for applications that do not require an interrupt (such as a
Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it
off and on.
• It is important to stop Timer/Counter before changing mode.
Mode 0 (13-bit Timer) Mode 0 configures T imer 1 as a 13-bit Timer, which is s et up as an 8-bit Timer (TH1 register)
with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register (see
Figure 23). The upper 3 bits of TL1 register are ignored. Prescaler overflow increments TH1
register.
Mode 1 (16-bit Timer) Mode 1 conf igures Timer 1 as a 16-bi t Tim er with TH1 a nd TL1 r egist ers conn ected in ca scad e
(see Figure 24). The selected input increments TL1 register.
Mode 2 (8-bit Timer
with Auto-Reload) Mode 2 con fig ures Timer 1 a s a n 8-bi t T ime r (TL1 re gis ter) wit h aut oma tic r elo ad from TH1 reg-
ister o n overfl ow (see Figure 25) . TL1 o verflow s ets TF 1 fla g in TCO N reg ister an d reload s TL 1
with the contents of TH1, which is preset by software. The reload leaves TH1 unchanged.
Mode 3 (Halt) Placin g Timer 1 in mode 3 caus es it to halt an d h old it s cou nt. This can be us ed to ha lt T imer 1
when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.
Interrupt Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is
set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt rou-
tine. Inte rrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are
globally enabled by setting EA bit in IEN0 register.
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AT89C51RE2
Figure 27. Timer Interrup t System
TF0
TCON.5
ET0
IEN0.1
Timer 0
Interrupt Request
TF1
TCON.7
ET1
IEN0.3
Timer 1
Interrupt Request
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Registers Table 46. TCON Register
TCON (S:88h)
Timer/Counter Control Register
Reset Value = 0000 0000b
76543210
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit Number Bit
Mnemonic Description
7 TF1 Timer 1 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.
6TR1
Timer 1 Run Control Bit
Clear to turn off Timer/Counter 1.
Set to turn on Timer/Counter 1.
5 TF0 Timer 0 Overflow Flag
Cleared by hardware when processor vectors to interrupt routine.
Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.
4TR0
Timer 0 Run Control Bit
Clear to turn off Timer/Counter 0.
Set to turn on Timer/Counter 0.
3IE1
Interrupt 1 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT1).
Set by hardware when external interrupt is detected on INT1# pin.
2IT1
Interr upt 1 Type Control Bit
Clear to select low level active (level tri ggered) for external interrupt 1 (INT1#).
Set to select falling edge active (edge triggered) for external interrupt 1.
1IE0
Interrupt 0 Edge Flag
Cleared by hardware when interrupt is processed if edge-triggered (see IT0).
Set by hardware when external interrupt is detected on INT0# pin.
0IT0
Interr upt 0 Type Control Bit
Clear to select low level active (level tri ggered) for external interrupt 0 (INT0#).
Set to select falling edge active (edge triggered) for external interrupt 0.
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Table 47. TMOD Register
TMOD (S:89h)
Timer/Counter Mode Control Register
Notes: 1. Reloaded from TH1 at overflow.
2. Reloaded from TH0 at overflow.
Reset Value = 0000 0000b
76543210
GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00
Bit Number Bit
Mnemonic Description
7GATE1
Timer 1 Gating Control Bit
Clear to enable Timer 1 whenever T R1 bit is set.
Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.
6C/T1#
Timer 1 Counter/Timer Select Bit
Clear for Timer operation: Timer 1 counts the divided-down system clock.
Set for Counter operation: Timer 1 counts negative transitions on external pin T1.
5M11Timer 1 Mode Select Bits
M11 M01 Operating mode
0 0 Mode 0: 8-bit T imer/Counter (TH1) with 5-bit prescaler (TL1).
0 1 Mode 1: 16-bit Timer/Counter.
1 0 M ode 2: 8-bit auto-reload Tim er/ Counter (TL1)(1)
1 1 M ode 3: Timer 1 halted. Retains count
4M01
3GATE0
Timer 0 Gating Control Bit
Clear to enable Timer 0 whenever T R0 bit is set.
Set to enable Timer/Counte r 0 only while INT0# pin is high and TR0 bit is set.
2C/T0#
Timer 0 Counter/Timer Select Bit
Clear for Timer operation: Timer 0 counts the divided-down system clock.
Set for Counter operation: Timer 0 counts negative transitions on external pin T0.
1M10
Timer 0 Mode Select Bit
M10 M00 Operating mode
0 0 Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).
0 1 Mode 1: 16-bit Timer/Counter.
1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0)(2)
1 1 Mode 3: TL0 is an 8-bit T imer/Counter
TH0 is an 8-bit Time r using Timer 1’s TR0 and TF0 bits.
0M00
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AT89C51RE2
Table 48. TH0 Register
TH0 (S:8Ch)
Timer 0 High Byte Register
Reset Value = 0000 0000b
Table 49. TL0 Register
TL0 (S:8Ah)
Timer 0 Low Byte Register
Reset Value = 0000 0000b
Table 50. TH1 Register
TH1 (S:8Dh)
Timer 1 High Byte Register
Reset Value = 0000 0000b
76543210
––––––––
Bit Number Bit
Mnemonic Description
7:0 High Byte of Timer 0.
76543210
––––––––
Bit Number Bit
Mnemonic Description
7:0 Low Byte of Tim er 0.
76543210
––––––––
Bit Number Bit
Mnemonic Description
7:0 High Byte of Timer 1.
76 7663E–8051–10/08
AT89C51RE2
Table 51. TL1 Register
TL1 (S:8Bh)
Timer 1 Low Byte Register
Reset Value = 0000 0000b
76543210
––––––––
Bit Number Bit
Mnemonic Description
7:0 Low Byte of Tim er 1.
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AT89C51RE2
Timer 2 The Timer 2 in the AT89C51RE2 is the standard C52 Timer 2.
It is a 16 -bit timer/ co unt er: the count is ma intained by two eight-bi t ti mer reg is ters , T H2 a nd T L 2
are cascaded. It is controlled by T2CON (Table 52) and T2MOD (Table 53) register s. Timer 2
operation is similar to Timer 0 and Timer 1.C/T2 selects FOSC/12 (timer operation) or external pin
T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to increment by the
selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes
are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON).
Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Capture and
Baud Rate Gener at or Modes .
Timer 2 includes the following enhancements:
• Auto-reload mode with up or down counter
• Programmable clock-output
Auto-Reload Mode The auto-reload mode configures Time r 2 as a 16- bit timer or event co unter with automatic
reload. If DCEN bit in T2MOD is cleared, Timer 2 behaves as in 80C52 (refer to the Atmel C51
Microcontroller Hardware description). If DCEN bit is set, Timer 2 acts as an Up/down
timer/counter as shown in Figure 28. In this mode the T2EX pin controls the direction of count.
When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag
and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and
RCAP2L registers to be loaded into the timer registers TH2 and TL2.
When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the timer
registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The under-
flow sets TF2 flag and reloads FFFFh into the timer registers.
The EXF 2 bit toggles wh en Timer 2 overfl ows or underflo ws accordi ng to the directio n of the
count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution.
78 7663E–8051–10/08
AT89C51RE2
Figure 28. Auto-Reload Mode Up/Down Counter (DCEN = 1)
Programmable
Clock-Output In th e clock-out mode, Timer 2 oper ates as a 50%- duty-cycle, prog rammable clock generator
(See Figure 29). The input clock increments TL2 at frequency FCLK PERIPH/2.The timer repeatedly
counts to ov erfl ow fr om a lo aded value. At ov er flo w, the co nte nts of RCAP 2H and RCAP 2L r eg-
isters are loaded into TH2 and TL2.In this mode, Timer 2 overflows do not generate interrupts.
The formula gives the clock-out frequency as a function of the system oscillator frequency and
the value in the RCAP2H and RCAP2L registers:
For a 16 MHz system clock, Timer 2 has a programmable frequency range of 61 Hz
(FCLK PERIPH/216) to 4 MHz (FCLK PERI PH/4). The gen erated clock signal is brought out to T2 pin
(P1.0).
Timer 2 is programmed for the clock-out mode as follows:
• Set T2OE bit in T2MOD register.
•Clear C/T2
bit in T2CON register.
• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L
registers.
• Enter a 16-bit initial value in timer registers TH2/TL2.It can be the same as the reload value
or a different one depending on the application.
• To start the timer, set TR2 run control bit in T2CON register.
It is possibl e to use Timer 2 as a baud ra te gen er ato r and a clock gene rator si mul tan eou sl y. For
this configurati on, the baud rates and clock frequenc ies are not independent since both func-
tions use the values in the RCAP2H and RCAP2L registers.
(DOWN COUNTING RELOAD VALUE)
C/T2
TF2
TR2
T2
EXF2
TH2
(8-bit)
TL2
(8-bit)
RCAP2H
(8-bit)
RCAP2L
(8-bit)
FFh
(8-bit) FFh
(8-bit)
TOGGLE
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
FCLK PERIPH 0
1
T2CON T2CON
T2CON
T2CON
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
:6
Clock O–utFrequency FCLKPERIPH
4 65536 RCAP2H RCAP2L⁄)–(×
---------------------------------------------------------------------------------------------
=
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AT89C51RE2
Figure 29. Clock-Out Mode C/T2 = 0
:6
EXF2
TR2
OVER-
FLOW
T2EX
TH2
(8-bit)
TL2
(8-bit)
TIMER 2
RCAP2H
(8-bit)
RCAP2L
(8-bit)
T2OE
T2
FCLK PERIPH
T2CON
T2CON
T2CON
T2MOD
INTERRUPT
QD
Toggle
EXEN2
80 7663E–8051–10/08
AT89C51RE2
Registers Table 52. T2CON Register
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on T imer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Ti mer 2 interrupt
is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode
(DCEN = 1).
5 RCLK Receive Clock bit
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
Timer 2 is not used to clock the serial port.
2TR2
Tim e r 2 Run contr ol bit
Cleared to turn off Timer 2.
Set to turn on Ti mer 2.
1C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for
clock out mode.
0 CP/RL2#
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on T imer 2
overflow.
Cleared to auto-reload on Tim er 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
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Table 53. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
Reset Val ue = XXXX XX00 b
Not bit address ab le
76543210
------T2OEDCEN
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1T2OE
Timer 2 Output Enable bit
Cleared to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
0DCEN
Down Counter En a ble bit
Cleared to disable Timer 2 as up/down counter.
Set to enable Timer 2 as up/down counter.
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AT89C51RE2
Programmable
Counter Array
PCA
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/coun ters . Its adva ntages inclu de reduce d softwa re ove rhead and i mproved accurac y. Th e
PCA con sists of a ded icated timer /counter wh ich serves as the time base fo r an array of fiv e
compar e/capture modul es. Its cl ock i nput ca n be progr ammed to coun t any on e of the fol lowin g
signals:
• Peripheral clock frequency (FCLK PERIPH) ÷ 6
• Peripheral clock frequency (FCLK PERIPH) ÷ 2
• Timer 0 overflow
• External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
• Rising and/or falling edge capture
• Software timer
• High-speed output
• Pulse width modulator
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer",
page 93).
When the compar e/capture modules are p rogrammed in the capture mode , software timer, or
high spee d output mode, an in terrupt can be gen erated when the mod ule execu tes its functio n.
All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/c ounter an d comp are/capt ure mo dules s hare Por t 1 for externa l I/O. T hese pins
are listed below. If the port is not used for the PCA, it can still be used for standard I/O.
The PCA timer is a common time base for all five modules (See Figure 30). The timer count
source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 54) and can be
programmed to run at:
• 1/6 the peripheral clock frequency (FCLK PERIPH)
• 1/2 the peripheral clock frequency (FCLK PERIPH)
• The Timer 0 overflow
• The inpu t on the ECI pin (P1.2)
PCA component External I/O Pin
16-bit Counter P1.2 / ECI
16-bit Module 0 P1.3 / CEX0
16-bit Module 1 P1.4 / CEX1
16-bit Module 2 P1.5 / CEX2
16-bit Module 3 P1.6 / CEX3
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AT89C51RE2
Figure 30. PCA Timer/Counter
CIDL CPS1 CPS0 ECF
It
CH CL
16 bit up / d own counter
To PCA
modules
Fclk pe riph /6
Fclk periph / 2
T0 OVF
P1.2
Idle
CMOD
0xD9
WDTE
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
overflow
84 7663E–8051–10/08
AT89C51RE2
Table 54. CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Reset Val ue = 00XX X00 0b
Not bit address ab le
The CMOD register includes three additional bits associated with the PCA (See Figure 30 and
Table 54).
• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
• The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON
SFR) to be set when the PCA timer overflows.
The CCON regi ste r conta ins the r un c ontrol bit for the P CA and the fla gs for the PCA ti mer (CF )
and each module (Refer to Table 55).
• Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing
this bit.
• Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be
generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by
software.
• Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and
are set by hardware when either a match or a capture occurs. These flags also can only be
cleared by software.
76543210
CIDL WDTE - - - CPS1 CPS0 ECF
Bit
Number Bit
Mnemonic Description
7CIDL
Counter Id le Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6WDTE
Wa tchdog Timer Enable
Cleared to disable Wat chdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2CPS1PCA Count Pulse Sele c t
CPS1 CPS0 Selected PCA input
0 0 Internal clock fCLK PE RIPH/6
0 1 Internal clock fCLK PE RIPH /2
1 0 Timer 0 Overflow
1 1 External clock at ECI/P1.2 pin (max rate = fCLK PERIPH/ 4)
1CPS0
0ECF
PCA Enable Count e r Ov e r f low Interr upt
Cleared to disable CF bit in CCO N to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
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AT89C51RE2
Table 55. CCON Register
CCON - PCA Counter Control Register (D8h)
Reset Value = 00X0 0000b
Not bit address ab le
The watchdog timer function is implemented in module 4 (See Figure 33).
The PCA interr upt sy s tem is sh own in Figure 31.
76543210
CF CR - CCF4 CCF3 CCF2 CCF1 CCF0
Bit
Number Bit
Mnemonic Description
7CF
PCA Counter Overflow flag
Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is
set. CF
may be set by either hardware or software but can only be cleared by software.
6CR
PCA Counter Run contr ol bit
Must be cleared by software to turn the PCA counter off.
Set by software to turn the PCA counter on.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 CCF4 PCA Module 4 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
3 CCF3 PCA Module 3 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
2 CCF2 PCA Module 2 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
1 CCF1 PCA Module 1 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
0 CCF0 PCA Module 0 interrupt flag
Must be cleared by software.
Set by hardware when a match or capture occurs.
86 7663E–8051–10/08
AT89C51RE2
Figure 31. PCA Interrupt System
PCA Modules: each one of the five compare/c ap tur e mod ul es ha s s ix pos sibl e func ti ons . It ca n
perform:
• 16-bit Capture, positive-edge triggered
• 16-bit Capture, negative-edge triggered
• 16-bit Capture, both positive and negative-edge triggered
• 16-bit Software Timer
• 16-bit High Speed Output
• 8-bit Pulse Width Modulator
In addition, module 4 can be used as a Watchdog Timer.
Each mo dule in the PCA has a special functi on regist er assoc iated with i t. These r egiste rs are:
CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 56). The registers contain the
bits that control the mode that each module will operate in.
• The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the
CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the
associate d module.
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
toggle when there is a match between the PCA counter and the module's capture/compare
register.
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to
be set when there is a match between the PCA counter and the module's capture/compare
register.
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 56 shows the CCAPMn settings for the various PCA functions.
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
Module 4
Module 3
Module 2
Module 1
Module 0
ECF
PCA Timer/Counter
ECCFn CCAPMn.0CMOD.0 IE.6 IE.7
To Interrupt
priority decoder
EC EA
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AT89C51RE2
Table 56. CCAPMn Registers (n = 0-4)
CCAPM0 - PCA Module 0 Compare/Capture Control Register (0DAh)
CCAPM1 - PCA Module 1 Compare/Capture Control Register (0DBh)
CCAPM2 - PCA Module 2 Compare/Capture Control Register (0DCh)
CCAPM3 - PCA Module 3 Compare/Capture Control Register (0DDh)
CCAPM4 - PCA Module 4 Compare/Capture Control Register (0DEh)
Reset Value = X000 0000b
Not bit address ab le
76543210
- ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6ECOMn
Enable Comparator
Cleared to disable the comparator function.
Set to enable the comparator function.
5 CAPPn Capture Positive
Cleared to disable positive edge capture.
Set to enable positive edge capture.
4CAPNn
Capture Negati v e
Cleared to disable negative edge capture.
Set to enable negative edge capture.
3MATn
Match
When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the
CCFn bit in CCON to be set, flagging an interrupt.
2 TOGn
Toggle
When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the
CEXn pin to toggle.
1PWMn
Pulse Width Modulation Mod e
Cleared to disable the CEXn pin to be used as a pulse width modulated output.
Set to enable the CEXn pin to be used as a pulse width modulated output.
0 CCF0
Enable CCF interrupt
Cleared to disable compare/capture flag CCFn in the CCON register to generate an
interrupt.
Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt.
88 7663E–8051–10/08
AT89C51RE2
Table 57. PCA Module Modes (CCAPMn Registers)
There are two additional registers associated with each of the PCA modules. They are CCAPnH
and CCAPnL and thes e are th e regist ers that s tore the 16- bit coun t when a c apture occurs or a
compare should occur. When a module is used in the PWM mode these registers are used to
control the duty cycle of the output (See Table 58 & Table 59).
Table 58. CCAPnH Registers (n = 0-4)
CCAP0H - PCA Module 0 Compare/Capture Control Register High (0FAh)
CCAP1H - PCA Module 1 Compare/Capture Control Register High (0FBh)
CCAP2H - PCA Module 2 Compare/Capture Control Register High (0FCh)
CCAP3H - PCA Module 3 Compare/Capture Control Register High (0FDh)
CCAP4H - PCA Module 4 Compare/Capture Control Register High (0FEh)
Reset Value = 0000 0000b
Not bit address ab le
ECOMn CAPP n CAPNn MATn TOGn PWMm E CCF n Module Func t ion
0000000 No Operation
X10000X
16-bit capture by a positive-edge
trigger on CEXn
X01000X
16-bit capture by a negative trigger on
CEXn
X 1 1 0 0 0 X 16-bit capture by a transition on CEXn
100100X
16-bit Software Timer / Compare
mode.
1 0 0 1 1 0 X 16-bit High Speed Output
1000010 8-bit PWM
1 0 0 1 X 0 X W atchdog T imer (module 4 only)
76543210
--------
Bit
Number Bit
Mnemonic Description
7-0 - PCA Module n Compare/Capture Control
CCAPnH Value
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AT89C51RE2
Table 59. CCAPnL Registers (n = 0-4)
CCAP0L - PCA Module 0 Compare/Capture Control Register Low (0EAh)
CCAP1L - PCA Module 1 Compare/Capture Control Register Low (0EBh)
CCAP2L - PCA Module 2 Compare/Capture Control Register Low (0ECh)
CCAP3L - PCA Module 3 Compare/Capture Control Register Low (0EDh)
CCAP4L - PCA Module 4 Compare/Capture Control Register Low (0EEh)
Reset Value = 0000 0000b
Not bit address ab le
Table 60. CH Register
CH - PCA Counter Register High (0F9h)
Reset Value = 0000 0000b
Not bit address ab le
Table 61. CL Register
CL - PCA Counter Register Low (0E9h)
Reset Value = 0000 0000b
Not bit address ab le
76543210
--------
Bit
Number Bit
Mnemonic Description
7-0 - PCA Module n Compare/Capture Control
CCAPnL Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7-0 - PCA counter
CH Value
76543210
--------
Bit
Number Bit
Mnemonic Description
7-0 - PCA Counter
CL Value
90 7663E–8051–10/08
AT89C51RE2
PCA Capture Mode T o use one of the PCA modules in the capture mode ei ther one or both of the CCAPM bits
CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1)
is sampl ed for a transit ion. When a val id transiti on occurs the PCA ha rdware lo ads the valu e of
the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and
CCAPnH). If the CCFn bit fo r the modul e in the CCO N SFR and the ECCFn bi t in the CCA PMn
SFR are set then an interrupt will be generated (Refer to Figure 32).
Figure 32. PCA Capture Mode
16-bit Software
Timer/ Compare
Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in
the modul es CCAPMn r egister . The PCA time r will be compa red to the m odule's capture regi s-
ters and whe n a match oc curs an inter rupt will occur if the CC Fn (CCON SFR ) and the ECC Fn
(CCAPMn SFR) bits for the module are both set (See Figure 33).
CF CR CCON
0xD8
CH CL
CCAPnH CCAPnL
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Time r
ECOMn CCA PMn, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
Cex.n
Capture
91
7663E–8051–10/08
AT89C51RE2
Figure 33. PCA Compare Mode and PCA Watchdog Timer
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-
wise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.
Once EC OM set, writ ing CCAPnL wil l clear ECOM so that an unwan ted match do esn’t occur
while modify ing the compa re va lue. W riting to CC APnH w ill set ECOM . For this re ason, us er
software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be
controlled by accessing to CCAPMn register.
High Speed Output
Mode In this mod e the CE X o utput (on port 1) as so ci ate d wit h the P CA m odu le wi ll togg le e ach time a
match occurs between the PCA counter and the module' s capture registers. To activate this
mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See
Figure 34).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0x DA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CCON
0xD8
PCA IT
Enable
PCA cou nte r/ti mer
RESET *
CIDL CPS1 CPS0 ECF CMOD
0xD9
WDTE
Reset
Write to
CCAPnL
Write to
CCAPnH
CF CCF2 CCF1 CCF0
CR CCF3CCF4
10
92 7663E–8051–10/08
AT89C51RE2
Figure 34. PCA High Speed Output Mode
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, other-
wise an unwanted match could happen.
Once EC OM set, writ ing CCAPnL wil l clear ECOM so that an unwan ted match do esn’t occur
while modify ing the compa re va lue. W riting to CC APnH w ill set ECOM . For this re ason, us er
software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be
controlled by accessing to CCAPMn register.
Pulse Width
Modulator Mode All o f the PCA modul es ca n be used a s PW M outputs . Figur e 35 show s the P WM func tion. Th e
frequency of the output depends on the source for the PCA timer. All of the modules will have
the same frequency of output because they all share the PCA timer. The duty cycle of each
module i s indepen den tly variab le us ing the modul e's cap ture reg ister CCA PLn. W hen th e valu e
of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low,
when i t is equ al to o r great er than t he outp ut will be hi gh. Wh en CL ov erflows from FF to 00,
CCAPLn is reload ed wi th the val ue in CCAP Hn. Thi s al lo ws up dat ing the PW M wi thou t glitc hes .
The PWM an d ECOM bits in the module's CCA PMn registe r must be set to en able the PW M
mode.
CH CL
CCAPnH CCAPnL
ECOMn CCAPMn, n = 0 to 4
0xD A to 0xD E
CAPNn MATn TOGn PWMn ECCFnCAPPn
16 bit comparator Match
CF CR CCON
0xD8
CCF4 CCF3 CCF2 CCF1 CCF0
PC A IT
Enable
CEXn
PC A counter/tim er
Write to
CCAPnH
Reset
Wr i te to
CCAPnL
10
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AT89C51RE2
Figure 35. PCA PWM Mode
PCA Watchdog
Timer An on-b oard watc hdog timer i s availabl e with the PCA to i mprove the reliabi lity of th e system
without in creasing chip count. Watch dog timers are useful for sy stems that ar e susceptible to
noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be
programmed as a watchdog. However, this module can still be used for other modes if the
watchdog is not needed . Figure 33 sh ows a diagra m of how the watch dog works . The user pre-
loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit
value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be
generated. This will not cause the RST pin to be driv en high.
In order to hold off the reset, the user has three options:
1. periodically change the compare value so it will never match the PCA timer,
2. periodically change the PCA timer value so it will never match the compare values, or
3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as in option
#3. If the program counter ever goes astray, a match will eventually occur and cause an internal
reset. The second option is also not recommended if other PCA modules are being used.
Remember, the PCA timer is the time base for all modules; changing the time base for other
modules would not be a good idea. Thus, in most applications the first solution is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
CL
CCAPnH
CCAPnL
ECOMn CCA PM n, n= 0 to 4
0xDA to 0xDE
CAPNn MATn TOGn PWMn ECCFnCAPPn
8 bit comparator CEXn
“0”
“1”
Enable
PCA counter/timer
Overflow
94 7663E–8051–10/08
AT89C51RE2
Seria l I/ O P o rt The serial I/O ports in the AT89C51RE2 are compatible with the serial I/O port in the 80C52.
They provide both synchronous and asynchronous communication modes. They operates as a
Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1,
2 and 3). Asynchronous transm ission and reception can occur simultaneously and at different
baud rates
Both serial I/O port include the following enhancements:
• Framing error detection
• Automatic address recognition
As these improvem ents appl y to both UART, mo st of the time in the followi ng lines, the re won’t
be any reference to UART_0 or UART_1, but only to UART, generally speaking.
Framing Error
Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To
enable the framing bit er ror detecti on feature , set SMOD0 bit in PCON register (See Figure 3 6)
for UART 0 or set SMOD0_1 in BDRCON_1 register for UART 1 (See Figure 37).
Figure 36. UART 0 Framing Err or Bloc k Dia gra m
Figure 37. UART 1 Framing Err or Bloc k Dia gra m
When th is feature is enab led, the r eceive r check s each incoming data fram e for a va lid st op bit.
An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by
two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table
68.) bit is set.
Software may exami ne FE b it afte r eac h rece ption t o chec k fo r data er rors. Once s et, on ly s oft-
ware or a res et can clea r FE bit. S ubsequen tly re ceiv ed frames with valid s top bits canno t clear
FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See
Figure 38 and Figure 39).
To UART 0 framing error control
SM0 to UART 0 mode control (SMOD0 = 0)
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)
SCON_0 (98h)
PCON (87h)
SM0/FE SM1 SM2 REN TB8 RB8 TI RI
SM0D1 SMOD0 -POF GF1 GF0 PD IDL
To UART 1 framing error control
SM0 to UART 1 mode control (SMOD0_1 = 0)
Set FE_1 bit if stop bit is 0 (framing error) (SMOD0_1 = 1)
SCON_1 (C0h)
BDRCON_1 (87h)
SM0_1/FE_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
SM0D1_1SMOD0_1 - BRR_1 TBCK_1 RBCK_1 SPD_1 SRC_1
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AT89C51RE2
Figure 38. UART Timings in Mode 1
Figure 39. UART Timings in Modes 2 and 3
Automatic
Address
Recognition
The automatic address recognition feature is enabled when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemen ted in ha rdware, a utomati c addr ess re cogni tion en hances th e multi proces sor com mu-
nication feature by allowing the serial port to examine the address of each incoming command
frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON
register to genera te an interrupt. This ensures that the CPU is not inter rupted by command
frames addre ss ed to other devi c es .
If desired, the us er may enab le the automatic addres s recogn iti on fe ature in mode 1.In this con-
figuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received
command frame address matches the device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broad-
cast address.
Note: The multiprocessor communication and automatic address recognition features cannot be
enabled in mode 0 (i. e. setting SM2 bit in SCON register in mode 0 has no effect).
Given Address Each device has an individual add ress that is specified in SADDR register; the SADEN register
is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
addres s. The don’t -care bits pr ovide the fle xibility to add ress one or more slaves at a ti me. The
following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Data byte
RI
SMOD0=X
Stop
bit
Start
bit
RXD D7D6D5D4D3D2D1D0
FE
SMOD0=1
RI
SMOD0=0
Data byte Ninth
bit Stop
bit
Start
bit
RXD D8D7D6D5D4D3D2D1D0
RI
SMOD0=1
FE
SMOD0=1
96 7663E–8051–10/08
AT89C51RE2
Slave A:SADDR1111 0001b
SADEN1111 1010b
Given1111 0X0Xb
Slave B:SADDR1111 0011b
SADEN1111 1001b
Given1111 0XX1b
Slave C:SADDR11 11 0010b
SADEN1111 1101b
Given1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1.To communicate
with slave A only, the master must send an address where bit 0 is clear (e.g.. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves
B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111
0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1
clear, and bit 2 clear (e.g. 1111 0001b).
Broadcast Address A bro adcast ad dress is formed f rom th e logica l OR o f the S ADDR and SADEN r egisters with
zeros defined as don’t-care bits, e.g.:
SADDR0101 0110b
SADEN1111 1100b
Broadcast =SADDR OR SADEN1111 111Xb
The use of do n’t -car e bits pro vides fle xi bili ty in defi ni ng the bro adcas t add re ss, howe ve r i n most
applications, a broadcast address is FFh. The following is an example of using broadcast
addresses:
Slave A:SADDR1111 0001b
SADEN1111 1010b
Broadcast1111 1X11b,
Slave B:SADDR1111 0011b
SADEN1111 1001b
Broadcast1111 1X11B,
Slave C:SADDR=111 1 0011b
SADEN1111 1101b
Broadcast1111 1111b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of
the slaves, the master must send an address FFh. To communicate with slaves A and B, but not
slave C, the master can send and address FBh.
Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i. e. the given and broadcast
addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any
address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not
support automatic address recognition.
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AT89C51RE2
Registers Table 62. SADEN_0 Register
SADEN - Slave Address Mask Register UART 0(B9h)
Reset Value = 0000 0000b
Not bit address ab le
Table 63. SADDR_0 Register
SADDR - Slave Address Register UART 0(A9h)
Reset Value = 0000 0000b
Not bit address ab le
Table 64. SADEN_1 Register
SADEN_1 - Slave Address Mask Register UART 1(BAh)
Reset Value = 0000 0000b
Not bit address ab le
Table 65. SADDR_1 Register
SADDR_1 - Slave Address Register UART 1(AAh)
Reset Value = 0000 0000b
Not bit address ab le
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76543210
76543210
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98 7663E–8051–10/08
AT89C51RE2
Baud Rate
Selection for
UART 0 for Mode 1
and 3
The Baud Rate Gene rator for transmit and receive clocks ca n be selected separately via the
T2CON and BDRCON_0 registers.
Figure 40. Baud Rate Selection for UART 0
Table 66. Baud Rate Selection Table UART 0
TCLK
(T2CON) RCLK
(T2CON) TBCK
(BDRCON) RBCK
(BDRCON) Clock Source
UART Tx Clock Source
UART Rx
0000Timer 1Timer 1
1000Timer 2Timer 1
0100Timer 1Timer 2
1100Timer 2Timer 2
X 0 1 0 INT_BRG Timer 1
X 1 1 0 INT_BRG Timer 2
0 X 0 1 Timer 1 I NT _BRG
1 X 0 1 Timer 2 I NT _BRG
X X 1 1 INT_BRG INT_BRG
RCLK
/ 16
RBCK
INT_BRG
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock_0
/ 16
0
1
TIMER_BRG_TX
Tx Clock_0
TBCK
TCLK
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AT89C51RE2
Baud Rate
Selection for
UART 1 for Mode 1
and 3
The Baud Rate Gene rator for transmit and receive clocks ca n be selected separately via the
T2CON and BDRCON_1 registers.
Figure 41. Baud Rate Selection for UART 1
Table 67. Baud Rate Selection Table UART 1
TCLK
(T2CON) RCLK
(T2CON) TBCK_1
(BDRCON_1) RBCK_1
(BDRCON_1) Clock Source
UART Tx_1 Clock Source
UART Rx_1
0000Timer 1Timer 1
1000Timer 2Timer 1
0100Timer 1Timer 2
1100Timer 2Timer 2
X 0 1 0 INT_BRG_1 Timer 1
X 1 1 0 INT_BRG_1 Timer 2
0 X 0 1 Timer 1 I NT _BRG_1
1 X 0 1 Timer 2 I NT _BRG_1
X X 1 1 INT_BRG_1 INT_BRG_1
RCLK
/ 16
RBCK_1
INT_BRG1
0
1
TIMER1
0
1
0
1
TIMER2
INT_BRG1
TIMER1
TIMER2
TIMER_BRG_RX
Rx Clock_1
/ 16
0
1
TIMER_BRG_TX
Tx Clock_1
TBCK_1
TCLK
100 7663E–8051–10/08
AT89C51RE2
Internal Baud Rate
Generator (BRG) The AT89C51RE2 implements two internal baudrate generators. Each one is dedicated to the
corresponding UART. The configuration and operating mode for both BRG are similar. When an
internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow
depen ding on the BRL (BRL or BRL_1 regist ers) relo ad valu e, the value of SPD (o r SPD_1) bit
(Speed Mode) in BDRCON (BDRCON_1) register and the value of the SMOD1 bit in PCON
register.
Figure 42. Internal Baud Rate generator 0
Figure 43. Internal Baud Rate generator 1
• The baud rate for UART is token by formula:
SPD_0
BRG
0
1
/6
BRL_0
/2
0
1INT_BRG
BRR_0
SMOD1
auto reload counteroverflow
FPER
BRG
0
1
/6
BRL_1
/2
0
1INT_BRG1
SPD_1
BRR_1
SMOD1_1
auto reload counteroverflow
FPER
Baud_Rate = 6(1-SPD) ⋅ 32 ⋅ (256 -BRL)
2SMOD1 ⋅ FPER
BRL = 256 - 6(1-SPD) ⋅ 32 ⋅ Baud_Rate
2SMOD1 ⋅ FPER
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Table 68. SCON_0 register
SCON_0 - Serial Control Register for UART 0(98h)
Reset Value = 0000 0000b
Bit addressable
76543210
FE/SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0
Bit
Number Bit
Mnemonic Description
7
FE_0
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
SM0_0 Serial port Mode bit 0
Refer to SM1_0 for serial port mode selection.
SMOD0_0 must be cleared to enable access to the SM0_0 bit.
6 SM1_0
Serial port Mode bit 1
SM0 SM1 Mode Description Baud Rate
0 0 0 Shift Register FCPU PERIPH/6
0 1 1 8-bit UART Variable
10 29-bit UARTF
CPU PERIPH /32 or /16
1 1 3 9-bit UART Variable
5 SM2_0
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
4REN_0
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3 TB8_0 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2 RB8_0
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2_0 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI_0
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
0RI_0
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 38. and
Figure 39. in the other modes.
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AT89C51RE2
Table 69. SCON_1 Register
SCON_1 - Serial Control Register for UART 1(C0h)
Reset Value = 0000 0000b
Bit addressable
76543210
FE/SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1
Bit
Number Bit
Mnemonic Description
7
FE_1
Framing Error bit (SMOD0=1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0_1 must be set to enable access to the FE_1 bit.
SM0_1 Serial port Mode bit 0
Refer to SM1_1 for serial port mode selection.
SMOD0_1 must be cleared to enable access to the SM0_1 bit.
6 SM1_1
Serial port Mode bit 1
SM0 SM1 Mode Description Baud Rate
0 0 0 Shift Register FCPU PERIPH/6
0 1 1 8-bit UART Variable
10 29-bit UARTF
CPU PERIPH /32 or /16
1 1 3 9-bit UART Variable
5 SM2_1
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and
eventually mode 1.This bit should be cleared in mode 0.
4REN_1
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
3 TB8_1 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2 RB8_1
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2_1 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1TI_1
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the
stop bit in the other modes.
0RI_1
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 38. and
Figure 39. in the other modes.
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Table 70. Example of Comp uted Value When X2=1, SMOD1=1, SPD=1
Table 71. Example of Comp uted Value When X2=0, SMOD1=0, SPD=0
The baud rate generator can be used for mode 1 or 3 (refer to Figure 40.), but also for mode 0
for UART, thanks to the bit SRC located in BDRCON register (Table 78.)
UART Registers Table 72. SBUF_0 register
SBUF_0 - Serial Buffer Register for UART 0(99h)
Reset Val ue = XXXX XXX Xb
Table 73. BRL_0 register
BRL_0 - Baud Rate Reload Register for the internal baud rate generator 0 (9Ah)
Reset Value = 0000 0000b
Baud Rates FOSC = 16. 384 MHz FOSC = 24M Hz
BRL Error (%) BRL Error (%)
115200 247 1.23 243 0.16
57600 238 1.23 230 0.16
38400 229 1.23 217 0.16
28800 220 1.23 204 0.16
19200 203 0.63 178 0.16
9600 149 0.31 100 0.16
4800 43 1.23 - -
Baud Rates FOSC = 16. 384 MHz FOSC = 24M Hz
BRL Error (%) BRL Error (%)
4800 247 1.23 243 0.16
2400 238 1.23 230 0.16
1200 220 1.23 202 3.55
600 185 0.16 152 0.16
76543210
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104 7663E–8051–10/08
AT89C51RE2
Table 74. SBUF_1 Register
SBUF - Serial Buffer Register for UART 1(C1h)
Reset Val ue = XXXX XXX Xb
Table 75. BRL_1 Register
BRL - Baud Rate Reload Register for the internal baud rate generator 1 (BBh)
Reset Value = 0000 0000b
76543210
76543210
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Table 76. T2CON Register
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
76543210
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#
Bit
Number Bit
Mnemonic Description
7TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is
enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter
mode (DCEN = 1)
5RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if
timer 2 is not used to clock the serial port.
2TR2
Timer 2 Run control bit
Cleared to turn off timer 2.
Set to tu rn on timer 2.
1C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: FCLK PERIPH).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for
clock out mode.
0 CP/RL2#
Time r 2 C a pture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2
overflow.
Cleared to auto-reload on timer 2 overflows or negative transitions on T2EX pin if
EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
106 7663E–8051–10/08
AT89C51RE2
Table 77. PCON Register
PCON - Power Contro l Regi ste r (87h)
Reset Value = 00X1 0000b
Not bit address ab le
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect
the value of this bit.
76543210
SMOD1_0 SMOD0_0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7 SMOD1_0 Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0_0 Serial port Mode bit 0 for UART
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1PD
Power-Down mo de bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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Table 78. BDRCON_0 Register
BDRCON_0 - Baud Rate Control Register (9Bh)
Reset Valu e = XXX0 000 0b
Not bit address ab le
76543210
- - - BRR_0 TBCK_0 RBCK_0 SPD_0 SRC_0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 BRR_0 Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3 TBCK_0 Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2RBCK_0
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1 SPD_0 Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0 SRC_0 Baud Rate Sour c e select bit in Mode 0 for UART
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
108 7663E–8051–10/08
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Table 79. BDRCON_1 Register
BDRCON - Baud Rate Control Register (BCh)
Reset Value = 0000 0000b
Not bit address ab le
76543210
SMOD1_1 SMOD0_1 - BRR_1 TBCK_1 RBCK_1 SPD_1 SRC_1
Bit
Number Bit
Mnemonic Description
7 SMOD1_1 Serial port Mode bit 1 for UART 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0_1 Serial port Mode bit 0 for UART 1
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 BRR_1 Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3 TBCK_1 Transmission Baud rate Generator Selection bit for UART 1
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2RBCK_1
Reception Baud Rate Generator Selection bit for UART 1
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1 SPD_1 Baud Rate Speed Control bit for UART 1
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0 SRC_1 Baud Rate Sour c e select bit in Mode 0 for UART 1
Cleared to select FOSC/12 as the Baud Rate Generator (FCLK PERIPH/6 in X2 mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
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Interrupt
System The AT89C51RE2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1),
three timer interrupts (timers 0, 1 and 2), two serial ports interrupts, SPI interrupt, Keyboard
interrupt and the PCA global interrupt. These interrupts are shown in Figure 44.
Figure 44. Interrupt Control System
Each of the inter rupt so urce s ca n be indi vidua lly enable d or disab led b y set tin g or cl eari ng a bi t
in the Inte rrup t Ena ble reg ister (Tab le 84 and T abl e 82 ). T hi s regi ste r also con tai ns a globa l di s-
able bit, which must be cleared to disable all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by
setting or clearing a bit in the In terrupt Prio rity regi ster (Tabl e 85) an d in the Interrupt P riority
High register (Table 83 and Table 84) shows the bit values and pr iority levels associated with
each combi nat ion .
IE1
0
3
High priority
interrupt
Interrupt
polling
sequence, decreasing from
high to low priority
Low priority
interrupt
Global Disable
Individual Enable
EXF2
TF2
TI
RI
TF0
INT0
INT1
TF1
IPH, IPL
IE0
0
3
0
3
0
3
0
3
0
3
0
3
PCA IT
KBD IT
SPI IT
0
3
0
3
TI_1
RI_1
0
3
TWI IT 0
3
110 7663E–8051–10/08
AT89C51RE2
Registers Table 80. Priority Level Bit Values
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two inter rupt requests of differe nt priority levels are r eceived sim ultaneously , the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneou sly, an int ernal po lling sequ ence d eterm ines which r equest is s ervic ed. Thus withi n eac h
priority level there is a second priority structure determined by the polling sequence.
iph. x ipl . x interrupt level priority
0 0 0 (lowest)
011
102
1 1 3 (highest)
111
7663E–8051–10/08
AT89C51RE2
Table 81. IEN0 Register
IEN0 - Interrupt Enable Register (A8h)
Reset Value = 0000 0000b
Bit addressable
76543210
EA EC ET2 ES ET1 EX1 ET0 EX0
Bit
Number Bit
Mnemonic Description
7EA
Enable All interrupt bit
Cleared to disable all interrupts.
Set to enable all interrupts.
6EC
PCA in te r r upt en able bit
Cleared to disable.
Set to enable.
5ET2
Timer 2 overflow interrupt Enable bit
Cleared to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
4ES
Serial port 0 Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
3ET1
Timer 1 overflow interrupt Enable bit
Cleared to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2EX1
External interrupt 1 Enable bit
Cleared to disable external interrupt 1.
Set to enable external interrupt 1.
1ET0
Timer 0 overflow interrupt Enable bit
Cleared to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0EX0
External interrupt 0 Enable bit
Cleared to disable external interrupt 0.
Set to enable external interrupt 0.
112 7663E–8051–10/08
AT89C51RE2
Table 82. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
Reset Value = X000 0000b
Bit addressable
76543210
- PPCL PT2L PSL PT1L PX1L PT0L PX0L
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6PPCL
PCA interrupt Priority bit
Refer to PPCH for priority level.
5PT2L
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4PSL
Serial port 0 Priority bit
Refer to PSH for priority level.
3PT1L
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2PX1L
External interrupt 1 Priority bit
Refer to PX1H for priority level.
1PT0L
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0PX0L
External interrupt 0 Priority bit
Refer to PX0H for priority level.
113
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AT89C51RE2
Table 83. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
Reset Value = X000 0000b
Not bit address ab le
76543210
- PPCH PT2H PSH PT1H PX1H PT0H PX0H
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6PPCH
PCA interr upt Priority high bit.
PPCH PPCL Priority Level
0 0 Lowest
01
10
1 1 Highest
5PT2H
Timer 2 overflow interrupt Priority High bit
PT2H PT2L Priority Level
0 0 Lowest
01
10
1 1 Highest
4PSH
Serial port Priority High bit
PSH PSL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
3PT1H
Timer 1 overflow interrupt Priority High bit
PT1H PT1L Priority Level
0 0 Lowest
01
10
1 1 Highest
2PX1H
External interrupt 1 Priority High bit
PX1H PX1L Priority Level
0 0 Lowest
01
10
1 1 Highest
1PT0H
Timer 0 overflow interrupt Priority High bit
PT0H PT0L Priority Level
0 0 Lowest
0 1
10
1 1 Highest
0PX0H
External interrupt 0 Priority High bit
PX0H PX0L Priority Level
0 0 Lowest
01
10
1 1 Highest
114 7663E–8051–10/08
AT89C51RE2
Table 84. IEN1 Register
IEN1 - Interrupt Enable Register (B1h)
Reset Val ue = XXXX 00x0 b
Bit addressable
76543210
- - - - ES_1 ESPI ETWI EKBD
Bit
Number Bit
Mnemonic Description
7-Reserved
6-Reserved
5-Reserved
4-Reserved
3ES_1
Serial port 1 Enable bit
Cleared to disable serial port interrupt.
Set to enable serial port interrupt.
2ESPI
SPI interru pt Enable bit
Cleared to disable SPI interrupt.
Set to enable SPI interrupt.
1ETWI
TWI interrupt Enable bit
Cleared to disable TWI interrupt.
Set to enable TWI interrupt.
0EKBD
Keyboard interrupt Enable bit
Cleared to disable keyboard interrupt.
Set to enable keyboard interrupt.
115
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AT89C51RE2
Table 85. IPL1 Register
IPL1 - Interrupt Priority Register (B2h)
Reset Val ue = XXXX 00X0 b
Bit addressable
76543210
- - - - PSL_1 SPIL TWIL KBDL
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 PSL_1 Serial port 1 Priority bit
Refer to PSH_1 for priority level.
2SPIL
SPI interr u pt Pri o r ity bit
Refe r to SP IH fo r prio r ity level.
1TWIL
TWI interrupt Priority bit
Refer to TWIH for priority level.
0KBDL
Keyboard interrupt Priority bit
Refer to KBDH for priority level.
116 7663E–8051–10/08
AT89C51RE2
Table 86. IPH1 Register
IPH1 - Interrupt Priority High Register (B3h)
Reset Val ue = XXXX 00X0 b
Not bit address ab le
76543210
- - - - PSH_1 SPIH TWIH KBDH
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3PSH_1
Serial port 1 Priority High bit
PSH_1 PSL_1 Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
2SPIH
SPI interr u pt Pri o r ity Hig h bit
SPIH SPIL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
1TWIH
TWI interrupt Priority High bit
TWIH TWIL Priority Level
0 0 Lowest
0 1
1 0
1 1 Highest
0KBDH
Keyboard interrupt Priority High bit
KB DH KBDL Priority Level
0 0 Lowest
0 1
10
1 1 Highest
117
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AT89C51RE2
Interrupt Sources
and Vector
Addresses
Table 87. Interrupt Sources and Vector Addresses
Number Polling Priority Interrupt Source Interrupt
Request Vector
Address
0 0 Reset 0000h
1 1 INT0 IE0 0003h
2 2 Timer 0 TF0 000Bh
3 3 INT1 IE1 0013h
4 4 Timer 1 IF1 001Bh
5 6 UART0 RI+TI 0023h
6 7 Timer 2 TF2+EXF2 002Bh
7 5 PCA CF + CCFn (n = 0-4) 0033h
8 8 Keyboard KBDIT 003Bh
9 9 TWI TWIIT 0043h
10 10 SPI SPIIT 004Bh
11 11 UART1 RI_1+TI_1 0053h
118 7663E–8051–10/08
AT89C51RE2
Power Management
Introduction Two power reduction mo des are implem ented in the AT89C51RE2. Th e Idle mode and the
Power-Down mode. These modes are detailed in the following sections. In addition to these
power r eduction mod es, the clocks of the cor e and pe riph erals c an be d ynami call y divi ded by 2
using the X2 mode detailed in Section “Enhanced Features”, page 13.
Idle Mode Idle mode is a power reducti on mode that reduces the power cons umption. In this mode, pro-
gram execution halts. Idle mode freezes the clock to the CPU at known states while the
peripherals continue to be clocked. The CPU status before entering Idle mode is preserved, i.e.,
the program counter and program status word register retain their data for the duration of Idle
mode. The contents of the SFRs and RAM are also retained. The status of the Port pins during
Idle mode is detailed in Table 88.
Entering Idle Mode To enter Idle mode, set the IDL bit in PCON register (see Table 89). The AT89C51RE2 enters
Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is
the last instruction executed.
Note: If IDL bit and PD bit are set simultaneously, the AT89C51RE2 enters Power-Down mode. Then it
does not go in Idle mode when exiting Power-Down mode.
Exiting Idle Mode There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
– Hardware clears IDL bit in PCON register which restores the clock to the CPU.
Execution resumes with the interrupt service routine. Upon completion of the
interrupt service routine, program execution resumes with the instruction
immediately following the instruction that activated Idle mode. The general purpose
flags (GF1 and GF0 in PCON register) may be used to indicate whether an interrupt
occurred during normal operation or during Idle mode. When Idle mode is exited by
an interrupt, the interrupt service routine may examine GF1 and GF0.
2. Generate a reset.
– A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously . This restores the clock to the CPU. Program execution momentarily
resumes with the instruction immediately following the instruction that activated the
Idle mode and may continue for a number of clock cycles before the internal reset
algorithm takes control. Reset initializes the AT89C51RE2 and vectors the CPU to
address C:0000h.
Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-
sible fo r the Port pi ns to be accesse d. To avoid unex pected output s at the Port pin s, the i nstruc tion
immediately following the instruction that activated Idle mode should not write to a Port pin or to
the external RAM.
Power-Down Mode The Power-Down mode places the AT89C51RE2 in a very low power state. Power-Down mode
stops the oscillator, freezes all clock at known states. The CPU status prior to entering Power-
Down mod e is preserved, i.e., the prog ram counter, program status word regi ster retain the ir
data for the duration of P ower-Down mode. In addition, the SF R and RAM contents are pre-
served. The status of the Port pins during Power-Down mode is detailed in Table 88.
Note: VCC may be reduced to as low as VRET during Power-Down mode to further reduce power dissi-
pation . Take care, however, that VDD is not reduced until Power-Down mode is invoked.
119
7663E–8051–10/08
AT89C51RE2
Entering Power-Down
Mode To enter Pow er -Down mod e, s et PD bi t in P CO N reg ister . Th e AT 89C5 1RE 2 e nters th e P owe r-
Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is
the last instruction executed.
Exiting Power-Down
Mode Note: If VCC was reduced during the Power-Down mode, do not exit Power-Down mode until VCC is
restored to the norm al ope rati ng lev el .
There are two ways to exit the Power-Down mode:
1. Generate an enabled external interrupt.
– The AT89C51RE2 provides capability to exit from Power-Down using INT0#, INT1#.
Hardware clears PD bit in PCON register which starts the oscillator and restores the
clocks to the CPU and peripherals. Using INTx# input, execution resumes when the
input is r eleased (see Figure 45). Execution resumes with the interrupt service
routine. Upon completion of the interrupt service routine, program execution
resumes with the instruction immediately following the instruction that activated
Power-Down mode.
Note: The external interrupt used to exit Power-Down mode must be configured as level sensitive
(INT0# and INT1#) and must be assigned the hi ghest priority. In addition, the duration of the inter-
rupt must be long enough to allow the oscillator to stabilize. The execution will only resume when
the interrupt is deasserted.
Note: Exit from power-down by external interrupt does not affect the SFRs nor the internal RAM content.
Figure 45. Power-Down Exit Waveform Using INT1:0#
2. Generate a reset.
– A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU and
peripherals. Program execution momentarily resumes with the instruction
immediately following the instruction that activated Power-Down mode and may
continue for a number of clock cycles before the internal reset algorithm takes
control. Reset initializes the AT89C51RE2 and vectors the CPU to address 0000h.
Note: During the time that execution resumes, the internal RAM cannot be accessed; however, it is pos-
sible fo r the Port pi ns to be accesse d. To avoid unex pected output s at the Port pin s, the i nstruc tion
immediately following the instruction that activated the Power-Down mode should not write to a
Port pin or to the external RAM.
Note: Exit from power-down by reset redefines all the SFRs, but does not affect the internal RAM
content.
INT1:0#
OSC
Power-down phase Oscillator restart phase Active phaseActive phase
120 7663E–8051–10/08
AT89C51RE2
Table 88. Pin Conditions in Special Operating Modes
Mode Port 0 Port 1 Port 2 Port 3 Port 4 ALE PS EN#
Reset Floating High High High High High High
Idle (internal
code) Data Data Data Data Data High High
Idle (external
code) Floating Data Data Data Data High High
Power-Down
(internal
code) Data Data Data Data Data Low Low
Power-Down
(external
code) Floating Data Data Data Data Low Low
121
7663E–8051–10/08
AT89C51RE2
Registers Table 89. PCON Register
PCON (87:h) Powe r configuration Regi st er
Rese t Valu e= XXXX 0000b
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit
Mnemonic Description
7SMOD1
Serial Port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Port Mode bit 0
Cleared to select SM0 bit in SCON register .
Set to select FE bit in SCON register .
5 - reserved
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by
software.
3GF1
General Purpose flag 1
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
2GF0
General Purpose flag 0
One use is to indicate whether an interrupt occurred during normal operation or during
Idle mode.
1PD
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD ta k es precedence.
0IDL
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
If IDL and PD are both set, PD ta k es precedence.
122 7663E–8051–10/08
AT89C51RE2
Oscillator To optimize the power consumption and execution time needed for a specific task, an internal
prescaler feature has been implemented between the oscillator and the CPU and peripherals.
Registers Table 90. CKRL Register
CKRL – Clock Reload Register (97h)
Reset Value = 1111 1111b
Not bit address ab le
Table 91. PCON Register
PCON – Power Control Register (87h)
Reset Value = 00X1 0000b Not bit addressable
76543210
CKRL7 CKRL6 CKRL5 CKRL4 CKRL3 CKRL2 CKRL1 CKRL0
Bit Number Mnemonic Description
7:0 CKRL Clock Reload Register
Prescaler value
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit Number Bit Mnemonic Description
7SMOD1
Serial Por t Mo de bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial Por t Mo de bit 0
Cleared to select SM0 bit in SCON register .
Set to select FE bit in SCON register .
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-off Flag
Cleared by software to recognize the next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be
set by software.
3GF1
Genera l-purpos e Fla g
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
2GF0
Genera l-purpos e Fla g
Cleared by software for general-purpose usage.
Set by software for general-purpose usage.
1PD
Power-do wn Mod e bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle Mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
123
7663E–8051–10/08
AT89C51RE2
Functional Block Diagram
Figure 46. Functional Oscillator Block Diagram
Prescaler Divider • A hardware RESET puts the prescaler divider in the follo wing state:
• CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature)
• Any value between FFh down to 00h can be written by software into CKRL register in order
to divide frequency of the selected oscillator:
• CKRL = 00h: minimum frequency
FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC/ 510 (X2 Mode)
• CKRL = FFh: maximum frequency
FCLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode)
FCLK CPU = FCLK PERIPH = FOSC (X2 Mode)
FCLK CPU and FCLK PERIPH
In X2 Mode, for CKRL<>0xFF:
In X1 Mode, for CKRL<>0xFF then:
Xtal2
Xtal1
Osc
CLK
Idle
CPU Clock
CKRL
Reload
8-bit
Prescaler-Divider
Reset
Peripheral Clock
:2
X2
0
1
FOSC
CKCON0
CLK
Periph
CPU
CKRL = 0xFF?
0
1
FCPU F=CLKPERIPH FOSC
2 255 CKRL–()×
-----------------------------------------------=
FCPU F=CLKPERIPH FOSC
4 255 CKRL–()×
-----------------------------------------------=
124 7663E–8051–10/08
AT89C51RE2
Hardware
Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT
(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user
must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is
enabled, it wil l inc reme nt every mach ine cy cl e whi le the osci ll ato r is runnin g and t here is no way
to dis able th e WDT exc ept thro ugh reset (e ither ha rdwar e reset or WDT ov erflow reset ). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
Using the WDT To enable the WDT, user must write 01EH and 0E1H in s equence to the WDTRST, SFR loca-
tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to
WDTRST to av oid WD T overflo w. The 14-bi t c ount er overflo ws when it reaches 163 83 (3FFFH)
and this will reset the device. When WDT is enabled, it will increment every machine cycle while
the oscillator is running. This means the user must reset the WDT at least every 16383 machine
cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write
only register. The WDT counter cannot be read or written. When WDT overflows, it will generate
an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TCLK PERIPH, where
TCLK PERIPH= 1/ FCLK PERIPH. To make the best use of the WDT, it should be serviced in those sec-
tions of code that will periodically be executed within the time required to prevent a WDT reset.
To have a m ore powerf ul WDT , a 27 coun ter has bee n added to ex tend the Time-ou t capab ility,
rankin g fro m 1 6ms to 2s @ F OSCA = 12M Hz. To mana ge this feat ure, refer to WD TPRG register
description, Table 92.
Table 92. WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Val ue = XXXX XXX Xb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
76543210
--------
125
7663E–8051–10/08
AT89C51RE2
Table 93. WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset value = XXXX X000
WDT During Power
Down and Idle In Power Down mode the os cillator sto ps, which m eans the WDT al so stops. Whil e in Power
Down mode the user does not ne ed to serv ice the WD T. Th ere are 2 me thods of ex iting Power
Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior
to entering Power Down mode. When Power Down is exited with hardware reset, servicing the
WDT should occur as it normally should whenever the AT89C51RE2 is reset. Exiting Power
Down with an interrupt is significantly different. The interrupt is held low long enough for the
oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the
WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the
interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.
To ens ure th at the WDT doe s n ot ov erflo w withi n a few sta tes o f ex it ing of powerdown , it i s b et-
ter to reset the WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
AT89C51 RE2 whil e in Idl e mo de, the use r shoul d al ways s et up a ti mer that wi ll period ic al ly exi t
Idle, service the WDT, and re-enter Idle mode.
76543210
-----S2S1S0
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6-
5-
4-
3-
2S2
WDT Time-out select bit 2
1S1WDT Time-out select bit 1
0S0WDT Time-out select bit 0
S2 S1 S0 Selected Time-out
00 0 (2
14 - 1) machine cycles, 16. 3 ms @ FOSCA =12 MHz
00 1 (2
15 - 1) machine cycles, 32.7 ms @ FOSCA=12 MHz
01 0 (2
16 - 1) machine cycles, 65. 5 ms @ FOSCA=12 MHz
01 1 (2
17 - 1) machine cycles, 131 ms @ FOSCA=12 MHz
10 0 (2
18 - 1) machine cycles, 262 ms @ FOSCA=12 MHz
10 1 (2
19 - 1) machine cycles, 542 ms @ FOSCA=12 MHz
11 0 (2
20 - 1) machine cycles, 1.05 s @ FOSCA=12 MHz
11 1 (2
21 - 1) machine cycles, 2.09 s @ FOSCA=12 MHz
126 7663E–8051–10/08
AT89C51RE2
Reduced EMI
Mode The AL E si gnal is u sed to demu ltiple x ad dres s and data buses on p ort 0 when used with exter-
nal program or data m emory. Never theless, du ring internal c ode execu tion, ALE s ignal is s till
generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.
The AO bit is located in AU XR register at bit loc ation 0. As soo n as AO is set, ALE is no longer
output bu t remains active during MOVX and MOV C instruct ions and ex ternal fetch es. During
ALE disabling, ALE pin is weakly pulled high.
Table 94. AUXR Register
AUXR - Auxiliary Register (8Eh)
Reset Value = XX00 10’HSB. XRAM’0b
Not bit address ab le
76543210
- - M0 XRS2 XRS1 XRS0 EXTRAM AO
Bit
Number Bit
Mnemonic Description
7-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5M0
Pulse length
Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods
(default).
Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods.
4XRS2
XRAM Size
XRS2 XRS1 XRS0 XRAM size
0 0 0 256 bytes
0 0 1 512 bytes
0 1 0 768 bytes(default)
0 1 1 1024 bytes
1 0 0 1792 bytes
3XRS1
2XRS0
1EXTRAM
EXTRAM bit
Cleared to access internal XRAM using movx @ Ri/ @ DPTR.
Set to access external mem ory.
Programmed by hardware after Power-up regarding Hardware Security Byte (HSB),
default setting, XRAM selected.
0AO
ALE Output bit
Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is
used.
127
7663E–8051–10/08
AT89C51RE2
Keyboard
Interface The AT89C51RE2 implements a keyboard interface allowing the connection of a
8 x n matri x keyboar d. It is based on 8 in puts with pr ogramma ble interru pt capabilit y on both
high or low level. These inputs are available as alternate function of P1 and allow to exit fr om
idle and power down modes.
The keyboa rd inte rface int erfaces with the C51 core thro ugh 3 spe cial func tion re giste rs: KBLS ,
the Key board Level Selec tion re giste r (Table 97), KB E, Th e Keybo ard inter rupt Enable regist er
(Table 96), and KBF, the Keyboard Flag register (Table 95).
Interrupt T he keyb oard in puts are cons ider ed as 8 indep endent int errupt so urce s sh aring the sam e inte r-
rupt vector . An inte rrupt ena ble bi t (KBD in IE1) a llows gl obal en able or d isable of the key board
interrupt (see Figure 47). As detailed in Figure 48 each keyboard input has the capability to
detect a pr ogram mable lev el accor ding to KB LS. x bit v alue. Lev el detect ion is the n report ed in
interrupt flags KBF. x that can be masked by software using KBE. x bits.
This structure allow keyboard arrangement from 1 by n to 8 by n matrix and allow usage of P1
inputs for othe r purpo se .
Figure 47. Keyboard Interface Block Diagram
Figure 48. Keyboard Input Circuitry
Power Reduction
Mode P1 inputs allow exit from idle and power down modes as detailed in Sec tion “P ower Manage-
ment”, page 118.
P1:x
KBE. x
KBF . x
KBLS. x
0
1
Vcc
Internal Pullup
P1.0
Keyboard Interface
Interrupt Request
KBD
IE1
Input Circuitry
P1.1 Input Circuitry
P1.2 Input Circuitry
P1.3 Input Circuitry
P1.4 Input Circuitry
P1.5 Input Circuitry
P1.6 Input Circuitry
P1.7 Input Circuitry
KBDIT
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Registers Table 95. KBF Register
KBF-Keyboard Flag Register (9Eh)
Reset Value= 0000 0000b
76543210
KBF7 KBF6 KBF5 KBF4 KBF3 KBF2 KBF1 KBF0
Bit Number Bit
Mnemonic Description
7KBF7
Keyboard line 7 flag
Set by hardware when the Port line 7 detects a programmed level. It generates a
Keyboard interrupt request if the KBKBIE. 7 bit in KBIE register is set.
Must be cleared by software.
6KBF6
Keyboard line 6 flag
Set by hardware when the Port line 6 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 6 bit in KBIE register is set.
Must be cleared by software.
5KBF5
Keyboard line 5 flag
Set by hardware when the Port line 5 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 5 bit in KBIE register is set.
Must be cleared by software.
4KBF4
Keyboard line 4 flag
Set by hardware when the Port line 4 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 4 bit in KBIE register is set.
Must be cleared by software.
3KBF3
Keyboard line 3 flag
Set by hardware when the Port line 3 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 3 bit in KBIE register is set.
Must be cleared by software.
2KBF2
Keyboard line 2 flag
Set by hardware when the Port line 2 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 2 bit in KBIE register is set.
Must be cleared by software.
1KBF1
Keyboard line 1 flag
Set by hardware when the Port line 1 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 1 bit in KBIE register is set.
Must be cleared by software.
0KBF0
Keyboard line 0 flag
Set by hardware when the Port line 0 detects a programmed level. It generates a
Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set.
Must be cleared by software.
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Table 96. KBE Register
KBE-Keyboard Input Enable Register (9Dh)
Reset Value= 0000 0000b
76543210
KBE7 KBE6 KBE5 KBE4 KBE3 KBE2 KBE1 KBE0
Bit
Number Bit
Mnemonic Description
7KBE7
Keyboard li ne 7 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 7 bit in KBF register to generate an interrupt request.
6KBE6
Keyboard li ne 6 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 6 bit in KBF register to generate an interrupt request.
5KBE5
Keyboard li ne 5 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 5 bit in KBF register to generate an interrupt request.
4KBE4
Keyboard li ne 4 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 4 bit in KBF register to generate an interrupt request.
3KBE3
Keyboard li ne 3 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 3 bit in KBF register to generate an interrupt request.
2KBE2
Keyboard li ne 2 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 2 bit in KBF register to generate an interrupt request.
1KBE1
Keyboard li ne 1 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 1 bit in KBF register to generate an interrupt request.
0KBE0
Keyboard li ne 0 Enable bit
Cleared to enable standard I/O pin.
Set to enable KBF. 0 bit in KBF register to generate an interrupt request.
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Table 97. KBLS Regi s ter
KBLS-Keyboard Level Selector Register (9Ch)
Reset Value= 0000 0000b
76543210
KBLS7 KBLS6 KBLS5 KBLS4 KBLS3 KBLS2 KBLS1 KBLS0
Bit Number Bit
Mnemonic Description
7KBLS7
Keyboard line 7 Level Selection bit
Cleared to enable a low level detection on Port line 7.
Set to enable a high level detection on Port line 7.
6KBLS6
Keyboard line 6 Level Selection bit
Cleared to enable a low level detection on Port line 6.
Set to enable a high level detection on Port line 6.
5KBLS5
Keyboard line 5 Level Selection bit
Cleared to enable a low level detection on Port line 5.
Set to enable a high level detection on Port line 5.
4KBLS4
Keyboard line 4 Level Selection bit
Cleared to enable a low level detection on Port line 4.
Set to enable a high level detection on Port line 4.
3KBLS3
Keyboard line 3 Level Selection bit
Cleared to enable a low level detection on Port line 3.
Set to enable a high level detection on Port line 3.
2KBLS2
Keyboard line 2 Level Selection bit
Cleared to enable a low level detection on Port line 2.
Set to enable a high level detection on Port line 2.
1KBLS1
Keyboard line 1 Level Selection bit
Cleared to enable a low level detection on Port line 1.
Set to enable a high level detection on Port line 1.
0KBLS0
Keyboard line 0 Level Selection bit
Cleared to enable a low level detection on Port line 0.
Set to enable a high level detection on Port line 0.
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2-wire Interface (TWI) Th is section describes the 2-wire inter face. The 2-wire bus is a bi- directional 2-wire
serial communication standard. It is designed primarily for simple but efficient integrated
circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA
(Serial Data) that ca rry info rmation b etween the ICs con nected to them. The s erial da ta
transf er i s lim ited to 40 0 Kbi t/s in st anda rd m ode. Variou s c ommun icat ion conf igura tion
can be d esign ed usin g this bu s. Fi gure 49 shows a typica l 2-wir e bus co nfigura tion . All
the devices connected to the bus can be master and slave.
Figure 49. 2- wire Bus Confi gurati on
SCL
SDA
device2device1 deviceN
device3 ...
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Figure 50. Block Diagram
Address Regi ster
Comparator
Timing &
Control
logic
Arbitration &
Sink Logic
Serial clock
generator
Shift Register
Control Register
Status Register
Status
Decoder
Input
Filter
Output
Stage
Input
Filter
Output
Stage
ACK
Status
Bits
8
8
7
8
Internal Bus
Timer 1
overflow
FCLK PERIPH/4
Interrupt
SDA
SCL
SSADR
SSCON
SSDAT
SSCS
PI2.1
PI2.0
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Description The C PU inte rface s to the 2-wire logic via the fo llowi ng four 8-bit sp ecia l funct ion r egis-
ters: the Synchronous Serial Control register (SSCON; Table 107), the Synchronous
Serial Data reg ister (SSDA T; Table 108), th e Synchron ous Serial Contro l and Status
register (SSCS; Table 109) and the Synchronous Serial Address register (SSADR Table
112).
SSCON is u sed to enable the TWI i nterface , to pr ogram the bit ra te (see Tab le 100 ), to
enable slav e modes, to ackn owledge or not a rece ived data, to send a START or a
STOP condi tion on the 2-wir e bus, and to acknowledge a s erial interrupt. A hardware
reset disables the TWI module.
SSCS contains a status code which reflects the status of the 2-wire logic and the 2-wire
bus. The three least significant bits are always zero. The five most significant bits con-
tains the status code. There are 26 possible status codes. When SSCS contains F8h,
no relevant state information is available and no serial interrupt is requested. A valid sta-
tus code is availabl e in SSCS one machine cycle after SI is set by hard ware and is still
present one machine cycle after SI has been reset by software. to Table 106. give the
status for the master modes and miscellaneous states.
SSDAT conta ins a byte of serial data to be transmi tted or a byte which has just been
received . It is address able wh ile it is not in proc ess of s hiftin g a byt e. This occurs when
2-wire logic is in a d efined state and the serial interrupt flag is set. Data in SSDAT
remains stable as long as S I is set. While data is being shifted out, data on the bus is
simultaneously shifted in; SSDAT always contains the last byte present on the bus.
SSADR may be loaded with the 7-bit slave address (7 most significant bits) to which the
TWI module will respond when programmed as a slave transmitter or receiver. The LSB
is used to enable general call address (00h) recognition.
Figure 51 shows how a data transfer is accomplished on the 2-wire bus.
Figure 51. Complete Data Transfer on 2-wire Bus
The four operati ng mod es are:
• Master Transmitter
• Master Receiver
• Slave transmitter
•Slave receiver
Data trans fer in each mo de of operatio n is sho wn in Tab le to Table 106 and Figure 52.
to Figure 55.. These figures contain the following abbreviations:
S : START condition
R: Read bit (high level at SDA)
SDA
SCL S
start
condition
MSB
12 789
ACK
acknowledgement
signal from receiver acknowledgement
signal from receiver
123-8 9
ACK stop
condition
P
clock line held low
while interrupts are serviced
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W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P : STOP condition
In Figure 52 to Figure 55, circles are used to indicate when the serial interrupt flag is set.
The numbers in the circles show the status code held in SSCS. At these points, a ser-
vice routine must be executed to continue or complete the serial transfer. These service
routine s are no t crit ical sin ce the serial t ransfer is suspe nded unti l the s erial i nterrupt
flag is cleared by software.
When the serial int errupt ro utine is entered, the status c ode in SSCS i s used to bra nch
to the app ropriate service routi ne. For ea ch status code, t he required software ac tion
and details of the following serial transfer are given in Table to Table 106.
Master Tr ansmitter Mode In the master transmitter mode, a number of data bytes are transmitted to a slave
receiver (Figure 52) . Before th e master tr ansmitter mode can be entered , SSCON mus t
be initialised as follows:
CR0, CR1 and CR2 define the in ternal seri al bit rate if extern al bit rate gen erator is not
used. SSIE must be set to enable TWI. STA, STO and SI must be cleared.
The maste r transmit ter mode may no w be entered by settin g the STA bit. Th e 2-wire
logic will now test the 2-wire bus and generate a START condition as soon as the bus
becomes free . W hen a ST A RT con diti on is t ra nsmi tted, the s er ia l inte r ru pt f lag ( SI bi t in
SSCON) is set, and the status code in SSCS will be 08h. This status must be used to
vector to an interrupt routine that loads SSDAT with the slave address and the data
direction bit (SLA+W).
When the slave ad dress and th e direct ion bit have been trans mitted and an acknow l-
edge ment bi t has bee n rece ived, SI is se t again and a numb er of st atus co de in SS CS
are possible. There are 18h, 20h or 38h for the master mode and also 68h, 78h or B0h if
the sl ave mod e was en abled (AA=lo gic 1). The appr opriat e actio n to be ta ken f or each
of these sta tus code is detaile d in Table . Th is scheme is repeate d until a STO P condi-
tion is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may
switch to the master receiver mode by loading SSDAT with SLA+R.
Master Receiver Mode In the master receiver mode, a number of data bytes are received from a slave transmit-
ter (Figure 53). The transfer is initialized as in the master transmitter mode. When the
START co ndition has bee n transmitte d, the interrup t routine mu st load SSDAT w ith the
7-bit sla ve addres s and the da ta direction bit (SLA+ R). The seri al interr upt flag SI must
then be cleared before the serial transfer can continue.
Table 98. SSCON Initialization
CR2 SSIE STA STO SI AA CR1 CR0
bit rate 1 0 0 0 X bit rate bi t rate
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When the slave ad dress and th e direct ion bit have been trans mitted and an acknow l-
edgement bit has been receiv ed, the serial interrupt flag is set again and a number of
status code in SSC S are possibl e. There ar e 40h, 48h or 38h for the mas ter mode an d
also 68h, 78h or B0h if the sla ve mode was enabled (AA=logic 1). The app ropriate
action to be ta ken for each of th ese status code is detailed in Tabl e . Th is schem e is
repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table 7 to Table 11. After a repeated START condition (state 10h) the TWI module may
switch to the master transmitter mode by loading SSDAT with SLA+W.
Slave Receiver Mode In the slave receiver mode, a number of data bytes are received from a master transmit-
ter (Figure 54). To initiate the slave receiver mode, SSADR and SSCON must be loaded
as follows:
The upper 7 bits are the address to which the TWI module will respond when addressed
by a ma ster. If the LSB (GC) is set the TWI module wil l respond to the general call
address (00h); otherwise it ignores the general call address.
CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable the
TWI. The AA bit must be set to enable the own slave address or the general call address
acknowledgement. STA, STO and SI must be cleared.
When SSADR and SSCON have been initialised, the TWI module waits until it is
addres sed b y i ts ow n sla ve addres s f ollowed by the data direc tion bi t whi ch mus t be at
logic 0 (W) for the TWI to ope rate in the slave receiver mode. After its own slave
address and the W bit have been received, the serial interrupt flag is set and a valid sta-
tus code c an be read from SS CS. This stat us code is used t o vector to an interrupt
service routine.The appropriate action to be taken for each of these status code is
detailed in Table . The slave receiver mode may also be entered if arbitration is lost
while TWI is in the master mode (states 68h and 78h).
If the AA bit is reset during a transfer, TWI module will return a not acknowledge (logic 1)
to SDA after the next received data byte. While AA is reset, the TWI module does not
respond to its own slave address. However, the 2-wire bus is still monitored and
addres s recog nition ma y be resum e at any time by setting AA . This mean s that the AA
bit may be used to temporarily isolate the module from the 2-wire bus.
Slave Tra nsmit ter Mo de In the slave transmitter mode, a number of data bytes are transmitted to a master
receiver (Figure 55). Data transfer is initialized as in the slave receiver mode. When
SSADR and SSCON have been initialized, the TWI module waits until it is addressed by
Table 99. SSADR: Slave Receiver Mode Initialization
A6 A5 A4 A3 A2 A1 A0 GC
own slave address
Table 100. SSCON: Slave Receiver Mode Initia lization
CR2 SSIE STA STO SI AA CR1 CR0
bit rate 1 0 0 0 1 bit rate bi t r a te
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its own sl ave addres s followed by the data direction bit which must be at logic 1 (R) for
TWI t o ope rate i n the sl ave tr ansm itter mo de. A fter i ts o wn s lave a ddre ss an d the R bi t
have been received, the serial interrupt flag is set and a valid status code can be read
from SSCS. This status code is used to vector to an interrupt service routine. The appro-
priate action to be taken for each of these status code is detailed in Table . T he slave
transmitter mode may also be entered if arbitration is lost while the TWI module is in the
maste r mode.
If the AA bit is reset during a transfer, the TWI module will transmit the last byte of the
transfer and enter state C0h or C8h. the TWI module is switched to the not addressed
slave mode and will ignore the master receiver if it continues the transfer. Thus the mas-
ter receiver receives all 1’s as serial data. While AA is reset, the TWI module does not
respond to its own slave address. However, the 2-wire bus is still monitored and
addres s recog nition ma y be resum e at any time by setting AA . This mean s that the AA
bit may be used to temporarily isolate the TWI module from the 2-wire bus.
Miscellaneous St ates There are two SSCS codes that do not correspond to a define TWI hardware state
(Table 106 ). These codes are discuss hereafter.
Status F8h indicates that no relevant information is available because the serial interrupt
flag is not set ye t. This oc curs between other stat es and when the TWI module is not
invo lved in a ser ial transfer.
Status 00h indicates that a bus error has occurred during a T WI serial transfer. A bus
error is caused when a START or a STOP condition occurs at an illegal position in the
format f rame. Exa mples o f suc h il legal po siti ons h appen during the s erial trans fer of a n
address byte, a data byte, or an acknowledge bit. When a bus error occurs, SI is set. To
recover from a bus error, the STO flag must be set and SI must be cleared. This causes
the TWI module to enter the not addressed slave mode and to clea r the STO flag (no
other bi ts in SSC ON are af fected). T he SDA an d SCL line s are re leased and no STOP
condition is transmitted.
Notes the TWI module interfaces to the external 2-wire bus via two port pins: SCL (serial clock
line) and SDA (seri al data line). T o avoid low lev el assertin g on thes e lines when th e
TWI module is enabled, the output latches of SDA and SLC must be set to logic 1.
Table 101. Bit Frequency Configuration
Bit Frequency ( kHz)
CR2 CR1 CR0 FOSCA= 12 MHz FOSCA = 16 MH z FOSCA divided by
0 0 0 47 62.5 256
0 0 1 53.5 71.5 224
0 1 0 62.5 83 192
0 1 1 75 100 160
1 0 0 - - Unused
1 0 1 100 133.3 120
1 1 0 200 266.6 60
1 1 1 0.5 <. < 62.5 0.67 <. < 83 96 · (256 - reload valueTimer 1)
(reload value range: 0-254 in mode 2)
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Figure 52. Format and State in the Master Transmitter Mode
SSLAWA Data AP
08h 18h 28h
MT
SSLAW
AP
AP
R
MR
10h
20h
30h
A or A continues
38h38h
Acontinues
68h
Other master
Othe r master
78h B0h To corresponding
states in sla ve mo de
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave addre ss
Not acknowledge
received after a data
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
byte
A or A continues
Othe r mast er
Data A
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This numbe r (con tained in SS CS) corr es pon ds
to a defined state of the 2-wire bus
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Table 102. Status in Master Transmitter Mode
Status
Code
SSSTA
Status of the Two-
wire Bus and Two-
wire Hardware
Application software response
Next Action Taken by Two-wire HardwareTo/From SSDAT
To SSCON
SSSTA SSSTO SSI SSAA
08h A ST ART condition has
been transmitted Write SLA+W X 0 0 X SLA+W will be transmitted.
10h A repeated START
condition has been
transmitted
Write SLA+W
Write SLA+R
X
X
0
0
0
0
X
X
SLA+W will be transmitted.
SLA+R will be transmitted.
Logic will switch to master receiver mode
18h SLA+W has been
transmitted; ACK has
been received
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
0
1
0
1
0
0
1
1
0
0
0
0
X
X
X
X
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
20h SLA+W has been
transmitted; NOT ACK
has been received
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
0
1
0
1
0
0
1
1
0
0
0
0
X
X
X
X
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
28h Data byte has been
transmitted; ACK has
been received
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
0
1
0
1
0
0
1
1
0
0
0
0
X
X
X
X
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
30h Data byte has been
transmitted; NOT ACK
has been received
Write data byte
No SSDAT action
No SSDAT action
No SSDAT action
0
1
0
1
0
0
1
1
0
0
0
0
X
X
X
X
Data byte will be transmitted.
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
38h Arbitration lost in
SLA+W or data bytes
No SSDAT action
No SSDAT action
0
1
0
0
0
0
X
X
Two-wire bus will be released and not addressed
slave mode will be entered.
A START condition will be transmitted when the bus
becomes free.
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Figure 53. Format and State in the Master Receiver Mode
SSLAR A Data
08h 40h 58h
SSLAR
AP W
MT
10h
48h
A or A continues
38h38h
Acontinues
68h
Other master
Other master
78h B0h To corr es po nd in g
states in slave mode
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Arbitration lost and
addressed as slave
Acontinues
Othe r master
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
AData PA
50h
MR
Arbitration lost in slave
address or acknowledge bit
Data A
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Table 103. Status in Master Receiver Mode
Status
Code
SSSTA
Status of the Two-
wire Bus and Two-
wire Hardware
Application software response
Next Action Taken by Two-wire HardwareTo/From SSDAT
To SSCON
SSSTA SSSTO SSI SSAA
08h A ST ART condition has
been transmitted Write SLA+R X 0 0 X SLA+R will be transmitted.
10h A repeated START
condition has been
transmitted
Write SLA+R
Write SLA+W
X
X
0
0
0
0
X
X
SLA+R will be transmitted.
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
38h Arbitration lost in
SLA+R or NOT ACK
bit
No SSDAT action
No SSDAT action
0
1
0
0
0
0
X
X
Two-wire bus will be released and not addressed
slave mode will be entered.
A START condition will be transmitted when the bus
becomes free.
40h SLA+R has been
transmitted; ACK has
been received
No SSDAT action
No SSDAT action
0
0
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned.
Data byte will be received and ACK will be returned.
48h SLA+R has been
transmitted; NOT ACK
has been received
No SSDAT action
No SSDAT action
No SSDAT action
1
0
1
0
1
1
0
0
0
X
X
X
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
50h Data byte has been
recei ved ; ACK has
been returned
Read data byte
Read data byte
0
0
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned.
Data byte will be received and ACK will be returned.
58h Data byte has been
received; NOT ACK
has been returned
Read data byte
Read data byte
Read data byte
1
0
1
0
1
1
0
0
0
X
X
X
Repeated START will be transmitted.
STOP condition will be transmitted and SSSTO flag
will be reset.
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
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Figure 54. Format and State in the Slave Receiver Mode
SSLAWA Data AData P or S
A
P or S
A
General Call A Data AData P or S
A
A
60h
68h
80h 80h A0h
88h
70h 90h 90h A0h
P or S
A
98h
A
78h
Data A
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
Receptio n of the own
slave address and one or
more data bytes. All are
acknowledged.
Last data byte received
is not acknowledged.
Arbitration lost as master
and addressed as slave
Receptio n of the gener al cal l
address and one or more data
bytes.
Last data byte received is
not acknowledged.
Arbitration lost as master and
addressed as slave by general call
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Table 104. Status in Slave Receiver Mode
Status
Code
(SSCS) Status of the 2-wire bus and
2-wire hardware
Application Software Response
Next Action Taken By 2-wire Sof tware
To/from SSDAT To SSCON
STA STO SI AA
60h Own SLA+W has been
received; ACK has been
returned
No SSDAT action or
No SSDAT action
X
X
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
68h
Arbitration lost in SLA+R/W as
master; own SLA+W has been
received; ACK has been
returned
No SSDAT action or
No SSDAT action
X
X
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
70h General call address has been
received; ACK has been
returned
No SSDAT action or
No SSDAT action
X
X
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
78h
Arbitration lost in SLA+R/W as
master; general call address
has been received; ACK has
been returned
No SSDAT action or
No SSDAT action
X
X
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
80h
Previously addressed with
own SLA+W; data has been
received; ACK has been
returned
No SSDAT action or
No SSDAT action
X
X
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
88h
Previously addressed with
own SLA+W; data has been
received; NOT ACK has been
returned
Read data byte or
Read data byte or
Read data byte or
Read data byte
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be
transmitted when the bus becomes free
90h
Previously addressed with
general call; data has been
received; ACK has been
returned
Read data byte or
Read data byte
X
X
0
0
0
0
0
1
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be
returned
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98h
Previously addressed with
general call; data has been
received; NOT ACK has been
returned
Read data byte or
Read data byte or
Read data byte or
Read data byte
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be
transmitted when the bus becomes free
A0h
A STOP condition or repeated
START condition has been
received while still addressed
as slave
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A START condition will be
transmitted when the bus becomes free
Table 104. Status in Slave Receiver Mode (Continued)
Status
Code
(SSCS) Status of the 2-wire bus and
2-wire hardware
Application Software Response
Next Action Taken By 2-wire Sof tware
To/from SSDAT To SSCON
STA STO SI AA
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Figure 55. Format and State in the Slave Transmitter Mode
SSLARAData AData P or S
A
A8h B8h C0h
P or S
A
C8h
All 1’s
A
B0h
Data A
n
From master to slave
From slave to master
Any number of data bytes and their associated
acknowledge bits
This number (contained in SSCS) corresponds
to a defined state of the 2-wire bus
Reception of the
own slave address
and one or more
data bytes
Arbitration lost as master
and addressed as slave
Last data byte transmitted.
Switched to not addressed
slave (AA=0)
Table 105. Status in Slave Transmitter Mode
Status
Code
(SSCS) Status of the 2-wire bus and
2-wire hardware
Application Software Response
Next Action Taken By 2-wire Software
To/from SSDAT To SSCON
STA STO SI AA
A8h Own SLA+R has been
received; ACK has been
returned
Load data byte or
Load data byte
X
X
0
0
0
0
0
1
Last data byte will be transmitted and NOT ACK
will be received
Data byte will be transmitted and ACK will be
received
B0h
Arbitration lost in SLA +R/W as
master; own SLA+R has been
received; ACK has been
returned
Load data byte or
Load data byte
X
X
0
0
0
0
0
1
Last data byte will be transmitted and NOT ACK
will be received
Data byte will be transmitted and ACK will be
received
B8h Data byte in SSDAT has been
transmitted; NOT ACK has
been received
Load data byte or
Load data byte
X
X
0
0
0
0
0
1
Last data byte will be transmitted and NOT ACK
will be received
Data byte will be transmitted and ACK will be
received
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Table 106. Miscellaneous Status
C0h Data byte in SSDAT has been
transmitted; NOT ACK has
been received
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A ST ART conditi on will be transmitted
when the bus becomes free
C8h Last data byte in SSDAT has
been transmitted (AA=0); ACK
has been received
No SSDAT action or
No SSDAT action or
No SSDAT action or
No SSDAT action
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1
Switched to the not addressed slave mode; no
recognition of own SLA or GCA. A START
condition will be transmitted when the bus
becomes free
Switched to the not addressed slave mode; own
SLA will be recognised; GCA will be recognised if
GC=logic 1. A ST ART conditi on will be transmitted
when the bus becomes free
Table 105. Status in Slave Transmitter Mode (Continued)
Status
Code
(SSCS) Status of the 2-wire bus and
2-wire hardware
Application Software Response
Next Action Taken By 2-wire Software
To/from SSDAT To SSCON
STA STO SI AA
Status
Code
(SSCS)
St atus of the 2-wire
bus and 2-wire
hardware
Applicat ion Softwar e Re s pons e
Next Action Taken By 2-wire
Software
To/from
SSDAT To SSCON
STA STO SI AA
F8h No relevant state
information
available; SI= 0
No SSDAT
action No SSCON action Wait or proceed current transfer
00h Bus error due to an
illegal START or
STOP condition
No SSDAT
action 010X
Only the internal hardware is
affected, no STOP condition is
sent on the bus. In all cases,
the bus is released and STO is
reset.
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Registers Table 107. SSCON Register
SSCON - Synchronous Serial Control register (93h)
76543210
CR2 SSIE STA STO SI AA CR1 CR0
Bit
Number Bit
Mnemonic Description
7CR2
Control Rate bit 2
See Table 101.
6SSIE
Synchronous Serial Interface Enab le bit
Clear to disable the TWI module.
Set to enable the TWI module.
5STA
St art flag
Set to send a START condition on the bus.
4ST0
Stop fla g
Set to send a STOP condition on the bus.
3SI
Synchronous Serial Interrupt flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
2AA
Assert Acknowledge flag
Clear in master and slave receiver modes, to force a not acknowledge (high level
on SDA).
Clear to disable SLA or GCA recognition.
Set to recognise SLA or GCA (if GC set) for entering slave receiver or transmitter
modes.
Set in master and slave receiver modes, to force an acknowledge (low level on
SDA).
This bit has no effect when in master transmitter mode.
1CR1
Control Rate bit 1
See Table 101.
0CR0
Control Rate bit 0
See Table 101.
Table 108. SSDAT (95h) - Syncrhonous Serial Data register (read/write)
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
76543210
Bit
Number Bit
Mnemonic Description
7 SD7 A ddress bit 7 or Data bit 7.
6 SD6 A ddress bit 6 or Data bit 6.
5 SD5 A ddress bit 5 or Data bit 5.
4 SD4 A ddress bit 4 or Data bit 4.
3 SD3 A ddress bit 3 or Data bit 3.
2 SD2 A ddress bit 2 or Data bit 2.
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Table 111. SSADR (096h) - Synchronus Serial Address Register (read/write)
Table 112. SSADR Register - Reset value = FEh
1 SD1 A ddress bit 1 or Data bit 1.
0 SD0 A ddress bit 0 (R/W) or Data bit 0.
Table 109. SSCS (094h) read - Synchronous Serial Control and Status Register
76543210
SC4 SC3 SC2 SC1 SC0 0 0 0
Table 110. SSCS Register: Read Mode - Reset Value = F8h
Bit
Number Bit
Mnemonic Description
0 0 A lw a ys zero
1 0 A lw a ys zero
2 0 A lw a ys zero
3SC0
Status Code bit 0
See to Table 106.
4SC1
Status Code bit 1
See to Table 106.
5SC2
Status Code bit 2
See to Table 106.
6SC3
Status Code bit 3
See to Table 106.
7SC4
Status Code bit 4
See to Table 106.
76543210
A7 A6 A5 A4 A3 A2 A1 A0
Bit
Number Bit
Mnemonic Description
7 A7 Slave Address bit 7
6 A6 Slave Address bit 6
5 A5 Slave Address bit 5
4 A4 Slave Address bit 4
3 A3 Slave Address bit 3
2 A2 Slave Address bit 2
1 A1 Slave Address bit 1
Bit
Number Bit
Mnemonic Description
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0GC
General Call bit
Clear to disable the general call address recognition.
Set to enable the general call address recognition.
Bit
Number Bit
Mnemonic Description
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Serial Port
Interface (SPI) The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communica-
tion between the MCU and peripheral devices, including other MCUs.
Features Features of the SPI Module include the following:
• Full-duplex, three-wire synchronous transfers
• Master or Slave operation
• Six programmable Master clock rates in master mode
• Serial clock with programmable polarity and phase
• Master Mode fault error flag with MCU interrupt capability
Signal Description Fig ure 56 sh ows a typical S PI bus c onfigurati on using one Mas ter con troller a nd many Slave
peripherals. The bus is made of three wires connecting all the devices.
Figure 56. SPI Master/Slaves Interconnection
The Mas ter device s elects the i ndividual Slave devi ces by u sing four pins of a paral lel port to
control the four SS pins of the Slave devices.
Master Output Slave
Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI
line is used to tr ans fer da ta i n s er ies fr om the M as ter to t he S la ve. Ther efo re , it is an o utpu t si g-
nal from th e Master, and a n input signal to a Slave. A By te (8-bit word) is transmitted most
significant bit (MSB) first, least significant bit (LSB) last.
Master Input Slave
Output (MISO) This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO
line is used to tr ans fer da ta i n s er ies fr om the S lave to th e Ma ste r. T herefo re , it is an o utpu t si g-
nal from the Sla ve, and an inpu t signal to the Ma ster. A Byte (8-bi t word) is tran smitted mos t
significant bit (MSB) first, least significant bit (LSB) last.
SPI Serial Clock (SCK) T his s ign al is use d to sync hron ize t he data trans mis sion both in a nd o ut of t he de vices th rough
their MOS I and MISO lines. It is driven by the Mas ter for eight clock cycles which all ows to
exchange one Byte on the serial lines.
Slave Sel ect (SS )Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any
message for a Slave. It is obvious that only one Master (SS high level) can drive the network.
The Mas ter may s ele ct eac h S lave d ev ic e by so ftwar e thr oug h por t p ins ( Figu re 57) . To p re ve nt
bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a
transmission.
Slave 1
MISO
MOSI
SCK
SS
MISO
MOSI
SCK
SS
PORT
0
1
2
3
Slave 3
MISO
MOSI
SCK
SS
Slave 4
MISO
MOSI
SCK
SS
Slave 2
MISO
MOSI
SCK
SS
VDD
Master
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AT89C51RE2
In a Master confi guration, the SS li ne can be used in co njunc tion with the MODF f lag in the SP I
Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error
conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general-purpose if the following conditions are met:
• The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind
of configuration can be found when only one Master is driving the network and there is no
way that the SS pin could be pulled low. Therefore, the MODF flag in the SPSCR will never
be set(1).
• The Device is configured as a Slave with CPHA and SSDIS control bits set(2). This kind of
configuration can happen when the system includes one Master and one Slave only.
Therefore, the device should always be selected and there is no reason that the Master
uses the SS pin to select the communicating Slave device.
Note: 1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA =’0’ because in this
mode, the SS is used to start the transmission.
Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is controlled by
three bits in the SPCON register: SPR2, SPR1 and SPR0.The Master clock is selected from one
of seven clock rates resulting from the division of the internal clock by 4, 8, 16, 32, 64 or 128.
Table 113 gives the different clock rates selected by SPR2:SPR1:SPR0.
In Slave mode, the maximum baud rate allowed on the SCK input is limited to Fsys/4
Table 113. SPI Master Baud Rate Selection
SPR2 SPR1 SPR0 Clock Rate Baud Rate Divisor (BD)
0 0 0 Don’t Use No BRG
001 F
CLK PERIPH /4 4
010 F
CLK PERIPH/8 8
011 F
CLK PERIPH /16 16
100 F
CLK PERIPH /32 32
101 F
CLK PERIPH /64 64
110 F
CLK PERIPH /128 128
1 1 1 Don’t Use No BRG
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Functional
Description Figure 57 shows a detailed structure of the SPI Module.
Figure 57. SPI Module Block Diagram
Operating Modes The Serial Peripheral Interface can be configured in one of the two modes: Master mode or
Slave mode. The configuration and initialization of the SPI Module is made through two
registers:
• The Serial Peripheral Control register (SPCON)
• The Serial Peripheral Status and Control Register (SPSCR)
Once the SPI is configured, the data exchange is made using:
• The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
receiv ed (shif ted i n se ri al ly). A seri al c lo ck li ne ( SCK) syn chro ni ze s shifting and s amp li ng on the
two seri al da ta li nes (MO SI an d MISO ). A S lave Sele ct li ne ( SS) all ows i ndividu al s electi on of a
Slave SPI device; Slave devices that are not selected do not interfere with SPI bus activities.
Shift Registe r01
234567
Internal Bus
Pin
Control
Logic MISO
MOSI
SCK
M
S
Clock
Logic
SPI In t er r u p t
8-bit bus
1-bit signal
SS
FCLK
Receive Data Register
SPDAT
SPI
Control
Transmit Data Register
-MODFSPIF OVR SPTE UARTMSPTEIEMODFIE
SPSCR
SPEN MSTRSPR2 SSDIS CPOL CPHA SPR1 SPR0
SPCON
Request
PERIPH
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When th e Mas ter device transm its d ata to the S lave d evic e via the MOSI line, the S lave d evic e
respond s by sendi ng data to the Ma ster devic e vi a th e M ISO l in e. This im pl ies full-dupl ex tr an s-
mission with both data out and data in synchronized with the same clock (Figure 58).
Figure 58. Full-Duplex Master-Slave Interconnection
Maste r Mode The SPI operate s in Mast er mode when th e Mast er bit, MSTR (1), in th e SPCO N reg ist er is set.
Only one Mas ter SP I dev ic e can i niti ate tra ns mis sio ns . Soft war e beg ins the tran sm iss ion fro m a
Master SPI Module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register
is empty, the Byte is immediately transferred to the shift register. The Byte begins shifting out on
MOSI p in un der the co ntr ol o f th e se rial c lo ck, SCK . Si mul tan eous l y, an other Byte s hi fts in from
the Slav e on the M aster’s MISO pi n. The transmi ssion en ds w hen the S erial Per ipheral transfer
data f lag, S PI F, in S PS CR becomes set. At the s ame ti me tha t S PI F be co mes s et, the rec ei ved
Byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF
by reading the Serial Peripheral Status register (SPSCR) with the SPIF bit set, and then reading
the SPDAT.
Slave Mode The SPI operates in Slave mode when the Master bit, MSTR (2), in the SPCON register is
clear ed. Be fore a data tr ansm is sion occ urs, t he S lave Se le ct pin, SS , of the Slave device must
be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI Modu le, data e nter s the s hi ft regis te r un der the cont rol of the S C K from the Mas-
ter SP I Modul e. Afte r a By te ente rs the s hift reg ister, it is imme diatel y tr ansferred to t he rece ive
data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software
must then read the SP DAT before another Byte enters the shift regi ster (3). A Slave SPI mus t
complete the wri te to the S PDAT (shi ft register ) at leas t one bus cycle b efore the Ma ster SP I
starts a transmission. If the write to the data register is late, the SPI transmits the data already in
the shift register from the previous transmission.
Transmission Formats Software can se lec t an y o f four co mb in ati ons of s er ia l clo ck (S CK ) phas e an d po lar i ty u sing two
bits in the SPCON: the Clock Polarity (CPOL (4)) and the Clock Phase (CPHA4). CPOL defines
the defau lt SCK line leve l in idle state. It has no signi ficant effect on the trans mission forma t.
CPHA de fines the edges on which th e input data are s ample d and the e dges on w hich the o ut-
put data are shif ted (Fig ure 5 9 and Figu re 60). Th e cloc k phas e and p olarity shoul d be ide ntica l
for the Master SPI device and the communicating Slave device.
8-bit Shift register
SPI
Clock Generator
Master MCU
8-bit Shift register
MISOMISO
MOSI MOSI
SCK SCK
VSS
VDD SSSS Slave MCU
1. The SPI Module s hou ld be config ured as a Mas ter be fore it is ena ble d (SPEN set) . Als o, the Mas-
ter SPI should be configured before the Slave SPI.
2. The SPI Module should be configured as a Slave before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock sp eed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
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Figure 59. Data Transmi ssion Format (CPHA = 0)
Figure 60. Data Transmi ssion Format (CPHA = 1)
Figure 61. CPHA/SS Timing
As shown in Figure 59, the first SCK edge is the MSB capture strobe. Therefore, the Slave must
begin driving its data before the first SCK edge, and a falling edge on the SS pin is us ed to s tart
the transmission. The SS pin must be toggled high and then low between each Byte transmitted
(Figure 61).
Figure 60 shows an SP I transmiss ion in which CP HA is’1’. In thi s case, the Ma ster begi ns driv-
ing i ts M OSI p in on th e fi rst S CK edge . T herefo re, the Slav e u ses t he f irst SC K e dge a s a star t
transmis sion s i gnal . The SS pi n c an rem ai n l ow be twee n tr ansm is sions (F ig ure 61 ). Th is for m at
may b e preferred in systems havi ng onl y one M aster and only one Sl ave driv ing th e MISO data
line.
Queuing transmission For an SPI configured in master or slave mode, a queued data byte must be transmit-
ted/received immediately after the previous transmission has completed.
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1MSB LSB
13245678
Capture Point
SS (to Slave)
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB
bit6 bit5 bit4 bit3 bit2 bit1
MSB LSB
132 45678
Capture Poi nt
SS (to Slave)
MISO (from Slave)
MOSI (from Ma st er )
SCK (CPOL = 1)
SCK (CPOL = 0)
SPEN (Internal)
SCK Cycle Number
Byte 1 Byte 2 Byte 3
MISO/MOSI
Maste r S S
Slave SS
(CPHA = 1)
Slave SS
(CPHA = 0)
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AT89C51RE2
When a transmission is in progress a new data can be queued and sent as soon as transmission
has been completed. So it is possible to transmit bytes without latency, useful in some
applications.
The SP TE bi t in SPSCR is se t as long a s the tran smis sion bu ffer i s free . It me ans t hat the user
application can write SPDAT with the data to be transmitted until the SPTE becomes cleared.
Figure 62 shows a queuing transmission in master mode. Once the Byte 1 is ready, it is immedi-
ately sent on the bus. Meanwh ile an other byte is prep ared (and the SP TE is cleared ), it will be
sent at the end of the current transmission. The next data must be ready before the end of the
current transmission.
Figure 62. Queuing Tra nsm iss ion In Master Mode
In slave mode it is almost the same except it is the external master that start the transmission.
Also, in slave mode, if no new data is ready, the last value received will be the nex t data byte
transmitted.
MSB B6 B5 B4 B3 B2 B1 LSB
MOSI
SCK
MSB B6 B5 B4 B3 B2 B1 LSB
BYTE 1 under transmission
MSB B6 B5 B4 B3 B2 B1 LSB MSB B6 B5 B4 B3 B2 B1 LSB
MISO
Data Byte 1 Byte 2 Byte 3
SPTE BYTE 2 under transmission
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Error Conditions The following flags in the SPSCR register indicate the SPI error conditions:
Mode Fault Error
(MODF) Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is
inconsistent with the actual mode of the device.
• Mode fault detection in Master mode:
MODF is set to warn that there may be a multi-master conflict for system control. In this case,
the SPI system is affected in the following ways:
– An SPI receiver/error CPU interrupt request is generated
– The SPEN bit in SPCON is cleared. This disables the SPI
– The MSTR bit in SPCON is cleared
Clearing the MODF bit is accomplished by a read of SPSCR register with MODF bit set, followed
by a write to the SPCON register. SPEN Control bit may be restored to its original set state after
the MODF bit has been cleared.
Figure 63. Mode Fault Conditions in Master Mode (Cpha =’1’/Cpol =’0’)
Note: When SS is discarded (SS disabled) it is not possible to detect a MODF error in master mode
because the SPI is internally unselected and the SS pin is a general purpose I/O.
• Mode fault detection in Slave mode
In slave mode, the MODF error is detected when SS goes high during a transmission.
A transmission begins when SS goes low and ends once the incoming SCK goes back to its idle
level following the shift of the eighteen data bit.
A MODF err or occurs if a slave is sele cted (SS is low) and late r unsele cted (SS is high) even if
no SCK is sent to that slave.
At an y tim e, a’1 ’ on the S S pin of a slave SPI p uts th e MI SO pi n in a high impe dance state and
internal state counter is cleared. Also, the slave SPI ignores all incoming SCK clocks, even if it
was already in the middle of a transmission. A new transmission will be performed as soon as
SS pin returns low.
SCK
SS
(master)
1 2 3SCK cycle # 0 0
SS
(slave)
(from master)
MODF detected
B6MSB
B6MSB
0
z
1
0
z
1
0
z
1
0
z
1
0
z
1
0
0
z
1
SPI enable
MODF detected
MOSI
MISO
(from master)
(from slave)
B5
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Figure 64. Mode Fault Conditions in Slave Mode
Note: when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave mode
because the SPI is internally selected. Also the SS pin becomes a general purpose I/O.
OverRun Condition This error mean that the speed is not adapted for the running application:
An OverRun condition occurs when a byte has been received whereas the previous one has not
been read by the application yet.
The last by te (which generate the overrun error) does n ot overwrite the unr ead data so that it
can still be read. Therefore, an overrun error always indicates the loss of data.
Interrupts Three SPI status flags can generate a CPU interrupt requests:
Table 114. SPI Inte rrupts
Serial Periphe ral dat a transfe r flag, SPI F: This bi t is set by ha rdware wh en a tran sfer ha s been
completed. SPIF bit generates transmitter CPU interrupt request only when SPTEIE is disabled.
Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent with the
mode of the SPI (in both master and slave modes).
Serial Per iphe ral Trans mit Reg ister em pty flag , SPTE: Th is bit is set when the tr ansmit bu ffer is
empty ( other data ca n be loaded is SPDAT). S PTE bit gen erates transmi tter CPU inter rupt
request only when SPTEIE is enabled.
Note: Whi le using SPTE inte rruptio n for “bur st mode” tran sfers (S PTEIE= ’1’), the user soft-
ware application should take care to clear SPTEIE, during the last but one data reception (to
be able to generate an interrupt on SPIF flag at the end of the last data reception).
SCK
1 2 3SCK cycle # 0
SS
(slave)
(from master)
MODF detected
B6MSB
B6MSB
0
z
1
0
z
1
0
z
1
0
z
1
0
MODF detected
MOSI
MISO
(from master)
(from slave)
MSB
B5 B4
4
Flag Request
SPIF (SPI data transfer) SPI Transmitter Interrupt Request
MODF (Mode Fault) SPI mode-fault Interrupt Request
SPTE (Transm i t register empty) SPI transmit register empty Interrupt Request
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Figure 65. SPI Interrupt Requests Generation
Registers Three registers in the SPI module provide control, status and data storage functions. These reg-
isters are describe in the following paragraphs.
Serial Peripheral
Control Register
(SPCON)
• The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configure the SPI Module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI Module
• Frees the SS pin for a general-purpose
Table 115 describes this register and explains the use of each bit
Table 115. SPCON Register
SPCON - Serial Peripheral Control Register (0D4H)
SPI
CPU Interrupt Request
SPIF
SPTEIE
SPTE
MODF
MODFIE
76543210
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
Bit Number Bit Mnemonic Description
7SPR2
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and SPR0 for
detail).
6 SPEN Serial Peripheral Enable
Cleared to disable the SPI interface (internal reset of the SPI).
Set to enable the SPI interface.
5SSDIS
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode, this bit
has no effect if CPHA =’0’. When SSDIS is set, no MODF interrupt request
is generated.
4MSTR
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
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Reset Value = 0001 0100b
Not bit address ab le
Serial Peripheral Status
Register and Control
(SPSCR)
The Serial Peripheral St atus Register contains flags to signal the following conditions:
• Data transfer complete
• Write collision
• Inconsistent logic level on SS pin (mode fault error)
Table 116. SPSCR Register
SPSCR - Serial Peripheral Status and Control register (C4H)
3CPOL
Clock Polarity
Cleared to have the SCK set to’0’ in idle state.
Set to have the SCK set to’1’ in idle state.
2CPHA
Clock Phase
Cleared to have the data sampled when the SCK leaves the idle state (see
CPOL).
Set to have the data sampled when the SCK returns to idle state (see
CPOL).
1SPR1
SPR2 SPR1 SPR0 Serial Peripheral Rate
0 0 0 Invalid
00 1 F
CLK PERIPH /4
01 0 F
CLK PERIPH /8
01 1F
CLK PERIPH /16
10 0F
CLK PERIPH /32
10 1F
CLK PERIPH /64
11 0F
CLK PERIPH /128
1 1 1 Invalid
0SPR0
Bit Number Bit Mnemonic Description
76543210
SPIF - OVR MODF SPTE UARTM SPTEIE MODFIE
Bit Number Bit
Mnemonic Description
7SPIF
Serial Peripheral Dat a Transfer Flag
Cleared by hardware to indicate data transfer is in progress or has been approved by a
clearing sequence.
Set by hardware to indicate that the data transfer has been completed.
This bit is cleared when reading or writing SPDATA after reading SPSCR.
6-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5OVR
Overrun Error Flag
- Set by hardware when a byte is received whereas SPIF is set (the previous received
data is not overwritten).
- Cleared by hardware when reading SPSCR
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Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa
Register (SPDAT) The Se rial P er ip heral Da ta Regi st er (T abl e 117 ) is a r ea d/wr ite b uffer f or th e r ecei v e d ata r egi s-
ter. A write to SPDAT places da ta directl y into the shi ft regi ste r. No tr an sm it b uffer is av ail ab le i n
this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the
shift register.
Table 117. SPDAT Register
SPDAT - Serial Peripheral Data Register (C5H)
Reset Value = Indeterm inate
R7:R0: Receive data bits
4MODF
Mode Faul t
- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master
and slave modes).
- Cleared by hardware when reading SPSCR
When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS remains high. A new
transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN bit in
SPCON register).
3 SPTE
Serial Peripheral Transmit register Empty
- Set by hardware when transmit register is empty (if needed, SPDAT can be loaded with
another data).
- Cleared by hardware when transmit register is full (no more data should be loaded in
SPDAT).
2UARTM
Serial Peripheral UART mode
Set and cleared by software:
- Clear: Normal mode, data are transmitted MSB first (default)
- Set: UART mode, data are transmitted LSB first.
1SPTEIE
Interrupt Enable for SPTE
Set and cleared by software:
- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is
generated).
- Clear to disable SPTE interrupt generation
Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag goes high.
To enable SPIF interrupt again, SPTEIE should be cleared.
0MODFIE
Interrupt Enable for MODF
Set and cleared by software:
- Set to enable MODF interrupt generation
- Clear to disable MODF interrupt generation
Bit Number Bit
Mnemonic Description
76543210
R7 R6 R5 R4 R3 R2 R1 R0
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SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-
going ex change . Howeve r, sp ecial care sh ould be taken w hen w riting to t hem whi le a tra nsmis-
sion is on-going:
• Do not change SPR2, SPR1 and SPR0
• Do not change CPHA and CPOL
• Do not change MSTR
• Clearing SPEN would immediately disable the peripheral
• Writing to the SPDAT will cause an overflow.
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Power Monitor The POR/PFD function monitors the internal power-supply of the CPU core memories and the
perip herals, an d if neede d, suspends their act ivity when the internal power supp ly falls be low a
safety threshold. This is achieved by applying an internal reset to them.
By generating the Reset the Power Monitor insures a correct start up when AT89C51RE2 is
powered up.
Description In order to startup and maintain the microcontroller in correct operating mode, VCC has to be sta-
bilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude
compatible with logic level VIH/VIL.
These parameters are controlled during the three phases: power-up, normal operat ion and
power going down. See Figure 66.
Figure 66. Power Monitor Block Diagram
Note: 1. Once XTAL1 High and low levels reach above and below VIH/VIL. a 1024 clock period delay
will extend the rese t comi ng from the Powe r Fail Dete ct. If the power fall s belo w the Power Fai l
Detect threshold level, the Reset will be applied immediately.
The Voltage regulator generates a regulated internal supply for the CPU core the memories and
the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.
VCC
Power On Reset
Power Fail Detect
Voltage Regulator
XTAL1 (1)
CPU core
Memories
Peripherals
Regulated
Supply
RST pin
Hardware
Watchdog
PCA
Watchdog
Internal Reset
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The Power fail detect monitor the supply generated by the voltage regulator and generate a
reset if this supply falls below a safety threshold as illustrated in the Figure 67 below.
Figure 67. Power Fail Detect
When the po wer is applied, the P ower Monitor immediatel y asserts a r eset. Once the interna l
supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL
clock i nput. The inter nal reset wil l remain ass erted until the Xtal1 le vels are ab ove and bel ow
VIH and VIL. Fur ther m ore. A n intern al cou nter wi ll count 1024 clock perio ds befo re the re set is
de-asserted.
If the internal power supply falls below a safety level, a reset is immediately asserted.
Vcc
t
Reset
Vcc
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Power-off Flag The powe r-off flag allows the us er to distinguish betwe en a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (Table 118). POF is set by hardware when
VCC rises f ro m 0 t o i ts no mi nal v ol tag e. T h e POF c an be s et or c l eared by so ftwar e al low ing th e
user to determine the type of reset.
Table 118. PCON Register
PCON - Power Contro l Regi ste r (87h)
Reset Value = 00X1 0000b
Not bit address ab le
76543210
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number Bit
Mnemonic Description
7SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6SMOD0
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register .
5-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4POF
Power-Off Flag
Cleared to recognize next reset type.
Set by hardware when VCC rises fr om 0 to its nominal voltage. Can also be set by
software.
3GF1
Genera l pur pose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2GF0
Genera l pur pose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0IDL
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
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Reset
Introduction The reset sources are: Power Manageme nt, Hardware Watch dog, PCA Watchdog and Reset
input.
Figure 68. Reset schematic
Reset Input The Reset input can be used to force a reset pulse longer than the internal reset controlled by
the Power Monitor. RST input has a pull- down resistor allowing power-on reset by simply con-
necting an external capacitor to VCC as shown in Figure 69. Resistor value and input
characteristics are discussed in the Section “DC Characteristics” of the AT89C51RE2 datasheet.
Figure 69. Reset Circuitry and Power-On Reset
Power
Monitor
Hardware
Watchdog
PCA
Watchdog
RST
Internal Reset
RST
RRST
VSS
To internal reset
RST
VDD
+
b. Power-on Reseta. RST input circuitry
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Reset Output
As detailed in Section “Hardware W atchdog Timer”, page 124, the WDT generates a 96-clock
period pu lse on t he RST pin . In order to p roperly propagat e this pu lse to the rest of the applic a-
tion in case of external capacitor or power-supply supervisor circuit, a 1 k Ω resistor must be
added as shown Figu re 70.
Figure 70. Recommended Reset Output Schematic
RST
VDD
+
VSS
VDD
RST
1K
To other
on-board
circuitry
166 7663E–8051–10/08
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Electrical Characteristics
Absolute Maximum Ratings
DC Parameters
I = industrial................................ ...... ..... ...... ...... .-40 °C to 85°C
Storage Temperatu re....... ...... ..... ...... ............ -65°C to + 150°C
Volta ge on VCC to VSS (standard voltage).........-0.5V to + 6.5V
Volta ge on VCC to VSS (low voltage).................. -0.5V to + 4.5V
Volta ge on Any Pin to VSS...................... ....-0.5V to VCC + 0.5V
Power Dissipation........................................................... 1 W(2)
Note: Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions above those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions may affect
device reliability.
Power dissipation is based on the maximum allow-
able die temperature and the thermal resistance of
the package.
TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 40 MHz
Symbol P arameter Min Typ Max Unit Test Conditions
VIL Input Low Voltage -0.5 0.2 VCC - 0.1 V
VIH Input High Voltage except RST, XTAL1 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High V olt age RST, XTAL1 0.7 VCC VCC + 0.5 V
VOL Output Low Voltage, ports 1, 2, 3, 4 (6)
0.3
0.45
1.0
V
V
V
VCC = 4.5V to 5.5V
IOL = 100 μA(4)
IOL = 1.6 mA(4)
IOL = 3.5 mA(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 0.8 mA(4)
VOL1 Output Low Voltage, port 0, ALE, PSEN (6)
0.3
0.45
1.0
V
V
V
VCC = 4.5V to 5.5V
IOL = 200 μA(4)
IOL = 3.2 mA(4)
IOL = 7.0 mA(4)
0.45 V VCC = 2.7V to 5.5V
IOL = 1.6 mA(4)
VOH Output High Voltage, ports 1, 2, 3, 4
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
VCC = 5V ± 10%
IOH = -10 μA
IOH = -30 μA
IOH = -60 μA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 μA
VOH1 Output High Voltage, port 0, ALE, PSEN
VCC - 0.3
VCC - 0.7
VCC - 1.5
V
V
V
VCC = 5V ± 10%
IOH = -200 μA
IOH = -3.2 mA
IOH = -7.0 mA
0.9 VCC VVCC = 2.7V to 5.5V
IOH = -10 μA
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Note s: 1. O perat ing I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 74), VIL =
VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. I CC would be slightly higher if a crystal oscillator us ed
(see Figure 71).
2. Idle I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5V, VIH = VCC -
0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 72).
3. Pow er -d o wn I CC is me a su red wit h all ou tpu t pi ns di sc on nec t ed ; EA = VCC, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Fig-
ure 73).
4. Capa ci t an ce loading on Po rt s 0 an d 2 may cause sp urious noise pulses to be supe rim pos ed on the VOLS of ALE and Ports 1
and 3. The no is e is due to ex te rnal bus capacitanc e di sc ha rgin g in to the Port 0 and Port 2 pin s whe n the se pin s mak e 1 to 0
transitio ns during bus o pera t io n. In the w ors t ca se s (capacitive l oad ing 100 pF), the noi se p uls e on th e ALE line may e xc ee d
0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary.
5. T y pical value s are ba sed on a li mited number of s ampl es and a re n ot guara nteed. T he val ues li sted ar e at room tempe rature
and 5V.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port:
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related sp ecification. Pins are not guaranteed to sink current greater
than the listed test conditions.
Figure 71. ICC Test Condition, Active Mode
RRST RST Pull-down Resistor 50 200(5) 250 kΩ
IIL Logical 0 Input Current ports 1, 2, 3, 4 and 5 -50 μAV
IN = 0.45V
ILI Input Leakage Current ±10 μA 0.45V < VIN < VCC
ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4 -650 μAV
IN = 2.0V
CIO Capacitance of I/O Buffer 10 pF FC = 3 MHz
TA = 25°C
IPD Power-down Current 75 150 μA2.7 < V
CC < 5. 5V(3)
ICCOP Power Supply Current on normal mode 0.4 x Frequency (MHz) + 5 m A VCC = 5.5V(1)
ICCIDLE Power Supply Current on idle mode 0.3 x Frequency (MHz) + 5 m A VCC = 5.5V(2)
ICCWRITE Power Supply Current on flash write 0.8 x Frequency (MHz) + 15 mA VCC = 5.5V
tWRITE Flash programming time 7 10 ms 2. 7 < VCC < 5.5V
TA = -40°C to +85°C; VSS = 0V; VCC =2.7V to 5.5V; F = 0 to 40 MHz (Continued)
Symbol P arameter Min Typ Max Unit Test Conditions
EA
VCC
VCC
ICC
(NC)
CLOCK
SIGNAL
VCC
All other pins are disconnected.
RST
XTAL2
XTAL1
VSS
VCC
P0
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Figure 72. ICC Test Condition, Idle Mode
Figure 73. ICC Test Condition, Power-down Mode
Figure 74. Clock Signal Waveform for ICC Tests in Active and Idle Modes
AC Parameters
Explanation of the AC
Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The
other c haracter s, depen ding on thei r posi tions, stand for t he nam e of a signa l or the lo gical s ta-
tus of that signal. The following is a list of all the characters and what they stand for.
Example:TAVLL = Time for Addres s Val id to ALE Low.
TLLPL = Time for ALE Low to PSEN Low.
(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs =
80 pF.)
Table 119 Table 122, and Table 125 give the description of each AC symbols.
Table 120, Table 121, Table 123 and Table 126 gives the range for each AC parameter.
Table 120, Table 121 and Table 127 give the frequency derating formula of the AC parameter
for eac h sp eed r ang e d es crip tio n. T o c al cu lat e e ac h A C sy mb ols . Take the x val ue i n th e cor re-
sponding column (-M or -L) and use this value in the formula.
RST EA
XTAL2
XTAL1
VSS
VCC
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
CLOCK
SIGNAL
RST EA
XTAL2
XTAL1
VSS
VCC
VCC
ICC
(NC)
P0
VCC
All other pins are disconnected.
VCC-0.5V
0.45V 0.7VCC
0.2VCC-0.1
TCLCH
TCHCL
TCLCH = TCHCL = 5ns.
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Example: TLLIU for -M and 20 MHz, Standard clock.
x = 35 ns
T 50 ns
TCCIV = 4T - x = 165 ns
Exte rn al Pr og r am
Memory
Characteristics
Table 119. Symbol Description
Table 120. AC Parameters for a Fix Clock
Notes: 1. ‘ -L ‘ refers to 2V - 5.5V version.
2. ‘ -M ’ refers to 4.5V to 5.5V version.
Symbol Parameter
T Oscillator clock period
TLHLL ALE pulse width
TAVLL Address Valid to ALE
TLLAX Address Hol d After AL E
TLLIV ALE to Valid Instruction In
TLLPL ALE to PSEN
TPLPH PSEN Pulse Width
TPLIV PSEN to Valid Instruction In
TPXIX Input Instruction Hold After PSEN
TPXIZ Input Instruction Float After PSEN
TAVIV Address to Valid Instruction In
TPLAZ PSEN Low to Address Float
Symbol -M(1) -L(2) Units
Min Max Min Max
T25 25 ns
TLHLL 35 35 ns
TAVLL 55ns
TLLAX 55ns
TLLIV n 65 65 ns
TLLPL 55ns
TPLPH 50 50 ns
TPLIV 30 30 ns
TPXIX 00ns
TPXIZ 10 10 ns
TAVIV 80 80 ns
TPLAZ 10 10 ns
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Table 121. AC Parameters for a Variable Clock
Notes: 1. ‘ -L ‘ refers to 2V - 5.5V version.
2. ‘ -M ’ refers to 4.5V to 5.5V version.
Symbol Type Standard
Clock X2 Clock X parameter for
-M(1) range X parameter for
-L(2) range Units
TLHLL Min 2 T - x T - x 15 15 ns
TAVLL Min T - x 0.5 T - x 20 20 ns
TLLAX Min T - x 0.5 T - x 20 20 ns
TLLIV Max 4 T - x 2 T - x 35 35 ns
TLLPL Min T - x 0.5 T - x 15 15 ns
TPLPH Min 3 T - x 1.5 T - x 25 25 ns
TPLIV Max 3 T - x 1.5 T - x 45 45 ns
TPXIX Min x x 0 0 ns
TPXIZ Max T - x 0.5 T - x 15 1 5 ns
TAVIV Max 5 T - x 2.5 T - x 45 45 ns
TPLAZ Max x x 10 10 ns
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Exte rn al Pr og r am
Memory Read Cycle
Exte rnal Data Memory
Characteristics Table 122. Symbol Description
TPLIV
TPLAZ
ALE
PSEN
PORT 0
PORT 2
A0-A7A0-A7 INSTR ININSTR IN INSTR IN
ADDRESS
OR SFR-P2 ADDRESS A8-A15ADDRESS A8-A15
12 TCLCL
TAVIV
TLHLL
TAVLL
TLLIV
TLLPL
TPLPH
TPXAV
TPXIX
TPXIZ
TLLAX
Symbol Parameter
TRLRH RD Pul se W idth
TWLWH WR Pulse Width
TRLDV RD to Valid Data In
TRHDX Data Hold After RD
TRHDZ Dat a Float After RD
TLLDV ALE to Valid D a ta In
TAVDV Address to Valid Data In
TLLWL AL E to WR or RD
TAVWL Address to WR or RD
TQVWX Data Valid to WR Transition
TQVWH Data Set-up to WR High
TWHQX Dat a Hold After WR
TRLAZ RD Low to Address Float
TWHLH RD or WR High to ALE high
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Table 123. AC Parameters for a Fix Clock
Notes: 1. ‘ -L ‘ refers to 2V - 5.5V version.
2. ‘ -M ’ refers to 4.5V to 5.5V version.
Symbol
-M(1) -L(2)
UnitsMin Max Min Max
TRLRH 125 125 ns
TWLWH 125 125 ns
TRLDV 95 95 ns
TRHDX 00ns
TRHDZ 25 25 ns
TLLDV 155 155 ns
TAVDV 160 160 ns
TLLWL 45 105 45 105 ns
TAVWL 70 70 ns
TQVWX 55ns
TQVWH 155 155 ns
TWHQX 10 10 ns
TRLAZ 00ns
TWHLH 5 45 5 45 ns
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Notes: 1. ‘ -L ‘ refers to 2V - 5.5V version.
2. ‘ -M ’ refers to 4.5V to 5.5V version.
Exte rnal Data Memory
Write Cycle
Table 124. AC Parameters for a Variable Clock
Symbol Type Standard
Clock X2 Clock X param eter for
-M(1) range X parameter for
-L(2) range Units
TRLRH Min 6 T - x 3 T - x 25 25 ns
TWLWH Mi n 6 T - x 3 T - x 2 5 25 ns
TRLDV Max 5 T - x 2.5 T - x 30 30 ns
TRHDX Min x x 0 0 ns
TRHDZ Max 2 T - x T - x 25 25 ns
TLLDV Max 8 T - x 4T -x 45 45 ns
TAVDV Max 9 T - x 4.5 T - x 65 65 ns
TLLWL Min 3 T - x 1.5 T - x 30 30 ns
TLLWL M a x 3 T + x 1.5 T + x 30 30 ns
TAVWL Min 4 T - x 2 T - x 30 30 ns
TQVWX Min T - x 0.5 T - x 20 20 ns
TQVWH Min 7 T - x 3.5 T - x 20 20 ns
TWHQX Min T - x 0 .5 T - x 15 15 ns
TRLAZ Max x x 0 0 ns
TWHLH Min T - x 0.5 T - x 20 20 ns
TWHLH Max T + x 0.5 T + x 20 20 ns
TQVWH
TLLAX
ALE
PSEN
WR
PORT 0
PORT 2
A0-A7 DATA OUT
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TQVWX
ADDRESS A8-A15 OR SFR P2
TWHQX
TWHLH
TWLWH
174 7663E–8051–10/08
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External Data Memory Read Cycle
Serial Port Timing -
Shift Register Mode Table 125. Symbol Description
Table 126. AC Parameters for a Fix Clock
Notes: 1. ‘ -L ‘ refers to 2V - 5.5V version.
2. ‘ -M ’ refers to 4.5V to 5.5V version.
ALE
PSEN
RD
PORT 0
PORT 2
A0-A7 DATA IN
ADDRESS
OR SFR-P2
TAVWL
TLLWL
TRLAZ
ADDRESS A8- A15 OR SFR P2
TRHDZ
TWHLH
TRLRH
TLLDV
TRHDX
TLLAX
TAVDV
Symbol Parameter
TXLXL Serial port cl ock cycle time
TQVHX Output data set-up to clock rising edge
TXHQX Output data hold after clock rising edge
TXHDX Input data hold after clock rising edge
TXHDV Clock rising edge to input data valid
Symbol
-M(1) -L(2)
UnitsMin Max Min Max
TXLXL 300 300 ns
TQVHX 200 200 ns
TXHQX 30 30 ns
TXHDX 00ns
TXHDV 117 117 ns
175
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Table 127. AC Parameters for a Variable Clock
Notes: 1. ‘ -L ‘ refers to 2V - 5.5V version.
2. ‘ -M ’ refers to 4.5V to 5.5V version.
Shif t Register Timing
Waveforms
External Clo ck Driv e
Waveforms
AC Testing
Input/Output
Waveforms
AC inputs during testing are driven at VCC - 0.5 for a logic “ 1” and 0.45V for a logic “0”. Timing
measurement are made at VIH min. for a logic “1” and VIL max for a logic “0”.
Float Waveforms
Symbol Type Standard
Clock X2 Clock X Parameter For
-M(1) Range X Parameter For
-L(2) Range Units
TXLXL Min 12 T 6 T ns
TQVHX Min 10 T - x 5 T - x 50 50 ns
TXHQX Min 2 T - x T - x 20 20 n s
TXHDX Min x x 0 0 ns
TXHDV Max 10 T - x 5 T- x 133 133 ns
INPUT DATA VALIDVALID VALID VALID
0123456 87
ALE
CLOCK
OUTPUT DATA
WRIT E to SBUF
CLEAR RI
TXLXL
TQVXH TXHQX
TXHDV TXHDX SET TI
SET RI
INSTRUCTION
01234567
VALID VALID VALID VALID
VCC-0.5V
0.45V
0.7VCC
0.2VCC-0.1
TCHCL TCLCX TCLCL
TCLCH
TCHCX
INPUT/OUTPUT 0.2 VCC + 0.9
0.2 VCC - 0.1
VCC -0.5V
0.45V
FLOAT
VOH - 0.1V
VOL + 0.1V
VLOAD VLOAD + 0.1V
VLOAD - 0.1V
176 7663E–8051–10/08
AT89C51RE2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage
occur s and beg ins to fl oat wh en a 10 0 mV cha nge fro m the load ed VOH/VOL level occurs. IOL/IOH
≥ ± 20 mA.
Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.
Figure 75. Internal Clock Sign als
This diagr am indic ates when signal s ar e clo cked i nter na lly. The time i t takes the sig nal s to propagate to the pins , howe ve r,
ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propaga-
tion also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD and WR propagation
delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC
specifications.
DATA PCL OUT DATA PCL OUT DATA PCL OUT
SAMPLED SAMPLED SAMPLED
STATE4 STATE5 STATE6 STATE1 STATE2 STATE3 STATE4 STATE5
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
FLOAT FLOAT FLOAT
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INS TRUC TION
INDICATES ADDR ESS TRANSI T IO N S
EXTERNAL PROGRAM MEMORY FETCH
FLOAT
DATA
SAMPLED
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
PCL OUT (EVEN IF PROGRAM
MEMORY IS IN T E RN AL)
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
OLD DATANEW DATA P0 PINS SAMPLED
P1, P2, P3 PINS SAMP L ED P1, P2, P3 PINS SAMPLED
P0 PIN S SAMPL ED
RXD SAMPLED
INTERNAL
CLOCK
XTAL2
ALE
PSEN
P0
P2 (EX T )
READ CYCLE
WRITE CYCLE
RD
P0
P2
WR
PORT OPERATION
MOV PORT SRC
MOV DEST P0
MOV DEST PORT (P1. P2. P3)
(INC L U D ES INTO. IN T1. TO T1)
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
DATA OUT
DPL OR Rt OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P0
P2
RXD SAMPLED
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Flash Memory Table 128. Timing Symbol Definitions
Table 129. Memory AC Timing
VDD = 3V to 5.5V, TA = -40 to +85°C
Figure 76. Flash Memory – ISP Waveforms
Figure 77. Flash Memory – Internal Busy Waveforms
Signals Conditions
S (Hardware
condition) PSEN#,EA L Low
RRST VValid
B FBUSY flag X No Longer Valid
Symbol Parameter Min Typ Max Unit
TSVRL Input PSEN# Valid to RST Edge 50 ns
TRLSX Input PSEN# Hold after RST Edge 50 ns
TBHBL Flash Internal Busy (Programming) Time 10 ms
NFCY Number of Flash Erase/Write Cycles 100 000 cycles
TFDR Flash Retention Ti me 10 years
RST TSVRL
PSEN#1
TRLSX
FBUSY bit TBHBL
178 7663E–8051–10/08
AT89C51RE2
Ordering Information
Table 130. Possible Order Entries
Part Number Supply Voltage Temperature Range Package
AT89C51RE2-SLSUM 2.7V-5.5V Industrial & Green PLCC44
AT89C51RE2-RLTUM VQFP44
AT89C51RE2-SLSEM 2.7V -5. 5V Engineering Samples PLCC44
AT89C51RE2-RLTEM VQFP44
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Packaging Information
PLCC44
180 7663E–8051–10/08
AT89C51RE2
STANDARD NOTES FOR PLCC
1/ CONTROLLING DIMENSIONS : INCHES
2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982.
3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS.
MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm (.008 INCH) PER
SIDE.
181
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VQFP44
182 7663E–8051–10/08
AT89C51RE2
STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP
1/ CONTROLLING DIMENSIONS : INCHES
2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M -
1982.
3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS.
MOLD PROTUSIONS SHALL NOT EXCEED 0.25 mm (0.010 INCH).
THE TOP PACKAGE BODY SIZE MAY BE SMALLER THAN THE BOTTOM
PACKAGE BODY SIZE BY AS MUCH AS 0.15 mm.
4/ DATUM PLANE "H" LOCATED AT MOLD PARTING LINE AND
COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT
BOTTOM OF PARTING LINE.
5/ DATUM "A" AND "D" TO BE DETERMINED AT DATUM PLANE H.
6/ DIMENSION " f " DOES NOT INCLUDE DAMBAR PROTUSION ALLOWABLE
DAMBAR PROTUSION SHALL BE 0.08mm/.003" TOTAL IN EXCESS OF THE
" f " DIMENSION AT MAXIMUM MATERIAL CONDITION .
DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
183
7663E–8051–10/08
AT89C51RE2
Document
Revision
History
Changes from
7663B to 7663C 1. Modified ordering information.
2. Various grammatical corections throughout document.
Changes from
7663C to 7663D 1. TWI interfac e added .
Changes from
7663D to 7663E 1. Removed 64 and 68 pins package product version.
2. Minor correction on Table 69 on page 102.
17663E–8051–10/08
AT89C51RE2
Features ................................................................................................. 1
Description ............................................................................................ 2
Block Diagram ...................................................................................... 3
Pin Configurations ............................................................................... 4
SFR Mapping ......................................................................................... 7
Enhanced Features ......... ..... ..... .... ..................................................... 13
X2 Feature.......................................................................................................... 13
Dual Data Pointer Register DPTR ..................................................... 18
Memory Architecture ...........................................................................................21
Expanded RAM (XRAM) ....... ..... .... ..... ............................ ..... ............... 22
Registers............................................................................................................. 24
Extended Stack................................................................................................... 25
Flash Memory ..................................................................................... 27
General Description............................................................................................ 27
Features.............................................................................................................. 27
Flash memory organization ................................................................................ 27
On-Chip Flash memory....................................................................................... 28
On-Chip ROM bootloader................................................................................... 31
Boot process....................................................................................................... 32
Access and Operations Descriptions.................................................................. 36
Operation Cross Memory Access ..................................................... 50
Sharing Instructions ........................................................................... 50
Flash Protection from Parallel Programming .................................. 52
Bootloader Architecture .................................................................... 53
Introduction......................................................................................................... 53
Bootloader Description ....................................................................................... 54
ISP Protocol Description..................................................................................... 56
Protocol............................................................................................................... 57
ISP Commands description................................................................................ 61
Timers/Counters ................................................................................. 68
Timer/Counter Operations.................................................................................. 68
Timer 0................................................................................................................ 68
Timer 1................................................................................................................ 71
2
7663E–8051–10/08
AT89C51RE2
Interrupt .............................................................................................................. 71
Registers............................................................................................................. 73
Timer 2 ................................................................................................. 77
Auto-Reload Mode.............................................................................................. 77
Programmable Clock-Output.............................................................................. 78
Registers............................................................................................................. 80
Programmable Counter Array PCA ................................................... 82
PCA Capture Mode............................................................................................. 90
16-bit Software Timer/ Compare Mode............................................................... 90
High Speed Output Mode................................................................................... 91
Pulse Width Modulator Mode.............................................................................. 92
PCA Watchdog Timer......................................................................................... 93
Serial I/O Port ...................................................................................... 94
Framing Error Detection ..................................................................................... 94
Automatic Address Recognition.......................................................................... 95
Registers............................................................................................................. 97
Baud Rate Selection for UART 0 for Mode 1 and 3............................................ 98
Baud Rate Selection for UART 1 for Mode 1 and 3............................................ 99
UART Registers................................................................................................ 103
Interrupt System ............................................................................... 109
Registers........................................................................................................... 110
Interrupt Sources and Vector Addresses.......................................................... 117
Power Management .......................................................................... 118
Introduction....................................................................................................... 118
Idle Mode.......................................................................................................... 118
Power-Down Mode........................................................................................... 118
Registers........................................................................................................... 121
Oscillator ........................................................................................... 122
Registers........................................................................................................... 122
Functional Block Diagram .................................................................................123
Hardware Watchdog Timer .............................................................. 124
Using the WDT ................................................................................................. 124
WDT During Power Down and Idle................................................................... 125
Reduced EMI Mode ........................................................................... 126
Keyboard Interface ........................................................................... 127
Registers........................................................................................................... 128
37663E–8051–10/08
AT89C51RE2
2-wire Interface (TWI) ....................................................................... 131
Description........................................................................................................ 133
Notes ................................................................................................................ 136
Registers........................................................................................................... 146
Serial Port Interface (SPI) ................................................................ 149
Features............................................................................................................ 149
Signal Description............................................................................................. 149
Functional Description ...................................................................................... 151
Power Monitor ................................................................................... 161
Description........................................................................................................ 161
Power-off Flag ................................................................................... 163
Reset .................................................................................................. 164
Introduction....................................................................................................... 164
Reset Input .................. ....... ...... ....... ................... ...... ....... ...... ....... ...... ....... ...... . 164
Reset Output ......... ...... .................... ...... ...... ....... ...... ....... ...... .................... ...... ..16 5
Electrical Characteristics ................................................................. 166
Absolute Maximum Ratings ..............................................................................166
DC Parameters .................................................................................................166
AC Parameters................................................................................................. 168
Ordering Information ........................................................................ 178
Packaging Information ..................................................................... 179
PLCC44............................................................................................................ 179
VQFP44............................................................................................................ 181
Document Revision Histor y .......... ..... ..... .... ..................................... 183
Changes from 7663B to 7663C........................................................................ 183
Changes from 7663C to 7663D........................................................................ 183
Changes from 7663D to 7663E........................................................................ 183
7663E–8051–10/08
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