SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 FEATURES D 1-A Low-Dropout Voltage Regulator D Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, D D D D D D D 3.0-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions Dropout Voltage Down to 230 mV at 1 A (TPS76850) Ultralow 85-A Typical Quiescent Current Fast Transient Response 2% Tolerance Over Specified Conditions for Fixed-Output Versions Open Drain Power Good (See TPS767xx for Power-On Reset With 200-ms Delay Option) 20-Pin TSSOP (PWP)PowerPAD Package Thermal Shutdown Protection description This device is designed to have a fast transient response and be stable with 10-F low ESR capacitors. This combination provides high performance at a reasonable cost. SUPPORTS DEFENSE, AEROSPACE AND MEDICAL APPLICATION D D D D D D D Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (-555C/1255C) Temperature Range{ Extended Product LIfe Cycle Extended Product-Change Notification Product Traceability Additional temperature ranges are available - contact factory. PWP PACKAGE (TOP VIEW) GND/HSINK GND/HSINK GND NC EN IN IN NC GND/HSINK GND/HSINK 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 GND/HSINK GND/HSINK NC NC PG FB/NC OUT OUT GND/HSINK GND/HSINK 12 Because the PMOS device behaves as a low-value 10 11 resistor, the dropout voltage is very low (typically 230 mV at an output current of 1 A for the TPS76850) and NC - No internal connection is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 85 A over the full range of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 A at TJ = 25C. 9 Power good (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. The TPS768xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 5.5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS768xx family is available in a 20-pin PWP package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. Copyright 2008, Texas Instruments Incorporated !"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2 #++ )#!#"($(!%- POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 description (continued) TPS76833 DROPOUT VOLTAGE vs FREE-AIR TEMPERATURE LOAD TRANSIENT RESPONSE 103 VO - Change in Output Voltage - mV 100 102 101 I O - Output Current - A VDO - Dropout Voltage - mV IO = 1 A IO = 10 mA 100 10-1 IO = 0 Co = 10 F 10-2 -60 -40 -20 0 20 40 60 80 100 120 140 Co = 10 F TA = 25C 50 0 -50 -100 1 0.5 0 0 TA - Free-Air Temperature - C 100 200 300 400 500 600 700 800 900 1000 t - Time - s ORDERING INFORMATION TJ OUTPUT VOLTAGE (V) PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING TYP 5.0 TPS76850QPWPREP 76850EP 3.3 TPS76833QPWPREP TPS76830QPWPREP 76833EP 76830EP TPS76828QPWPREP TPS76827QPWPREP 76828EP 76827EP 2.5 TPS76825QPWPREP 76825EP 1.8 TPS76818QPWPREP 76818EP 1.5 TPS76815QPWPREP 76815EP Adjustable 1.2 V to 5.5 V TPS76801QPWPREP 76801EP TPS76801MPWPREP 76801ME 3.0 2.8 -40C to 125C -55 C to 125C 125 C -55C 2.7 Adjustable 1.2 V to 5.5 V TSSOP - PWP TSSOP - PWP Tape and reel Tape and reel 5.0 TPS76850MPWPREP 76850ME For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. This device is Product Preview. The TPS76801 is programmable using an external resistor divider (see application information). The PWP package is available taped and reeled. Note R suffix to the device type (e.g., TPS76801QPWPREP). 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 description (continued) TPS768xx 6 VI IN PG 16 PG 7 IN OUT 5 0.1 F OUT EN 14 VO 13 + GND Co 10 F 3 See application information section for capacitor selection details. Figure 1. Typical Application Configuration (For Fixed Output Options) functional block diagram--adjustable version IN EN PG _ + OUT + _ R1 Vref = 1.1834 V FB/NC R2 GND External to the device POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 functional block diagram--fixed-voltage version IN EN PG _ + OUT + _ R1 Vref = 1.1834 V R2 GND Terminal Functions PWP Package TERMINAL NAME NO. I/O DESCRIPTION GND/HSINK 1 Ground/heatsink GND/HSINK 2 Ground/heatsink GND 3 LDO ground NC 4 No connect EN 5 I Enable input IN 6 I Input IN 7 I Input NC 8 No connect GND/HSINK 9 Ground/heatsink GND/HSINK 10 Ground/heatsink GND/HSINK 11 Ground/heatsink GND/HSINK 12 OUT 13 O Regulated output voltage OUT 14 O Regulated output voltage FB/NC 15 I Feedback input voltage for adjustable device (no connect for fixed options) PG 16 O PG output NC 17 No connect NC 18 No connect GND/HSINK 19 Ground/heatsink GND/HSINK 20 Ground/heatsink 4 Ground/heatsink POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 13.5 V Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to VI + 0.3 V Maximum PG voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table Output voltage, VO (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network terminal ground. DISSIPATION RATING TABLE - FREE-AIR TEMPERATURES PACKAGE AIR FLOW (CFM) PWP PWP TA < 25C POWER RATING DERATING FACTOR ABOVE TA = 25C TA = 70C POWER RATING TA = 85C POWER RATING 0 2.9 W 23.5 mW/C 1.9 W 1.5 W 300 4.3 W 34.6 mW/C 2.8 W 2.2 W 0 3W 23.8 mW/C 1.9 W 1.5 W 300 7.2 W 57.9 mW/C 4.6 W 3.8 W This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in x 5-in PCB, 1 oz. copper, 2-in x 2-in coverage (4 in2). This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in x 2-in PCB, 1 oz. copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002. recommended operating conditions MIN Input voltage, VI# Output voltage range, VO Output current, IO (see Note 1) MAX UNIT 2.7 10 V 1.2 5.5 V 0 1.0 A Operating virtual junction temperature, TJ (see Note 1) -40 125 C # To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load). NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the device operate under conditions beyond those specified in this table for extended periods of time. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature range, VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 F (unless otherwise noted) PARAMETER TEST CONDITIONS TPS76801 5.5 V VO 1.5 V, 5.5 V VO 1.5 V, MIN TJ = 25C TJ = -40C to 125C TPS76815 TJ = 25C, TJ = -40C to 125C, 2.7 V < VIN < 10 V TPS76818 TJ = 25C, TJ = -40C to 125C, 2.8 V < VIN < 10 V TPS76825 TJ = 25C, TJ = -40C to 125C, TPS76827 TJ = 25C, TJ = -40C to 125C, 3.7 V < VIN < 10 V TPS76828 TJ = 25C, TJ = -40C to 125C, 3.8 V < VIN < 10 V TPS76830 TJ = 25C, TJ = -40C to 125C, 4 V < VIN < 10 V TPS76833 TJ = 25C, TJ = -40C to 125C, TPS76850 TJ = 25C, TJ = -40C to 125C, 6 V < VIN < 10 V Quiescent current (GND current) EN = 0V, (see Note 2) 10 A < IO < 1 A, TJ = 25C TJ = -40C to 125C Output voltage line regulation (VO/VO) (see Notes 2 and 3) VO + 1 V < VI 10 V, TJ = 25C Output voltage (10 A to 1 A load) (see Note 2) IO = 1 A, 2.7 V < VIN < 10 V 1.5 2.450 2.7 2.744 FB input current TPS76801 3.060 3.366 5.0 4.900 5.100 85 125 TJ = 25C, EN = VI, 2.7 V < VI < 10 V TJ = -40C to 125C %/V 3 mV 55 Vrms 1 A V 0.9 f = 1 KHz, Co = 10 F, Power supply ripple rejection (see Note 2) 60 TJ = 25C NOTES: 2. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 10 V. 3. If VO 1.8 V then VImax = 10 V, VImin = 2.7 V: V O VImax * 2.7 V 100 If VO 2.5 V then VImax = 10 V, VImin = VO + 1 V: Line Reg. (mV) + %V V O 1000 VImax * VO ) 1 V POST OFFICE BOX 655303 100 * DALLAS, TEXAS 75265 1000 A nA 1.7 Low level enable input voltage Line Reg. (mV) + %V A C 2 High level enable input voltage 6 2 150 10 FB = 1.5 V A A 0.01 1.7 Thermal shutdown junction temperature Standby current 2.856 3.3 Load regulation EN = VI, 2.7 V < VI < 10 V V 3.0 3.234 VO = 0 V 2.754 2.8 4.3 V < VIN < 10 V Output current limit 2.550 2.646 2.940 Output noise voltage (TPS76818) 1.836 2.5 4 V < VIN < 10 V 4.3 V < VIN < 10 V BW = 200 Hz to 100 kHz, Co = 10 F, IC = 1 A, TJ = 25C 1.530 1.8 3.5 V < VIN < 10 V 6 V < VIN < 10 V UNIT 1.02VO 1.470 1.764 3.8 V < VIN < 10 V MAX VO 0.98VO 2.8 V < VIN < 10 V 3.5 V < VIN < 10 V 3.7 V < VIN < 10 V TYP V dB SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 electrical characteristics over recommended operating free-air temperature range, VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 F (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Trip threshold voltage IO(PG) = 300 A VO decreasing Hysteresis voltage Measured at VO Output low voltage VI = 2.7 V, V(PG) = 5 V Minimum input voltage for valid PG PG Leakage current Input current (EN) MIN TYP UNIT 98 %VO %VO 1.1 92 V 0.5 IO(PG) = 1 mA 0.15 EN = 0 V -1 EN = VI -1 0 0.4 V 1 A 1 A A 1 IO = 1 A, IO = 1 A, TJ = 25C TJ = -40C to 125C 500 TPS76828 TJ = 25C TJ = -40C to 125C 450 TPS76830 IO = 1 A, IO = 1 A, TJ = 25C TJ = -40C to 125C 350 TPS76833 IO = 1 A, IO = 1 A, IO = 1 A, IO = 1 A, TJ = 25C TJ = -40C to 125C 230 TPS76850 Dropout voltage (see Note 4) MAX 825 675 mV 575 380 NOTE 4: IN voltage equals VO(typ) - 100 mV; TPS76801 output voltage set to 3.3 V nominal with external resistor divider. TPS76815, TPS76818, TPS76825, and TPS76827 dropout voltage limited by input voltage range limitations (i.e., TPS76830 input voltage needs to drop to 2.9 V for purpose of this test). TYPICAL CHARACTERISTICS Table of Graphs FIGURE VO Zo VDO Output voltage vs Output current 2, 3, 4 vs Free-air temperature 5, 6, 7 Ground current vs Free-air temperature 8, 9 Power supply ripple rejection vs Frequency 10 Output spectral noise density vs Frequency 11 Input voltage (min) vs Output voltage 12 Output impedance vs Frequency 13 Dropout voltage vs Free-air temperature Line transient response Load transient response VO 14 15, 17 16, 18 Output voltage vs Time Dropout voltage vs Input voltage Equivalent series resistance (ESR) vs Output current POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 19 20 22 - 25 7 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TPS76815 TPS76833 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs OUTPUT CURRENT 1.4985 3.2835 VI = 4.3 V TA = 25C 1.4980 VO - Output Voltage - V VO - Output Voltage - V 3.2830 VI = 2.7 V TA = 25C 3.2825 3.2820 3.2815 3.2810 1.4975 1.4970 1.4965 1.4960 1.4955 3.2805 1.4950 3.2800 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 IO - Output Current - A 0.9 0 1 0.1 0.2 0.3 Figure 2 0.6 0.7 0.8 TPS76825 TPS76833 OUTPUT VOLTAGE vs OUTPUT CURRENT OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 0.9 1 3.32 VI = 3.5 V TA = 25C 2.4955 VI = 4.3 V 3.31 VO - Output Voltage - V 2.4950 VO - Output Voltage - V 0.5 Figure 3 2.4960 2.4945 2.4940 2.4935 2.4930 3.30 3.29 IO = 1 A IO = 1 mA 3.28 3.27 3.26 2.4925 2.4920 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 3.25 -60 -40 -20 0 20 40 Figure 4 Figure 5 POST OFFICE BOX 655303 60 80 100 120 140 TA - Free-Air Temperature - C IO - Output Current - A 8 0.4 IO - Output Current - A * DALLAS, TEXAS 75265 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TPS76815 TPS76825 OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 1.515 2.515 VI = 3.5 V VI = 2.7 V 2.510 VO - Output Voltage - V 1.505 1.500 IO = 1 A IO = 1 mA 1.495 1.490 2.505 2.500 IO = 1 A 2.495 IO = 1 mA 2.490 2.485 1.485 -60 -40 -20 0 20 40 60 80 2.480 -60 -40 100 120 140 TA - Free-Air Temperature - C -20 0 20 40 60 80 100 120 TA - Free-Air Temperature - C Figure 6 Figure 7 TPS76833 GROUND CURRENT vs FREE-AIR TEMPERATURE 92 90 VI = 4.3 V 88 Ground Current - A VO - Output Voltage - V 1.510 86 84 82 IO = 1 mA 80 IO = 1 A 78 IO = 500 mA 76 74 72 -60 -40 -20 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - C Figure 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TPS76815 TPS76833 GROUND CURRENT vs FREE-AIR TEMPERATURE POWER SUPPLY RIPPLE REJECTION vs FREQUENCY 90 PSRR - Power Supply Ripple Rejection - dB 100 VI = 2.7 V Ground Current - A 95 90 IO = 1 A IO = 1 mA 85 IO = 500 mA 80 75 -60 -40 -20 0 20 40 60 80 70 60 50 40 30 20 10 0 -10 10 100 120 140 VI = 4.3 V Co = 10 F IO = 1 A TA = 25C 80 100 TA - Free-Air Temperature - C Figure 9 Figure 10 TPS76833 OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY Output Spectral Noise Density - V Hz 10-5 VI = 4.3 V Co = 10 F TA = 25C IO = 7 mA 10-6 IO = 1 A 10-7 10-8 102 103 104 f - Frequency - Hz Figure 11 10 1k 10k f - Frequency - Hz POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 105 100k 1M SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS INPUT VOLTAGE (MIN) vs OUTPUT VOLTAGE 4 IO = 1 A VI - Input Voltage (Min) - V TA = 25C TA = 125C 3 TA = -40C 2.7 2 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 VO - Output Voltage - V Figure 12 TPS76833 TPS76833 OUTPUT IMPEDANCE vs FREQUENCY DROPOUT VOLTAGE vs FREE-AIR TEMPERATURE 103 0 IO = 1 A VDO - Dropout Voltage - mV Zo - Output Impedance - VI = 4.3 V Co = 10 F TA = 25C IO = 1 mA 10-1 IO = 1 A 102 101 IO = 10 mA 100 10-1 IO = 0 Co = 10 F 10-2 101 102 103 104 f - Frequency - kHz 105 106 10-2 -60 -40 -20 0 20 40 60 80 100 120 140 TA - Free-Air Temperature - C Figure 13 Figure 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TPS76815 TPS76815 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE VO - Change in Output Voltage - mV VI - Input Voltage - V 100 3.7 2.7 Co = 10 F TA = 25C 50 0 -50 I O - Output Current - A VO - Change in Output Voltage - mV -100 10 0 -10 Co = 10 F TA = 25C 0 20 40 60 1 0.5 0 0 80 100 120 140 160 180 200 t - Time - s 100 200 300 400 500 600 700 800 900 1000 t - Time - s Figure 16 TPS76833 TPS76833 LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE 100 VO - Change in Output Voltage - mV VI - Input Voltage - V Figure 15 Co = 10 F TA = 25C 5.3 I O - Output Current - A VO - Change in Output Voltage - mV 4.3 10 0 -10 0 20 40 60 80 100 120 140 160 180 200 t - Time - s Co = 10 F TA = 25C 50 0 -50 -100 1 0.5 0 0 100 200 300 400 500 600 700 800 900 1000 t - Time - s Figure 18 Figure 17 12 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TPS76833 TPS76801 OUTPUT VOLTAGE vs TIME (AT STARTUP) DROPOUT VOLTAGE vs INPUT VOLTAGE 900 IO = 1 A Co = 10 F IO = 1 A TA = 25C 3 800 VDO - Dropout Voltage - mV VO- Output Voltage - V 4 2 1 Enable Pulse - V 0 700 600 500 TA = 25C 400 TA = 125C 300 200 TA = -40C 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 t - Time - ms 0.9 1 2.5 3.5 4 VI - Input Voltage - V 4.5 5 Figure 20 Figure 19 VI 3 To Load IN OUT + EN Co GND RL ESR Figure 21. Test Circuit for Typical Regions of Stability (Figures 22 through 25) (Fixed Output Options) POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 TYPICAL CHARACTERISTICS TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 ESR - Equivalent Series Resistance - ESR - Equivalent Series Resistance - 10 Region of Instability 1 Region of Stability VO = 3.3 V Co = 4.7 F VI = 4.3 V TA = 25C 0.1 0 200 400 600 800 Region of Instability VO = 3.3 V Co = 4.7 F VI = 4.3 V TJ = 125C 1 Region of Stability 0.1 1000 0 200 IO - Output Current - mA 400 Figure 22 800 1000 Figure 23 TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITY EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT EQUIVALENT SERIES RESISTANCE vs OUTPUT CURRENT 10 10 ESR - Equivalent Series Resistance - ESR - Equivalent Series Resistance - 600 IO - Output Current - mA Region of Instability 1 Region of Stability VO = 3.3 V Co = 22 F VI = 4.3 V TA = 25C 0.1 0 200 400 600 800 1000 Region of Instability VO = 3.3 V Co= 22 F VI = 4.3 V TJ = 125C 1 Region of Stability 0.1 0 IO - Output Current - mA 200 400 600 800 1000 IO - Output Current - mA Figure 24 Figure 25 Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to Co. 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 APPLICATION INFORMATION The TPS768xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V, 3.3 V, and 5.0 V), and offers an adjustable device, the TPS76801 (adjustable from 1.2 V to 5.5 V). device operation The TPS768xx features very low quiescent current, which remains virtually constant even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the load current through the regulator (IB = IC/). The TPS768xx uses a PMOS transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range. Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into dropout. The resulting drop in forces an increase in IB to maintain the load. During power up, this translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation. The TPS768xx quiescent current remains low even when the regulator drops out, eliminating both problems. The TPS768xx family also features a shutdown mode that places the output in the high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 A. If the shutdown feature is not used, EN should be tied to ground. minimum load requirements The TPS768xx family is stable even at zero load; no minimum load is required for operation. FB - pin connection (adjustable version only) The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output voltage is sensed through a resistor divider network to close the loop as shown in Figure 27. Normally, this connection should be as short as possible; however, the connection can be made near a critical circuit to improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is essential. external capacitor requirements An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 F or larger) improves load transient response and noise rejection if the TPS768xx is located more than a few inches from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load transients with fast rise times are anticipated. Like all low dropout regulators, the TPS768xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10 F and the ESR (equivalent series resistance) must be between 50 m and 1.5 . Capacitor values 10 F or larger are acceptable, provided the ESR is less than 1.5 . Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Most of the commercially available 10 F surface-mount ceramic capacitors, including devices from Sprague and Kemet, meet the ESR requirements stated above. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 15 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 APPLICATION INFORMATION external capacitor requirements (continued) TPS768xx 6 VI 7 IN PG 5 PG 250 k IN OUT C1 0.1 F 16 OUT EN 14 VO 13 + GND Co 10 F 3 Figure 26. Typical Application Circuit (Fixed Versions) programming the TPS76801 adjustable LDO regulator The output voltage of the TPS76801 adjustable regulator is programmed using an external resistor divider as shown in Figure 27. The output voltage is calculated using: V O +V 1 ) R1 R2 ref (1) Where: Vref = 1.1834 V typ (the internal reference voltage) Resistors R1 and R2 should be chosen for approximately 50-A divider current. Lower value resistors can be used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 30.1 k to set the divider current at 50 A and then calculate R1 using: R1 + V V O *1 ref R2 (2) OUTPUT VOLTAGE PROGRAMMING GUIDE TPS76801 VI 0.1 F IN PG PG 250 k 1.7 V 0.9 V OUTPUT VOLTAGE EN OUT VO R1 FB / NC GND R1 R2 UNIT 2.5 V 33.2 30.1 k 3.3 V 53.6 30.1 k 3.6 V 61.9 30.1 k 4.75 V 90.8 30.1 k R2 Figure 27. TPS76801 Adjustable LDO Regulator Programming 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SGLS011B - MARCH 2003 - REVISED DECEMBER 2008 APPLICATION INFORMATION power-good indicator The TPS768xx features a power-good (PG) output that can be used to monitor the status of the regulator. The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as a low-battery indicator. PG does not assert itself when the regulated output voltage falls out of the specified 2% tolerance, but instead reports an output voltage low, relative to its nominal regulated value. regulator protection The TPS768xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be appropriate. The TPS768xx also features internal current limiting and thermal protection. During normal operation, the TPS768xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds 150C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130C(typ), regulator operation resumes. power dissipation and junction temperature Specified regulator operation is assured to a junction temperature of 125C; the maximum junction temperature should be restricted to 125C under normal operating conditions. This restriction limits the power dissipation the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: P T max * T A + J D(max) R qJA Where: TJmax is the maximum allowable junction temperature. RJA is the thermal resistance junction-to-ambient for the package, i.e., 172C/W for the 8-terminal SOIC and 32.6C/W for the 20-terminal PWP with no airflow. TA is the ambient temperature. The regulator dissipation is calculated using: P D + V *V I O I O Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the thermal protection circuit. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 17 PACKAGE OPTION ADDENDUM www.ti.com 12-Dec-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS76801MPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76801QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76815QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76818QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76825QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76833QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76850MPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS76850QPWPREP ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-01XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-02XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-03XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-04XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-08XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-09XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-10XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/03632-11XE ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 12-Dec-2008 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS76801-EP, TPS76815-EP, TPS76818-EP, TPS76825-EP, TPS76833-EP, TPS76850-EP : TPS76801, TPS76815, TPS76818, TPS76825, TPS76833, TPS76850 * Catalog: * Automotive: TPS76801-Q1, TPS76815-Q1, TPS76818-Q1, TPS76825-Q1, TPS76833-Q1, TPS76850-Q1 NOTE: Qualified Version Definitions: - TI's standard catalog product * Catalog * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) TPS76801MPWPREP HTSSOP PWP 20 2000 330.0 16.4 TPS76801QPWPREP HTSSOP PWP 20 2000 330.0 TPS76815QPWPREP HTSSOP PWP 20 2000 330.0 TPS76818QPWPREP HTSSOP PWP 20 2000 TPS76825QPWPREP HTSSOP PWP 20 W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.0 Q1 16.4 6.95 7.1 1.6 8.0 16.0 Q1 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS76833QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS76850MPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 TPS76850QPWPREP HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS76801MPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76801QPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76815QPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76818QPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76825QPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76833QPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76850MPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 TPS76850QPWPREP HTSSOP PWP 20 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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