UNISONIC TECHNOLOGIES CO., LTD
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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Copyright © 2010 Unisonic Technologies Co., Ltd QW-R103-002.E
CURRENT MODE PWM
CONTROL CIRCUITS
DESCRIPTION
The UTC UC3842A/3843A provide the necessary functions to
implement off-line or DC to DC fixed frequency current mode ,
controlled switching circuits with minimal external components.
FEATURES
*Low Start Up Current ( Typical 0.12mA )
*Automatic Feed Forward Compensation
*Pulse-by-Pulse Current Limiting
*Under-voltage Lockout with Hysteresis
*Double Pulse Suppr ession
*High Current Totem Pole Output to Drive MOSFET Directly
*Internally Trimmed Band Gap Reference
*500kHz Operation
ORDERING INFORMATION
Ordering Number
Normal Lead Free Plating Halogen Free Package Packing
UC3842A-D08-T UC3842AL-D08-T UC3842AP-D08-T DIP-8 Tube
UC3842A-S08-R UC3842AL-S08-R UC3842AP-S08-R SOP-8 Tape Reel
UC3842A-S08-T UC3842AL-S08-T UC3842AP-S08-T SOP-8 Tube
UC3843A-D08-T UC3843AL-D08-T UC3843AP-D08-T DIP-8 Tube
UC3843A-S08-R UC3843AL-S08-R UC3843AP-S08-R SOP-8 Tape Reel
UC3843A-S08-T UC3843AL-S08-T UC3843AP-S08-T SOP-8 Tube
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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PIN CONFIGURATION
RT/CT
Output
GND
1
2
3
4
8
7
5
6
Current Sense
COMP
VFB
VREF
VCC
BLOCK DIAGRAM
7
5
7
6
5
4
3
1
2
8
Internal
Bias
5V REF S/R
U.V.L.O
R
S
PWM
LATCH
ERROR
AMPLIFIER
1V
OSCILLATOR
VFB
COMP
CURRENT SENSE
RT/CT
Vcc
GND
OUTPUT
Vcc
GND
CURRENT
SENSE
COMPARATOR
VREF
1/2VRE
F
VREF
Good
Logic
1/3VREF
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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ABSOLUTE MAXIMUM RATINGS (Ta=25)
PARAMETER SYMBOL RATINGS UNIT
Supply Voltage(Low Impedance Source) VCC 30 V
Supply Voltage(ICC<30mA) VCC Self Limiting V
Output Current ( Peak ) IO(PEAK) ±1 A
Output Energy (capacity Load ) 5 μJ
Analog Inputs(pin 2,3) VI(ANA) -0.3 ~ +6.3 V
Error Amplifier Output Sink Current ISINK(EA) 10 mA
DIP-8 1.0 W
Power Dissipation( Ta25°C) SOP-8 PD 0.5 W
Derated at Ta>25°C PD 8 mW/°C
Junction Temperature TJ +150 °C
Storage Temperature TSTG -65 ~ +150 °C
Note Absolute maximum ratings are those values beyond which the device which the device could be permanently
damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied.
ELECTRICAL CHARACTERISTICS
(0°CTa70°C, VCC=15V, RT=10kΩ, CT=3.3nF, unless otherwise specified)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Reference Section
Output Voltage VREF T
J=25°C,IOUT=1mA 4.9 5 5.1 V
Line Regulation ΔVREF 12VIN25V 6 20 mV
Load Regulation ΔVREF 1IOUT=20mA 6 25 mV
Temperature Stability (Note 1) 0.2 0.4 mV/°C
Total Output Variation Line, Load, Temp(Note 1) 4.82 5.18 V
Output Noise Voltage Vosc 10Hzf10kHz,TJ=25°C (Note 1) 50 μV
Long Term Stability Ta=25°C,1000Hrs(Note 1) 5 25 mV
Output Short Circuit ISC -30 -100 -180 mA
Oscillator Section
Initial Accuracy f TJ=25°C 47 52 57 kHz
Voltage Stability Δf/ΔVcc 12VCC25V 0.2 1 %
Temperature Stability TminTaTmax(Note 1) 5 %
Amplitude Vosc Vpin 4 peak to peak 1.7 V
Error Amplifier Section
Input Voltage VI(EA) Vpin 1=2.5V 2.42 2.50 2.58 V
Input Bias Current II(BIAS) -0.3 -2 μA
AVOL
2 VOUT4V 60 90 dB
Unity Gain Bandwidth TJ=25°C (Note 1) 0.7 1 MHz
PSRR
I2VCC25V 60 70 dB
Output Sink Current IO(SINK) Vpin 2=2.7V,Vpin 1=1.1V 2 6 mA
Output Source Current IO(SOURCE) Vpin 2=2.3V,Vpin 1=5V -0.5 -0.8 mA
VOUT High VOH Vpin 2=2.3V, RL=15kΩ to GND 5 6 V
VOUT Low VOL Vpin 2=2.7V,Vpin 1=1.1V 0.7 1.1 V
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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ELECTRICAL CHARACTERISTICS(Cont.)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Current Sense section
Gain GV (Note 2,3) 2.85 3 3.15 V/V
Maximum Input signal VI(MAX) Vpin 1=5V( Note 2) 0.9 1 1.1 V
PSRR
12VCC25V 70 dB
Input Bias Current IBIAS -2 -10 μA
Delay to Output Vpin 3=0 to 2V 150 300 ns
Output Section IO(SINK)=20mA 0.1 0.4 V
Low VOL IO(SINK)=200mA 1.5 2.2 V
IO(SOURCE)=20mA 13 13.5 V
Output Level High VOH IO(SOURCE)=200mA 12 13.5 V
Rise Time tR T
J=25°C,CL=1nF(Note 1) 50 150 ns
Fall Time tF T
J=25°C,CL=1nF(Note 1) 50 150 ns
Under-Voltage Lockout Output Section
3842A 14.5 16 17.5 V
Start Threshold 3843A VTH(ST) 7.8 8.4 9 V
3842A 8.5 10 11.5 V
Min. Operating Voltage 3843A VOPR(MIN) After Turn On 7 7.6 8.2 V
PWM Section MAX D(MAX) 95 97 100 %
Duty Cycle Min D(MIN) 0 %
Total Standby Curren t
Start-up Current IST 0.12 0.3 mA
Operating Supply Current ICC(OPR) Vpin 2=Vpin 3=0V 11 17 mA
VCC Zener Voltage Vz I
CC=25mA 34 V
Note:1.These parameters, although guaranteed ,are not 100% tested in producti on.
2. Parameters measured at trip point of latch with Vpin 2=0.
3. Gain defined as:
4. Adjust VCC above the start threshold before setting at 15V.
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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OPEN-LOOP LABORATORY TEST FIXTURE
High peak current associated with capacity loads necessitate careful grounding techniques. Timing and bypass
capacitors should be connect ed close to pin 5 in single point GND. The transistor and 5kΩ potentio-meter are used
to sample the oscillator waveform and apply an adjustable Ramp to Pin 3.
UNDER-VOLTAGE LOCKOUT
During Under-Voltage Lockout, the output driver is biased to a high impedance state. Pin 6 should be shunt to
GND with a bleeder resistor to prevent activat ing the power switch with output leakage currents.
ERROR AMPLIFIER CONFIGURATION
2
1
0.5mA
2.5V
Zf
Zi
Error amplifier can source or sink up to 0.5mA
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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CURRENT SENS E CIRCUIT
5
3
1
2R
R1V
CRs
R
Is
Error Amplifier
Current Sense Comparator
Peak current (Is) determined by the formula: Ismax=10V/Rs.
A small RC filter be required to suppress switch transients.
SLOPE COMPENSATION
0.1 F
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converts requiring duty cycles over 50%.Note that capacitor C, forms a filter with R2 to suppress
the leading edge s witch spikes.
OSCILLATOR SECTION
Dead time vs. CT(RT>5kΩ) Timing Resistance vs. Frequency
td (μs)
RT (kΩ)
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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SHUTDOWN TECHNIQUES
8
3
330Ω
500Ω
1kΩ1
Shutdown To current
Sense resistor
Shutdown
Shutdown UTC UC3842A can be accomplished by two methods; either raise pin 3 above 1V or pull Pin 1 below a
voltage two diode drops above ground. Either method caused the output of PWM comparator to be high(refer to
block diagram).The PW M latch is reset dominant so th at the output will remain low until the ne xt clock cycle after the
shutdown condition at pins 1 and/or 3 is removed . In one example, an externally latched shut –down may be
accomplished by adding an SCR which be reset by cycling VCC below the lower UVLO threshold. At this point the
reference turns off allowing the SCR to reset.
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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TYPICAL CHARACTERISTICS
Output Saturation Characteristics Error Amplifier Open-Loop Frequency Response
Saturation Voltage (V)
Voltage Gain (dB)
PHASE (Degree)
-50 -25 0 25 50 75 100 125 150
4.96
4.97
4.98
4.99
5.00
5.01
5.02
Temperature ()
Vcc=15V
IOUT=1mA
-50 -25 0 25 50 75 100 125 150
250
300
350
400
450
500
550
Temperature ()
Vcc=9V
VREF Temperature Drift Istart Temperature Drift
UC3842A/3843A LINEAR INTEGRATED CIRCUIT
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UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
m alfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believ ed to be accurate
and reliable and m ay be changed without notice.