MCP2030DM-TPR - Microchip Technology

MCP2030

Device Features:

• Three input pins for analog input signals

• High input detection sensitivity (3 mVPP, typical)

• High modulation depth sensitivity (as low as 8%)

• Three output selections:

- Demodulated data

- Carrier clock

- RSSI

• Input carrier frequency: 125 kHz, typical

• Input data rate: 10 Kbps, maximum

• 8 internal Configuration registers

• Bidire ct ion al transponder com munic ati on

(LF talk back)

• Programmab le antenn a tuning capacita nce

(up to 63 pF, 1 pF/step)

• Programmable output enable filter

• Low standby current: 4 μA (with 3 channels

enabled), typical

• Low operating current: 13 μA (with 3 channels

enabled), typical

• Serial Peripheral Interface (SPI™) with external

devices

• Supports Battery Back-Up mode and batteryless

operation with external circuits

• Industri al and Ext end ed Temperatur e Range :

-40°C to +85°C (industrial)

Typical Applicat ions:

• Automotive industry applications:

- Passive Keyless Entry (PKE) transponder

- Remote door locks and gate openers

- Engine immobilizer

- LF initiator sensor for tire pressure monitoring

systems

• Security Industry applic ations:

- Long range access control transponder

- Parking lot entry transponder

- Hands-free apartment door access

- Asset control and management

Description:

The MCP2030 is a stand-alone Analog Front-End

(AFE) de vice fo r Low-Freque ncy (LF) sensing and bidi-

rectional communication applications. The device has

eight internal Configuration registers which are

readable and programmable, except the read-only

STATUS register, by an external device.

The device has three low-frequency input channels.

Each input channel can be individually enabled or dis-

abled. The device can dete ct an inpu t signa l with ampl i-

tude as low as ~1 mVPP and can demodulate an

amplitude-modulated input signal with as low as 8%

modula tion dept h. The devi ce can al so transmit data b y

clamping and unclamping the input LC antenna

voltage.

The device can output demodulated data, carrier clock

or RSSI current depending on the register setting. The

demodulated data and carrier clock outputs are avail-

able on the LF DAT A pin, while the RSSI output is avai l-

able on the RSSI pin. The RSSI current output is

linearly proportional to the input signal strength.

The device has programmable internal tuning capaci-

tors for each input channel. The user can program

these capacitors up to 63 pF, 1 pF per step. These

internal tuning capacitors can be used effectively for

fine-tuning of the external LC resonant circuit.

The device is optimized for very low current consump-

tion and has various battery-saving low-power modes

(Sleep, Standby, Active). The device can also be oper-

ated in Ba ttery Back -up and Batteryl ess modes using a

few external components.

This device is available in 14-pin PDIP, SOIC, and

TSSOP packages. This device is also used as the AFE

in the PIC16F639.

Package Types:

NCLCCOM

LCX

VSS

LFDATA/

VDD

LCZ

LCY

VSS

SCLK/ALERT

RSSINC

VDD

CCLK/SDIO

MCP2030

PDIP, SOIC, TSSOP

Three-Chan nel Analog Front-End Device

MCP2030

NOTES:

MCP2030

1.0 ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings(†)

Ambient temperature under bias...................-40°C to +125°C

Storage temperature ................... .. .. ..... .. .. .... -65°C to +150°C

Voltage on VDD with respect to VSS ............... -0.3V to +6.5V

Voltage on all ot her pins with

respe ct to V SS ...................................... -0.3V to (VDD + 0.3V)

Maximum current out of VSS pin ...................... ...........300 mA

Maximum current into VDD pin....................................250 mA

Maximum LC Input Voltage

(LCX, LCY, LCZ) loaded, with device............... .. .......10.0 VPP

Maximum LC Input Voltage

(LCX, LCY, LCZ) unloaded, without device.............700.0 VPP

Maximum Input Current (rms) into device

per LC Channel.............................................................10 mA

Human Body ESD rating... .... ...... .... ........... .... ....2000 (min.) V

Machine Model ESD rating ..................................200 (min.) V

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of th e dev ice at

those or any other conditions above those indicated in the

operation listings of this specification is not implied. Exposure

to maximum rating conditions for extended periods may affect

device reliability.

DC Characteristics

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C

LC Signal Input Sinusoidal 300 mVPP

Carrier Frequency 125 kHz

LCCOM connected to VSS

Parameters Sym. Min. Typ† Max. Units Conditions

Supply Voltage VDD 2.0 3.0 3.6 V

VDD Start Voltage to ensure internal

Power-on Reset signal VPOR ——1.8V

Modulation Transistor-on Resistance RM—50100ΩVDD = 3.0V

Active Current (detecting signal)

1 LC Input Channel Receiving Signal

3 LC Input Channel Receiving Signals

IACT —

—10

13 —

18 μA

μA

CS = VDD

Input = Continuous Wave (CW);

Amplitude = 300 mVPP.

All channels enabled.

Standby Current (wait to detect signal)

1 LC Input Channel Enabled

2 LC Input Channels Enabled

3 LC Input Channels Enabled

ISTDBY —

—

μA

CS = VDD; ALERT = VDD

Sleep Current ISLEEP —0.2 1μACS = VDD; AL E RT = VDD

Analog Input Leakage Current

LCX, LCY, LCZ

LCCOM

IAIL —

——

—± 1

± 1μA

μAVDD = 3.6V, VSS ≤ VIN ≤ 1V with respect to

ground. Internal tuning capacitors are switched

off, tested in Sleep mode.

Digital Input Low Voltage VIL VSS — 0.3 VDD V SCLK, SDI, CS

Digital Input High Voltage VIH 0.8 VDD —V

DD V SCLK, SDI, CS

Digital Input Leakage Current (No te 1)

SDI

SCLK, CS

IIL —

——

—± 1

± 1μA

μA

VDD = 3.6V

VSS ≤ VPIN ≤ VDD

VPIN ≤ VDD

Digital Output Low Voltage

ALERT, LFDATA/SDIO VOL ——V

SS + 0.4 V Analog Front-End section

IOL = 1.0 mA, VDD = 2.0V

Digital Output High Vo ltage

ALERT, L FDATA/SDIO VOH VDD - 0.5 — — V IOH = -400 μA, VDD = 2.0V

Digital Input Pull-Up Resistor

CS, SCLK RPU 50 200 350 kΩVDD = 3.6V

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, +25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: Negative current is defined as current sourc e d by the pin.

MCP2030

AC Characteristics

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Supply Voltage 2.0V ≤ VDD ≤ 3.6V

Operating temperature -40°C ≤ TA ≤ +85°C

LCCOM connected to VSS

LC Signal Input Sinusoidal 300 mVPP

Carrier Frequency 125 kHz

LCCOM connected to VSS

Parameters Sym. Min. Typ† Max. Units Conditions

Input Sensitivity VSENSE 13.0 6mV

PP VDD = 3.0V

Output enable filter disabled

AGCSIG = 0; MODMIN = 00

(33% modulation depth setting)

Input = Continu ous Wave (CW)

Output = Logic level transition from

low-to-high at sensitivity level for CW input.

Coil de-Q’ing Voltage -

RF Limit er (RFLM) must be active VDE_Q 3— 5 VV

DD = 3.0V, Force IIN = 5 μA (worst case)

RF Limit er Turn-on Res ista nce

(LCX, LCY, LCZ) RFLM — 300 700 ΩVDD = 2.0V, VIN = 8 VDC

Sensitivity Reduction SADJ —

—0

-30 —

—dB

VDD = 3.0V

No sensitivity reduction selected

Max. reduction selected

Monotonic increment in attenuation value

from setting = 0000 to 1111 by design

Minimum Modulation Depth

60% setting

33% setting

14% setting

VIN_MOD —

—

VDD = 3.0V

See Section 5.21 “Minimum Modulation

Depth Requirement for Input Signal”.

See Modulation Depth Definition in

Figure 5-5.

Carrier frequency FCARRIER —125 — kHz

Input modulation frequency FMOD — — 10 kHz Input data rate with NR Z data format.

VDD = 3.0V

Minimum modulation depth setting = 33%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 100%

LCX Tuning Capacitor CTUNX —

—

VDD = 3.0V,

Config. Reg. 1, bits <6:1> Setting = 000000

63 pF ±30%

Config. Reg. 1, bits <6:1> Setting = 111111

63 steps, approx. 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

LCY Tuning Capacitor CTUNY —

—

VDD = 3.0V,

Config. Reg. 2, bits <6:1> Setting = 000000

63 pF ±30%

Config. Reg. 2, bits <6:1> Setting = 111111

63 steps, approx. 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

LCZ Tuning Capacitor CTUNZ —

—

VDD = 3.0V,

Config. Reg. 3, bits<6:1> Setting = 000000

63 pF ±30%

Config. Reg. 3, bits<6:1> Setting = 111111

63 steps, approx. 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

Q of Internal Tuning Capacitors Q_C 50 * — —

Demodulator Charge Time

(delay time of demodulated output to rise) TDR —50 — μsV

DD = 3.0V

Minimum modulation depth setting = 33%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 100%

* Parameter is characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).

2: Required output enable filter low time mu st account for input path analog delays (= TOEL + TDR - TDF).

MCP2030

Demodulator Discharge Time (delay time

of demodul ate d outp ut to fall) TDF —50 — μsV

DD = 3.0V

MOD depth setting = 33%

Input conditions:

Amplitude = 300 mVPP

Modulation depth = 100%

Rise time of LFD ATA TRLFDATA —0.5 — μsV

DD = 3.0V. Time is measured from 10% to

90% of amplitude

Fall time of LFDATA TFLFDATA —0.5 — μsV

DD = 3.0V

Time is measured from 10% to 90% of

amplitude

AGC stabilization time

(TAGC + TPAGC)TSTAB 4—— ms

AGC initialization time TAGC —3.5 — ms

High time after AGC initialization time TPAGC —62.5 — μs

Gap time after AGC stabilization time TGAP 200 — — μs

Time element of pulse TE100 — — μs Minimum pulse width

Time from exiting Sleep or POR to being

ready to receive signal TRDY ——50*ms

Minimum time AGC level must be held

after receiving AGC Preserve command TPRES 5*— — ms AGC level must not change more than 10%

during TPRES.

Internal RC oscillator frequency FOSC 27 32 35.5 kHz Internal clock trimmed at 32 kHz during test

Inactivity timer time- out TINACT 13.5 16 17.75 ms 512 cycles of RC oscillator @ FOSC

Alarm timer time-out TALARM 27 32 35.5 ms 1024 cycles of RC oscillator @ FOSC

LC Pin Input Resistance for

LCX, LCY, LCZ pins RIN — 800* — kΩLCCOM grounded, VDD = 3V,

FCARRIER = 125 kHz.

LC P in Input Parasitic Capac itance for

LCX, LCY, LCZ pins CIN —24* — pF

LCCOM grounded, VDD = 3V,

FCARRIER = 125 kHz.

Minimu m output enable filter high time

OEH (Bits Config0<8:7>)

01 = 1ms

10 = 2ms

11 = 4ms

00 = Filter Disabled

TOEH

32 (~1 ms)

64 (~2 ms)

128 (~4 ms)

—

clock

count

RC oscillator = FOSC (see FOSC specification

for variations).

Viewed from the pin input:

(Note 1)

Minimu m output enable filter low time

OEL (Bits Config0<6:5>)

00 = 1ms

01 = 1ms

10 = 2ms

11 = 4ms

TOEL

32 (~1 ms)

64 (~2 ms)

128 (~4 ms)

—

clock

count

RC oscillator = FOSC

Viewed from the pin input:

(Note 2)

Maximum output enable filter period

OEH OEL TOEH TOEL

01 00 = 1 ms 1 ms (Filter 1)

01 01 = 1 ms 1 ms (Filter 1)

01 10 = 1 ms 2 ms (Filter 2)

01 11 = 1 ms 4 ms (Filter 3)

TOET

—

96 (~3 ms)

128 (~4 ms)

192 (~6 ms)

clock

count

RC oscillator = FOSC

10 00 = 2 ms 1 ms (Filter 4)

10 01 = 2 ms 1 ms (Filter 4)

10 10 = 2 ms 2 ms (Filter 5)

10 11 = 2 ms 4 ms (Filter 6)

—

128 (~4 ms)

160 (~5 ms)

250 (~8 ms)

11 00 = 4 ms 1 ms (Filter 7)

11 01 = 4 ms 1 ms (Filter 7)

11 10 = 4 ms 2 ms (Filter 8)

11 11 = 4 ms 4 ms (Filter 9)

—

192 (~6 ms)

256 (~8 ms)

320 (~10 ms)

00 XX = Filter Disabled — — — LFDAT A output appears as long as input

signal level is greater than VSENSE.

AC Characteristics (Continued)

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Supply Voltage 2.0V ≤ VDD ≤ 3.6V

Operating temperature -40°C ≤ TA ≤ +85°C

LCCOM connected to VSS

LC Signal Input Sinusoidal 300 mVPP

Carrier Frequency 125 kHz

LCCOM connected to VSS

Parameters Sym. Min. Typ† Max. Units Conditions

* Parameter is characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).

2: Required output enable filter low time mu st account for input path analog delays (= TOEL + TDR - TDF).

MCP2030

RSSI current output IRSSI —

—

0.65

100

20.3

—

μA

VIN = 37 mVPP

VIN = 370 mVPP

VDD = 3.0V, VIN = 0 to 4 VPP

Linearly increases with input signal ampli-

tude.

Tested at VIN = 37 mVPP, 100 m VPP, and

370 mVPP at +25ºC.

RSSI current linearity ILRRSSI -15 — 15 % Tested at room temperature only (see

Equation 5-1 and Figure 5-7 for test method).

AC Characteristics (Continued)

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Supply Voltage 2.0V ≤ VDD ≤ 3.6V

Operating temperature -40°C ≤ TA ≤ +85°C

LCCOM connected to VSS

LC Signal Input Sinusoidal 300 mVPP

Carrier Frequency 125 kHz

LCCOM connected to VSS

Parameters Sym. Min. Typ† Max. Units Conditions

* Parameter is characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1: Required output enable filter high time must account for input path analog delays (= TOEH - TDR + TDF).

2: Required output enable filter low time mu st account for input path analog delays (= TOEL + TDR - TDF).

SPI Ti ming

Electrical Specifications: Standard Operating Conditions (unless otherwise stated)

Supply Voltage 2.0V ≤ VDD ≤ 3.6V

Operating temperature -40°C ≤ TA ≤ +85°C

LC Signal Input Sinusoidal 300 mVPP

Carrier Frequency 125 kHz

LCCOM connected to VSS

Parameters Sym. Min. Typ† Max. Units Conditions

SCLK Frequency FSCLK —— 3MHz

CS fall to first SCLK edge setup time TCSSC 100 — — ns

SDI setup time TSU 30 — — ns

SDI hold time THD 50 — — ns

SCLK high time THI 150 — — ns

SCLK low time TLO 150 — — ns

SDO setup time TDO ——150ns

SCLK last edge to CS rise setup time TSCCS 100 — — ns

CS high time TCSH 500 — — ns

CS rise to SCLK edge setup time TCS1 50 — — ns

SCLK edge to CS fall setup time TCS0 50 — — ns SCLK edge when CS is high

Rise time of SPI data

(SPI Read command) TRSPI —10—nsV

DD = 3.0V. Time is measured from 10% to

90% of ampli tude

Fall time of SPI data

(SPI Read command) TFSPI —10—nsV

DD = 3.0V. Time is measured from 90% to

10% of ampli tude

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

MCP2030

2.0 TYPICAL PERFORMANCE CURVES

FIGURE 2-1: Typica l Sta ndby Curre nt. FIGURE 2-2: Typical Active Current.

Note: The g r ap hs and t ables provid ed fol lowi ng this note are a st a t is tical summary b as ed on a l im ite d n um ber of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Standby Current (3 Channels Enabled)

2 V 3 V 3.6 V

VDD (V)

Current Draw (μA)

Standby Current (2 Channels Enabled)

0.5

1.5

2.5

3.5

2 V 3 V 3.6 V

VDD (V)

Current Draw (μA)

Stand by Current ( 1 Channel E nabled)

0.5

1.5

2.5

2 V 3 V 3.6 V

VDD (V)

Current Draw (μA)

+85°C

+25°C

-40°C

+85°C

+25°C

-40°C

+85°C

+25°C

-40°C

Active Current (3 Channels E nab led)

2 V 3 V 3.6 V

VDD (V)

Current Draw (μA)

Active Curren t (1 Channel Enabled)

2 V 3 V 3.6 V

VDD (V)

Current Draw (μA)

Active Current (2 Channels E nab led)

2 V 3 V 3.6 V

VDD (V)

Current Draw (μA)

+85°C

+25°C

-40°C

+85°C

+25°C

-40°C

+85°C

+25°C

-40°C

MCP2030

FIGURE 2-3: Oscillator Frequency vs.

Temperature, VDD = 3.6V and 2.0V.

FIGURE 2-4: Oscillator Frequency

Histograms vs. Tempera ture, VDD = 2V.

FIGURE 2-5: Oscillator Frequency

Histograms vs. Temperature at VDD = 3V.

FIGURE 2-6: De-Q’ed Voltage vs.

Unloaded Coil Voltage.

FIGURE 2-7: Modulation Transistor-on

Resistance (+25°C).

FIGURE 2-8: Channel Sensitivity vs.

Bandwidth.

-50 -25 0 25 50 75 100 125

Temperature (°C)

Oscillator Frequency (kHz.)

Osc. Freq. @ VDD = 3.6V

Osc. Freq. @ VDD = 2.0V

0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

30.0%

35.0%

40.0%

45.0%

50.0%

Oscillator Frequency (kHz.)

Percent age of Occur e nce s (%)

-40C

25C

85C

VDD = 2.0V

0.0%

5.0%

10.0%

15.0%

20.0%

25.0%

30.0%

35.0%

40.0%

45.0%

50.0%

Oscillator Frequency (kHz.)

Percentage of Occurences (%)

-40C

25C

85C

VDD = 3.6V

0 200 400 600 800

Unloaded Coil Voltage (VPP)

De-Q'e d (Loaded) Coil Volt age

(VPP)

0246

VDD (V)

Ohms

Ch. X

Ch. Y

Ch. Z

0 200 400 600

Fre que nc y (k Hz )

MCP2030

FIGURE 2-9: T ypical RSSI Output Current

vs. Input Signal Strength.

FIGURE 2-10: Typical Tuned Capacitance

Value vs. Configuration Register Bit Setting

(VDD = 3V, Temperature = +25°C.

FIGURE 2-11: Typical Tuned Capacitance

Value vs. Configuration Register Bit Setting

(VDD = 3V,Temperature = -40°C.

FIGURE 2-12: Typical Tuned Capacitance

Value vs. Configuration Register Bit Setting

(VDD = 3V,Temperature = +85°C.

100

120

0.5

1.5

2.5

3.5

4.5

5.5

Input Voltage (V)

RSSI (µA)

-40°C

+85°C +25°C

0 20406080

Bit Setting (Steps)

Capacitance (pF)

Ch. X

Ch. Y

Ch. Z

0 20406080

Bit Setting (steps)

Capacita nce (pF)

Ch. X

Ch. Y

Ch. Z

0 20406080

Bit Setting (Steps)

Capacit ance (pF )

Ch. X

Ch. Y

Ch. Z

MCP2030

FIGURE 2-13: Examples of RSSI Output

Current Variations Between Channel to Channel

and Device to Device at Room Temperature.

FIGURE 2-14: Example of Typical TDR

Changes over Temperatur e.

Input Signal Condition: Amplitude = 300 mVPP,

Modulation Depth = 100 %.

FIGURE 2-15: Example of Typical TDF

Changes over Temperatur e.

Input Signal Condition: Amplitude = 300 mVPP,

Modulation Depth = 100 %.

02468

Input Voltage (V)

RSSI Current (μA)

Ch-X

Ch-Y

Ch-Z

02468

Input Voltag e (V)

RSSI Current (μA)

Ch-X

Ch-Y

Ch-Z

Device (a)

Device (b)

Device (c)

Note: Equal amplitude is applied to each channel.

02468

Input Voltag e (V)

Current (μA)

Ch-X

Ch-Y

Ch-Z

100

85C 25C -20C -40C

Temperature (°C)

TDR (µs)

14%

33%

60%

85C 25C -20C -40C

Temperature (°C)

TDF (µs )

14%

33%

60%

MCP2030

2.1 Performance Plots

FIGURE 2-16: Input Sensitivity Example.

(a) Sensitivity = 1.06 mVPP

(b) Sensitivity = 3 mVPP

Demodulated output

Input signal

Demodulated output

Input signal

MCP2030

FIGURE 2-17: Typical AGC Initialization Time at Room Temperature (VDD = 3V).

Note: Ch2 is the input and Ch1 is the output (demodulated data appears after AGC Initialization time (TAGC)).

Output Enable Filter is disabled.

MCP2030

FIGURE 2-18: ALERT Output Example: With No Parity Error and no 32 ms Alarm Timer Time-out.

Note: Ch3 is the input with correct Output Enable Filter timing.

Ch1 is the demodulated LFDATA output.

Ch2 is the ALERT pin output. It shows that the ALE RT output pin maintains logic high if the input signal

meets the programmed filter timing requirement.

MCP2030

FIGURE 2-19: ALERT Output Example: With 32 ms Alarm Timer Timed out.

Note: The 32 ms Alarm Timer is enabled only if the Output Enable Filter is enabled.

Ch3 is the input s i gnal with incorrect Output Enable Filter timing.

Ch1 is the demodulated LFDATA output. No output since the input filter is not matched.

Ch2 is the ALERT output.

The output shows that the logic level changes after 32 ms from the AGC initialization time (TAGC) if the input

signal does not meet the programmed filter timing requirement.

MCP2030

FIGURE 2-20: Examples of Soft Inactivity Timer Timed out: This output is available only if the Output

Enable Filter is disabled.

(b) Input (Ch 2):

Input has no

(a) Output (Ch 1):

Device repeats

Soft Reset after

16 ms inactivity

timer has timed out

Note: Ch 2 is the input without modulation (i.e., noise)

Ch 1 is the output at the LFDATA pin due to the 16 ms Soft Inactivity Timer timed out. Note the 3.5 ms AGC

initia lization time after the Soft Reset.

The cases shown above apply when the Output Filter is disabled.

modulation

MCP2030

FIGURE 2-21: Examples of Clamp-On and Clamp-Off Commands and Changes in Coil Voltage.

Coil Voltage

Clock Pulses

Clamp On

Coil Voltage

Clock Pulses

Clamp Off

Command

LCX

SCLK

SDI

LCX

SCLK

SDI

MCP2030

FIGURE 2-22: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal =

77%, Minimum Modulation Depth (MODMIN) Setting = 60%.

FIGURE 2-23: Example of Minimum Modulation Depth Setting: Modulation Depth of Input

Signal = 56%, Minimum Modulation Depth (MODMIN) Setting = 60%.

Demodulated output

Input signal with 77%

modulation depth

Demodulated output

Input signal with 56%

modulation depth

Note: There is no demodulated output since the modulation depth of the input signal is lower than the minimum

modulation depth setting. The device will have demodulated output if the M inimum Modulation Depth option

is set to 8%, 14%, or 33%.

MCP2030

FIGURE 2-24: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal =

42%, Minimum Modulation Depth (MODMIN) Setting = 33%.

FIGURE 2-25: Example of Minimum Modulation Depth Setting: Modulation Depth of Input Signal =

14%, Minimum Modulation Depth (MODMIN) Setting = 14%.

Demodulated output

Input signal with 42%

modulation depth

Demodulated output

Input signal with 14%

modulation depth

MCP2030

FIGURE 2-26: Examples of Output Enable Filters 1 through 3 (Wake-up Filters) and Demodulated

Outputs.

Filter 1

Output Enable

Filter T iming of

Input Signal

Configuration

Bit Se ttings

OEH OEL

TOEH = 1 ms

TOEL = 1 ms

TOET = 3 ms

Filter 2

Output Enable

Filter Timing of

Input Signal

Configuration

Bit Settings

OEH OEL

TOEH = 1 ms

TOEL = 2 ms

TOET = 4 ms 01 10

Filter 3

Output Enable

Filter Timing of

Input Signal

Configuration Bit

Settings

OEH OEL

TOEH = 1 ms

TOEL = 4 ms

TOET = 6 ms 01 11

MCP2030

FIGURE 2-27: Examples of Output Enable Filters 4 through 6 (Wake-up Filters) and Demodulated

Outputs.

Filter 4

Output Enable

Filter Timing of

Input Signal

Configuration Bit

Settings

OEH OEL

TOEH = 2 ms

TOEL = 1 ms

TOET = 4 ms

Filter 5

Output Enable

Filter Timing of

Input Signal

Configuration Bit

Settings

OEH OEL

TOEH = 2 ms

TOEL = 2 ms

TOET = 5 ms 10 10

Filter 6

Output Enable

Filter Timing of

Input Signal

Configuration

Bit Settings

OEH OEL

TOEH = 2 ms

TOEL = 4 ms

TOET = 8 ms 10 11

MCP2030

FIGURE 2-28: Examples of Output Enable Filters 7 through 9 (Wake-up Filters) and Demodulated

Outputs.

Filter 7

Output Enable

Filter Timing of

Input Signal

Configuration Bit

Settings

OEH OEL

TOEH = 4 ms

TOEL = 1 ms

TOET = 6 ms

Filter 8

Output Enable

Filter Timing of

Input Signal

Configuration

Bit Settings

OEH OEL

TOEH = 4 ms

TOEL = 2 ms

TOET = 8 ms 11 10

Filter 9

Output Enable

Filter Timing of

Input Signal

Configuration Bit

Settings

OEH OEL

TOEH = 4 ms

TOEL = 4 ms

TOET = 10 ms 11 11

MCP2030

FIGURE 2-29: Input Signal and Demodulated Output When the Output Enable Filter is Disabled.

FIGURE 2-30: Input Signal and Demodulator Output When Output Enable Filter is Enabled and Input

Meets Filter Timing Requirements.

Input Signal

LFDATA

Note: Demodulated output is available immediately after AGC initialization.

Output

Input Signal

LFDATA

Note: Demodulated output is available only if the incoming signal meets the enable f ilter timing criteria that is defined in th

Configuration Register 0 (Register 5-1). If the criteria is met, the output is available after the low timing (TOEL) of th

Enable Filter.

Output

MCP2030

FIGURE 2-31: No Demodulator Output When Output Enable Filter is Enabled But Input Does Not

Meet Filter Timing Requirements.

Input Signal

No LFDATA

Output

MCP2030

FIGURE 2-32: Carrier Clock Output Examples.

(a) Carrie r Clock Out put with Carrier/1 Option

Carrier Clock Output

Carrier Input

(b) Carrier Clock Out put with Carrier/4 Opt ion

Carrier Input

Carrier Clock Output

MCP2030

3.0 PIN DESCRIPTIONS

3.1 Supply Volt age (V DD, VSS)

The VDD pin i s the power supply pin for the analog and

digital circuitry within the MCP2030. This pin requires

an approp riate bypass ca p ac ito r of 0 . 1 µF. The voltag e

on this pin shou ld be maint ained in the 2.0V -3.6V range

for specified operation.

The VSS pin is the ground pin and the current return

path for both analog and digital circuitry of the

MCP2030. If an analog ground plane is available, it is

recommended that this device be tied to the analog

ground plane of the PCB.

3.2 Chip Select (CS)

The CS pin needs to stay high when the device is

receiving input signals. Leaving the CS pin low will

place the device in the SPI Programming mode.

The CS pin is an ope n colle ct or outpu t. This p in has an

internal pull-up resi stor to ensure that no spurious SPI

communication occurs between power-up and pin

configuration of the MCU.

3.3 SPI Clock Input (SCLK/ALERT)

This pi n bec omes the SPI clo ck inpu t (SCLK) when C S

is low, and becomes the ALERT output when CS is

high.

The ALER T pin is an open collector output. This pin has

an internal pull-up resistor to ensure that no spurious

SPI communication occurs between power-up and pin

configuration of the MCU.

3.4 Received Signal Strength

Indicator (RSSI)

This pin becomes the Received Signal S trength Indicator

(RSSI ) ou tput curre nt si nk wh en th e RSSI outp ut op tion

is sele ct ed.

TABLE 3-1: PIN FUNCTION TABLES

Pin No. Symbol I/O/P Function

SS P Ground Pin.

2CSIChip Select Digital Input Pin.

3 SCLK/ALERT I/O Cl ock input for the modified 3-wire SPI interface.

ALERT output: This pin goes low if there is a parity error in the

Configuration register or the 32 ms alarm timer is timed out.

4 RSSI O Received Si gn al Strength In di ca to r (RSSI) current output.

5 NC N/A No Connect.

6 L FDATA/CCLK/SDIO I/O Demodulated data output.

Carrier clock outpu t.

Serial input or output data for the modified 3-wire SPI interface.

DD P Positive Supply Voltage Pin.

9 LCZ I Input pin for external LC antennas.

10 LCY I Input pin for external LC antennas.

11 LCX I Input pin for external LC antennas.

12 NC N/A No Connect.

13 LCCOM I Common reference input for the external LC antennas.

14 VSS P Ground Pin.

Type Identification: I = Input; O = Output; P = Power

MCP2030

3.5 Demodulated Dat a Output (LFDATA)

Carrier Clock Output (CCLK)

SPI Data I/O (SDIO)

When the CS pin is high, this pin is an output pin for

demodu lated d at a or carrier clock depen ding o n outp ut

type selection. When carrier clock output (CCLK) is

selected, the LFDATA output is a square pulse of the

input carr ier c lock and is availa ble as s oon as the AGC

stabilization time (TSTAB) is completed.

When the CS pin is low, this pin becom es the SPI da t a

input and output (SDIO).

3.6 LC Input (LCX, LCY, LCZ)

These pins are the input pins for the external LC

resonant antenna circuits. The antenna circuits are

connected between the LC pin and the LCCOM pin.

3.7 LC Common Reference (LCCOM)

This pin is the common reference input pin for the

external LC resonant circuit.

MCP2030

4.0 APPLICATION INFORMATION

The MCP2030 is a stand-alone 3-channel analog

front-end device for low frequency (LF) sensing and

bidirectional transponder applications. By connecting

three orthogonally placed LC resonant antennas to

the LC input pins, it can detect signals from all

directions (x, y and z).

The device draws more current when all channels are

enabled as compared to a single channel; therefore, it

is recommended to disable any unused channels by

setting Configuration Register 0 (Register 5-1).

The device’s high input sensitivity (as low as 1 mVPP)

and ability to detect weakly modulated (as low as 8%)

input signals with its low power feature set, makes the

device suitable for various applications such as a low-

cost hands-free Passive Keyless Entry (PKE)

transponder, an LF Initiator sensor for Tire Pressure

Monitoring Systems (TPMS) and long-range access

control applications in the automotive and security

industries.

4.1 Battery Back-up and Batteryless

Operation

The device supports both battery back-up and

batteryless operation by the addition of external

components, allowing the device to be partially or

completely powered from the field.

Figu re 4- 1 shows an example of the ext ernal circuit fo r

the battery back-up.

FIGURE 4-1: External Circuit Example for LF Field Powering and Battery Back-up Mode.

Note: Voltage on LCCOM combined with coil

input voltage must not exceed the maxi-

mum LC input voltage.

LCX

LCY

LCZ

VBAT

DBLOCK CPOOL

DFLAT1

RLIM

LCCOM

CCOM

Air Coil

DFLAT2

VDD

RCOM

DLIM LX

Legend: CCOM = LCCOM charging capacitor.

CPOOL = Pool capacitor (or battery back-up capacitor), charges in field and powers device.

DBLOCK = Battery protection from reverse charge.

Schottky for low forward bias drop.

DFLAT = Field rectifier diodes.

DLIM = Voltage limiting diode, may be required to limit VDD voltage when in strong fields.

RCOM = LCCOM discharge path.

RLIM = Current limiting resistor, required for air coil in strong fields.

MCP2030

4.2 Application Examples

Figure 4-2 shows an example of an external circuit for

a bidirec tio nal co mmuni catio n transp onder ap plica tio n.

Each LC input pin is connected to an external LC

resonant circuit. To achieve the best performance, the

resonant frequency of the LC circuit needs to be

matched to the detecting carrier frequency of interest.

The resonant frequency is given by the following

equation:

In t ypical 125 kHz appli cations, th e L value is a few mH,

and the C value is a few hundred pF, for example,

L = 4.9 mH, and C = 331 pF.

The reso nant f requ ency can b e fine -tuned by pro gram-

ming the internal tuning capacitors.

The output of the MCP2030 is fed into the external

MCU. The external MCU can send dat a by clampi ng on

and clamping off the MCP2030 coil voltages using an

SPI command, or via a UHF transmitter.

The RSSI output of the MCP2030 can be digitized by

the MCU firmware. Users can also consider using a

MCU that has an internal analog-to-digital converter

(ADC) such as the PIC16F684 or a stand-alone ADC

device.

Figu re 4 - 3 s h ows a n ex am pl e of a h and s- f re e P as si ve

Keyless Entry (PKE) system. The base station unit

transmits an LF command. The MCP2030 detects the

base station command and feeds the detected output

to the external MCU (PIC16F636). If the command is

correct, the MCU responds via an external UHF

transmitter or by using the LF talk-back modulators of

the MCP2030 device.

Figure 4-4 shows an example when the device is used

for a tire pressure monitoring sensor application. The

device detects the LF Initiator commands and transmit s

the tire pressure data to the base station via an external

UHF transmitter.

FIGURE 4-2: Example of External Circuits for Bidirectional Communication Transponder Applications.

fo1

2πLC

------------------

LCCOM

LCX

VSS

LFDATA/CCLK/SDIO

VDD

LCZ

LCY

VSS

SCLK/ALERT

RSSI

VDD

PIC16F636/684 To ADC

+3V

air-core

coil ferrite-core

coil

ferrite-core coil

MCP2030

+3V

RF Circuitry

(UHF TX)

315/434 MHz

SW1

SW2

SW3

SW4

CLCL

MCP2030

FIGURE 4-3: Example of Bidirectional Hand-free Passive Keyless Entry (PKE) System.

FIGURE 4-4: Example of Tire Pressure Monitoring Sensor Applications.

LED

UHF

Transmitter

LED

UHF

Receiver

Transmitter/

Receiver

Microcontroller

(MCU)

LF Command

(125kHz)

Response

(125kHz)

Response

(UHF)

Encrypted

Codes

Base Station PKE Transponder

Ant. X

Ant. Y

Ant. Z

MCU

(PIC16F636)

MCP2030

(3D Stand Alone

Analog Front-End)

RF Receiver

MCU

LF Initiator

RF Transmitter

MCP2030

Tire

Pressure

Sensor

UHF response with

tire pressure data

125 kHz Initiator

command

Note 1: The LF initiator sends LF commands to request the tire pressure data.

2: The MCP2030 picks up the LF commands and the MCU transmits the tire pressure data

via an external UHF transmitter.

MCU

MCP2030

NOTES:

© 2005 Microchip Technology Inc. DS21981A-page 31
MCP2030
5.0 FUNCTIONAL DESCRIPTION 
AND THEORY OF DEVICE 
OPERATION
The MCP2030 contains three analog input channels for
signal detection and LF talk-back. This section
provides the function description of the device.
Each analog input channel has internal tuning
capacitors, sensitivity control circuits, an input signal
strength limiter and an LF talk-back modulation
transistor. An Automatic Gain Control (AGC) loop is
used for all three input channel gains. The output of
each channel is OR’d and fed into a demodulator. The
digital output is passed to the LFDATA pin. Figure 5-1
shows the block diagram of the device and Figure 5-2
shows the input signal path.
There are  a tot al of  eig ht Confi guratio n regis ters. S ix  of
them are used for device operation options, one for
column parity bits and one for status indication of
device  operatio n. Each regi ster has 9  bits in cluding on e
row parity bit. These registers are readable and
writable by SPI commands except for the STATUS
register, which is read-only.
The device’s features are dynamically controllable by
programmi ng the Configuration registers.
5.1 RF Limiter
The RF Limiter limits LC pin input voltage by de-Q’ing
the external LC resonant antenna circuit. The limiter
begins de-Q’ing the external LC antenna when the
input voltage exceeds VDE_Q, progressively de-Q’ing
harder to reduce the antenna input voltage.
The signal levels from all 3 channels are combined
such that the limiter attenuates all 3 channels
uniformly, in respect to the channel with the strongest
signal.
5.2 Modulation Circuit
The modulation circuit consists of a modulation
transistor (FET), internal tuning cap acitors and external
LC antenna components. The modulation transistor
and the internal tuning capacitors are connected
between the LC input pin and LCCOM pin. Each LC
input has its own modulation transistor.
When the modulation transistor turns on, its low Turn-
on Resistance (RM) clamps the induced LC antenna
voltage. The coil voltage is minimized when the
modulation transistor turns-on and maximized when
the modulation transistor turns-off. The modulation
transistor’s low turn-on resistance (RM) result s in a high
modulation depth.  
The LF talk-back is achieved by turning on and off the
modulati on transistor.
The modulation data comes from the external micro-
controller section via the digital SPI as “Clamp On”,
“Clamp Off” commands. Only those inputs that are
enabled will execute the Clamp command. A basic
block diagram of the modulation circuit is shown in
Figure 5-1 and Figure 5-2.
The modulation FET is also shorted momentarily after
Soft Reset and Inactivity time r time-out.
5.3 Tuning Capacitor
Each channel has internal tuning capacitors for external
antenna tuning. The capacitor values are programmed
by the C onfiguration registers up to 63 pF , 1 pF per step.
5.4 Variable Attenuator
The variable attenuator is used to attenuate, via  AGC
control,  the input signal voltage to avoid saturating the
amplifiers and demodulators.
5.5 Sensitivity Contr ol
The sensitivity of each channel can  be reduced by  the
channel’s Configuration register sensitivity setting.
This is used to desensitize the channel from optimum.
5.6 AGC Control
The AGC controls the variable attenuator to limit the
internal signal voltage to avoid saturation of internal
amplifiers and demodulators (Refer to Section 5.4
“Variable Attenua tor”).
The signal levels from all 3 channels are combined
such that the AGC attenuates all 3 channels uniformly
in respect to the channel with the strongest signal.
Note: The user can control the tuning capaci-
tor by programming the Configuration
registers. See Register 5-2 through
Registe r 5-4 for details.
Note: The variable attenuator function is
accomplished by the device itself. The
user cannot control its function.
Note: The user can desensitize the channel
sensitivity by programming the
Configuration registers. See Register 5-5
and Register 5-6 for details.
Note: The AG C contro l func tion is  acco mplis hed
by the device itself. The user cannot
control its function.

MCP2030

5.7 Fixed Gain Amplifiers 1 and 2

FGA1 and FGA2 provides a maximum two-stage gain

of 40 dB.

5.8 Auto-Channel Selection

The auto-channel selection feature is enabled if the

Auto-Channel Select bit AUTOCHSEL<8> in Configu-

ration Register 5 (Register 5-6) is set, and disabled if

the bit is cleared. When this feature is active (i.e.,

AUTOCHSE <8> = 1), the control circuit checks the

demodulator output of each input channel immediately

after the AGC settling ti me (TSTAB). If the output is hig h,

it allows this channel to pass data, otherwise it is

blocked.

The status of this operation is monitored by STATUS

the current status of the channel selection activity, and

automatically updates for every Soft Reset period. The

auto-channel selection function resets after each Soft

Reset (or after Inactivity timer t ime-o ut). Ther efor e, the

blocked channels are re-enabled after So ft Reset.

This feature can make the output signal cleaner by

blocking any channel that was not high at the end of

TAGC. This function works only for demodulated data

output, and is not applied for carrier clock or RSSI

output.

5.9 Carrier Clock Detector

The Carrier Clock Detector senses the input carrier

cycles. The output of the detector switches digitally at

the signal carrier frequency. Carrier clock output is

ava ilable wh en the outp ut is sele cted by th e DATOUT

bit in Con figuration R egister 1 (Register 5-2).

5.10 Demodulator

The Demodulator consists of a full-wave rectifier, low

pass filter, peak detector and Data Slicer that detects

the envelope of the input signal.

5.11 Data Sli cer

The Data Slicer consists of a reference generator and

comparator. The Data Slicer compares the input with

the reference voltage. The reference voltage comes

from the minimum modulation depth requirement

setting and input peak voltage. The data from all 3

channels are OR’d together and sent to the output

enable filter.

5.12 Output Enable Filter

The Output Enable Filter enables the LFDATA output

once th e incom ing sign al meet s th e wake-up sequenc e

requirements (see Section 5.15 “Configurable

Output Enable Filter”).

5.13 Received Signal Strength

Indicator (RSSI)

The RSSI provides a current which is proportional to

the input signal amplitude (see Section 5.30.3

“Received Signal Strength Indicator (RSSI)

Output”).

5.14 Analog Front-End Timers

The device has an internal 32 kHz RC oscillator. The

oscillator is used in several timers:

• Inactivity timer

• Alarm timer

•Pulse width timer

• Per iod timer

• AGC settling timer

5.14.1 RC OSCILLATOR

The RC oscillator generates a 32 kHz internal cl ock.

Note: The user cannot control the gain of these

two amplifiers.

MCP2030

5.14.2 INACTIVITY TIMER

The Inactivity Ti mer is used to automatically return the

device to Standby m ode, i f ther e is n o input signa l. The

time-ou t period is approximately 16 ms (TINACT), based

on the 32 kHz internal clock.

The purpose of the Inactivity Timer is to minimize

current draw by automatically returning to the lower

current Standby mode, if there is no input signal for

approximately 16 ms.

The timer is reset when:

• An amplitude change in LF input signal, either

high-to-low or low-to-high

•CS

pin is low (any SPI command)

• Timer-related Soft Reset

The timer starts after AGC initialization time (TAGC).

The timer causes a Soft Reset when:

• A previously received input signal does not

change either high-to-low or low-to-high for

TINACT

The Soft Reset returns the device to Standby mode

where most of the analog circuits, such as the AGC,

demodulator and RC oscillator , are powered down. This

return s th e device to the lower Stand b y Cur r en t mo de .

5.14.3 ALARM TIMER

The Alarm Timer is used to notify the external MCU that

the d evi ce is rece ivin g an i nput sign al th at d oes not p ass

the output enable filter requirement. The time-out p eriod

is approximately 32 ms (TALARM) in the presence of

continuing noise.

The Alarm Timer time-out occurs if there is an input

signal for longer than 32 ms that does not meet the

output enable filter requirements. The Alarm Timer

time-out causes:

a) The ALERT pin to go low.

b) The ALARM bit to set in the Status

STAT US Register 7 (Register 5-8).

The external MCU is informed of the Alarm timer time-

out by monitoring the ALERT pin. If the Alarm timer

time-out occurs, the external MCU can take

appropriate actions such as lowering channel

sensitivity or disabling channels. If the noise source is

ignored, the device can return to a lower standby

current draw state.

The timer is reset when the:

•CS

pin is low (any SPI command).

• Ou tput enable filter is disabled.

• LFDATA pin is enabled (signal passed output

enable filter).

The timer starts after the AGC initialization time.

The time r causes a low outp ut on the AL ERT pin when:

• Output enable filter is enabled and modulated

input signal is present for TALARM, but does not

pass the output enable filter requirement.

5.14.4 PULSE WIDTH TIMER

The Pulse Width Timer is used to verify that the

received output enable sequence meets both the

minimum TOEH and minimum TOEL requirements.

5.14.5 PERIOD TIMER

The Period Timer is used to verify that the received

output enable sequence meets the maximum TOET

requirement.

5.14.6 AG C INITIALIZATI ON TIME R (TAGC)

This timer is used to keep the output enable filter in

Reset while the AGC settles on the input signal. The

time-out period is approximately 3.5 ms. At the end of

this time (TAGC), the input should remain high (TPAGC),

otherwise the counting is aborted and a Soft Reset is

issued. See Figure 5-4 for details.

Note: The Alarm timer is disabled if the output

enable filter is disabled.

Note 1: The device needs continuous and

uninterrupted high input signal during

AGC initialization time (TAGC). Any

absence of signal during this time may

reset the timer and a new input signal is

needed for AGC settling time, or may

result in improper AGC gain settings

which will produc e invalid output.

2: The rest of the device section wakes up

if any of these input channels receive

the AGC settling time correctly. STATUS

cate which input channels have waken

up the device first. Valid input signal on

multiple input pins can cause more than

one channel's indicator bit to be set.

MCP2030

FIGURE 5-1: Functional Block Diagram.

Configuration

To Tuning Cap X

To Tuning Cap Y

To Tuning Cap Z

To Modulation

VSST

LCX

LCY

LCZ

LCCOM

Transistors

Registers

VDDT

To Sensitivity Z

To Sensitivity Y

To Sensitivity X

Modulation

Depth

AGC Preserve

LCCOM

Detector

CS LFDATA/SCLK/ALERT

External MCU

Command Decoder/Controller

Mod Tune X

Output Enable

Lim

LCCOM

Mod T une Y

Lim

Mod Tu ne Z

Lim

32 kHZ

Oscillator

AGC

Sensitivity

Control X

Sensitivity

Control Y

Sensitivity

Control Z

Filter

AGC

Timer

RSSI CCLK/SDIO

÷ 64

Watchdog

WAKEX

WAKEZ

WAKEY

MCP2030

FIGURE 5-2: Input Signal Path.

Limiter MOD

FET Capacitor

Tuning Var

Atten

FGA1 FGA2

Full-Wave

LFDATA

LCX/

LCY/

LCZ

LCCOM

Carrier

>4V

WAKEZ

WAKEY

CLKDIV

DATOUT

AGC

Feedback

Peak

REF GEN

0.1V

AGCACT

AGCSIG

Demodulator

Decode

AGC

Registers

Configuration

Sens.

Control

Legend:

FGA = Fixed Gain Amplifier

FWR = Full-wave Rectifier

LPF = Low-pass Filter

PD = Peak Detector

Detector

–

0.4V

≈

Data Slicer

MOD Depth Control

Output Enable

Filter

Amplifier

≈

Rectifier Low-Pass

Filter Detector

Auto-Channel

Selector

32 kHz

Clock/AGC

/1 OR /4

CHX

CHY

CHZ ACT

AUTOCHSEL

LFDATA

RSSI GEN

Timer

÷ 64

RSSI

DETZ

DETY

DETX

WAKEX

MCP2030

5.15 Configurable Output Enable Filt er

The purpose of this filter is to enable the LFDATA out-

put and wake the external microcontroller only after

receivi ng a spe cific se quence o f puls es on the LC input

pins. Therefore, it prevents waking up the external

microc ontroll er due to no ise or unwa nte d input sign als.

The circuit compares the timing of the demodulated

header waveform with a pre-defined value, and

enables the demodulated LFDATA output when a

match occu rs.

The output enable filter consists of a high (TOEH) and

low duration (TOEL) of a pulse immediately after the

AGC settling gap time. The selection of high and low

times further implies a max period time. The output

enable high and low times are determined by SPI

programming. Figure 5-3 and Figure 5-4 show the

output enable filter waveform s.

There should be no missing cycles during TOEH.

Missing cycles may result in failing the output enable

condition.

FIGURE 5-3: Output Enable Filter Timing.

Data Packet

t ≥ TOEH t ≥ TOEL

Required Output Enable Sequence

LFDATA output is enabled

on this rising edge

t ≤ TOET

Demodulator

Output TGAP

Device Wake-up

Start bit

AGC

(TAGC + TPAGC)

TSTAB

and AGC Stabilization Gap Pulse

MCP2030

FIGURE 5-4: Output Enable Filter Timing Example (Detailed).

LF Coil Input

Demodulated LFDATA Output

Low

Standby

Mode

Current

Filter is passed and

LFDATA is enabled

Gap

TPAGC

Legend: TAGC = AGC initialization time

TPAGC = High time after TAGC

TSTAB = AGC stabilization time (TAGC + TPAGC)

TE= Time element of pulse (minimum pulse width)

TGAP = AGC stabili zation ga p

TOEH = Minimum output enable filter high time

TOEL = Minimum output enable filter low tim e

TOET = Maximum output enable filter period

3.5 ms

Filter

starts

TGAP

Start bit for data

(need

TSTAB

t ≥ TOEH

t ≥ TOEL

t ≤ TOET

t ≥ 2T

(AFE Stabilization)

“high”) Pulse

TAGC

(AGC initialization time)

MCP2030
DS21981A-page 38 © 2005 Microchip Technology Inc.
TABLE 5-1: OUTPUT ENABLE FILTER 
TIMING 
TOEH is measured from the rising edge of the
demodulator output to the first falling edge. The pulse
width must fall within TOEH ≤ t ≤ TOET.
TOEL is measured from the falling edge of the
demodu lator output to the ris ing edge of the ne xt pulse.
The pulse width must fall within TOEL ≤ t ≤ TOET.
TOET is measured from rising edge to the next rising
edge (i.e., the sum of TOEH and TOEL). The sum of TOEH
and TOEL must be t ≤ TOET. If the Configuration Register
0 (Regis ter 5-1), OEH<8:7>  is   set to ‘00’, then the fil ter
is disabled. See Figure 2-30 for this  case.
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions. 
• The received hi gh is not greater t han the 
configured minimum TOEH value.
• During TOEH, a loss of s ignal for longe r than 56 μs 
causes a filter Reset.
• The received low is not greater than the 
configured minimum TOEL value.
• The received sequence exceeds the maximum 
TOET value:
-T
OEH + TOEL > TOET
-or T
OEH > TOET
-or T
OEL > TOET
• A Soft Reset SPI command is receiv ed.
If the fil ter reset s due to a long  high-time (T OEH > T OET),
the high-pulse timer will not begin timing again until
after a gap of TE and another low-to-high transition
occurs on the demodulator output.
Disabling the output enable filter disables the TOEH and
TOEL requirement and the device passes all detected
data. See  Figure 2-30, Figure 2-31 and Figure 2-32 for
examples.
When v iewed f rom an a pplicati on perspe ctive, f rom th e
pin input, the actual output enable filter timing must
factor in the analog delays in the input path (such as
demodulator charge and discharge times).
•T
OEH - TDR + TDF
•T
OEL + TDR - TDF
The output enable filter starts immediately after TGAP,
the gap after AGC stabilization period.
5.16 Input Sensitivity Control
The device has typical input sensitivity of 3 mVPP. This
means any input signal with amplitude greater than 3
mVPP can be detected. The internal AGC loop regu-
lates the detecting signal amplitude when the input
level is greater than approximately 20 mVPP. This
signal  ampli tude i s cal led “AGC-ac tive  level ”. The AG C
loop reg ulates the inpu t voltage so th at  the  in put signal
amplitude range will be kept within the linear range of
the detection circuits without saturation. The AGC
Acti ve  Sta t us  bi t ( AGC AC T< 5> ) i n  STATUS Reg is t er 7
(Register 5-8) is se t if th e AGC l oop reg ulates th e inp ut
voltage.
Table 5-2 shows the input sensitivity comparison when
the AGCSIG option is us ed. When AGCSIG option  bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 5-1). The channel input
sensitivity can be reduced by setting the appropriate
Configuration registers. Configuration Register 3
(Register 5-4), Configuration Register 4 (Register 5-5)
and Configuration Register 5 (Register 5-6) have the
option to reduce each channel gain from 0 dB to
approximately -30 dB.
OEH 
<1:0> OEL 
<1:0> TOEH
(ms) TOEL
(ms) TOET
(ms)
01 00 113
01 01 113
01 10 124
01 11 146
10 00 214
10 01 214
10 10 225
10 11 248
11 00 416
11 01 416
11 10 428
11 11 4410
00 XX Filter Disabled
Note 1: The timing values of TOEH and TOEL are 
minimum and TOET is maximum at room 
temperature and VDD = 3.0V, 32 kHz 
oscillator.

MCP2030

TABLE 5-2: INPUT SENSITIVITY VS. MODULATED SIGNAL STRENGTH SETTING (AGCSIG <7>)

5.17 Input Channels (Enable/Disable)

Each channel can be individually enabled or disabled

by programm ing bits in Configuration Register 0<3:1>

(Register 5-1).

The purpos e o f having an option to disable a particul ar

channel is to minimize current draw by powering down

as much circuitry as possible, if the channel is not

needed for o peratio n. The exact circu it s disa ble d when

an input is disabled are amplifiers, detector, full-wave

rectifier , data slicer, and modu lati on FET. Howev er, the

RF input limiter remains active to protect the silicon

from excessive antenna input voltages.

5.18 AGC Amplifier

The circuit automatically amplifies input signal voltage

levels to an acceptable level for the data slicer. Fast

attack and slow release by nature, the AGC tracks the

carrier signal level and not the modulated data bits.

The AGC inherently tracks the strongest of the three

antenna input signals. The AGC requires an AGC

initialization time (TAGC).

The AGC will attempt to regulate a channel’s peak

signal volt age into the data s licer to a desired regu lated

AGC voltage – reducing the input path’s gain as the

signal lev el atte mpts to incre ase above regulated AG C

voltage, and allowing full amplification on signal levels

below th e regulated AGC voltage.

The AGC has two modes of operation:

1. During the AGC initialization time (TAGC), the

AGC time constant is fast, allowing a reasonably

short acquisition time of the continuous input

signal.

2. After TAGC, the AGC switches to a slower time

constant for data slicing.

Also, the AGC is fro zen when the input sig nal enve lope

is low. The AGC tracks only high envelope levels.

5.19 AGC Preserve

The AGC preserve feature is used to preserve the AGC

value during the AGC initialization time (TAGC) and

apply the value to the data slicing circuit for the follow-

ing dat a stream s instead of using a new tracki ng valu e.

This feature is useful to demodulate the input signal

correctly when the input has random amplitude varia-

tions at a given time period. This feature is enabled

when the device receives an AGC Preserve On com-

mand and disabled if it receives an AGC Preserve Off

command. Once the AGC Preserve On command is

received, the device acquires a new AGC value during

each AGC initialization time and preserves the value

until a So ft R eset or an AGC Preserve O ff command i s

issued. Therefore, it does not need to issue another

AGC Preserve On command. An AGC Preserve Off

command is needed to disable the AGC preserve

feature (see Section 5.31.2.5 “AGC Preserve On

Command” and Section 5.31.2.6 “AGC Preserve Off

Command” for AGC Preserve comma n ds).

AGCSIG<7>

(Config. Register 5) Description Input

Sensitivity

(Typical)

0Option Disabled – Detect any input signal level (demodulated data and

carrier clock). 3.0 mVPP

1Option Enabled – No output until AGC Status = 1 (i.e., VPEAK ≈ 20 mVPP)

(demodulated data and carrier clock).

• Provides the best signal to noise ratio.

20 mVPP

MCP2030

5.20 Soft Reset

The Soft Reset is issued in the following events:

a) After Power-on Reset (POR),

b) After Inactivity timer time-out,

c) If an “Abort” occurs,

d) After receivin g SPI Soft Reset command.

The “Abort” occurs if there is no positive signal

detected at the end of the AGC initialization period

(TAGC). The Soft Reset initializes internal circuits and

brings the device into a low current Standby mode

operatio n. The internal circui ts that are i nitialized by th e

Soft Reset includ e:

• Output Enab le Fil ter

•AGC circuits

• Demodulator

• 32 kHz Internal Oscillator

The Soft Reset has no effect on the Configuration register

setup, except for some of the AFE STATUS Register 7

bits. (Register 5-8).

The circuit initialization takes one internal clock cycle

(1/32 kHz = 31.25 μs). During the initialization, the

modulation transistors between each input and

LCCOM pins are turned-on to discharge any internal/

external parasitic charges. The modulation transistors

are turned-off immediately after the initialization time.

The Soft Reset is executed in Active mode only . It is not

valid in Standby mode.

5.21 Minimum Modulation Depth

Requirement for Input Signal

The device demodulates the modulated input signal if

the modulation depth of the input signal is greater than

the minimum requirement that is programmed in

Configuration Register 5 (Register 5-6). Figure 5-5

shows the definition of the modulation depth and

examples. MO DMIN<6:5> of the C onfigu ration R egister

5 offer four options. They are 60%, 33%, 14% and 6%.

The default setting is 33%.

The purpose of this feature is to enhance the

demodulation integrity of the input signal. The 6%

setting is the bes t cho ice for t he in put si gna l with w ea k

modulation depth, which is typically observed near the

high-voltage base station antenna and also at far-

distance from the base station antenna. It gives the

best demodula tio n sensit ivi ty, but is very sus ceptib le to

noise sp ikes that can resul t in a bit dete ction error. The

60% setti ng can redu ce the bit e rrors ca used by noise,

but gives the least demodulation sensitivity. See

Table 5-3 for minimum modulation depth requirement

settings.

TABLE 5-3: SETTING FOR MINIMUM

MODULATION DEPTH

REQUIREMENT

MODMIN Bits

(Config. Register 5) Modul ation Depth

Bit 6 Bit 5

00 33% (default)

01 60%

10 14%

11 8%

MCP2030

FIGURE 5-5: Modulation Depth Examples.

(a) Modulation Depth Definition

(b) Input signal vs. minimum modulation depth setting vs. LFDATA output

A - B

A + B X 100%

Modulation Depth (%) = 10 - 7

10 + 7 X 100% = 17.64%

Amplitude 10 mVPP

7 mVPP

Amplitude

Modulation Depth (%) =

Demodulated LFDATA Output when MODMIN Setting = 14%

Demodulated LFDATA Output if MODMIN Setting = 33%

Input signal with modulation dep th = 17.6 4%

Coil Input Strength

Amplitude

(LFDATA output = not toggled)

(LFDATA output = toggled)

Input Signal

MCP2030

5.22 Low-Current Sleep Mode

The device can stay at an ultra low-current mode

(Sleep mode) when it receives a Sleep command via

the Serial Peripheral Interface (SPI). All circuits includ-

ing the RF Limiter, except the minimum circuitry

required to retain register memory and SPI capability,

will be powered down to minimize the current draw.

Power-on Reset or any SPI command, other than the

Sleep command, is required to wake the device from

Sleep.

5.23 Low-Current Standby Mode

The device is in Standby mode when no input signal is

present on the input pins, but is powered and ready to

receive any incoming signals.

5.24 Low-Current Active Mode

The device is in Low-Current Active mode when an

input signal is present on any input pin and internal

circuitry is switching with the received data.

5.25 Error Detection of Configuration

The Configuration registers are volatile memory.

Therefore, the contents of the registers can be cor-

rupted or cleared by any electrical incidence such as

battery di sc on nec t. To ensure dat a inte gri ty, the dev ic e

has an error detection mechanism using row and col-

umn parity bits of the Configuration register memory

map. The bit 0 of e ac h reg is ter i s a ro w p arity bit which

is calculated ov er the eight Configuration bits (from bit

1 to b it 8). The Col umn Pari ty Reg ister ( Configu ration

lated over the respective columns (Configuration regis-

ters 0 to 5) of the Configuration bits. The STATUS

tion. Parity is to be odd. The parity bit set or cleared

makes an odd number of set bits. The user needs to

calculate the row and column parity bits using the

contents of the registers and program them. During

operation, the device continuously calculates the row

and column parity bits of the configuration memory

map. If a parity error occurs, the device lowers the

SCLK/ALERT pin (interrupting the microcontroller

section) indicating the configuration memory has been

corrupted or unloaded and needs to be reprogrammed.

At an initial condition after a Power-on Reset, the

values of the registers are all clear (default cond ition).

Therefore, the device will issue the parity bit error by

lowering the SCLK/ALERT pin. If the user reprograms

the registers with the correct parity bits, the SCLK/

ALERT pin will be toggled to logic high level

immediately.

The parity bit errors do not change or affect any

functional operation.

Table 5-4 sh ows an exam ple of the register va lues an d

corresp onding parity bits.

TABLE 5-4: CONFIGURATION REGISTER PARITY BIT EXAMPLE

(Row Parity)

Conf iguration Register 0 1010 1000 0

Conf iguration Register 1 0000 0000 1

Conf iguration Register 2 0000 0000 1

Conf iguration Register 3 0000 0000 1

Conf iguration Register 4 0000 0000 1

Conf iguration Register 5 1000 0000 0

Conf iguration Register 6

(Column Parity Register) 1101 0111 1

MCP2030

5.26 Factory Cali bration

The dev ice is cal ibrated du ring probe test to reduc e the

device-to-device variation in standby current, internal

timing and sensitivity, as well as channel-to-channel

sensitivity variation.

5.27 De-Q’ing of Antenna Circuit

When the transponder is close to the base station, the

transponder coil may develop coil voltage higher than

VDE_Q. This condition is called “near field”. The device

detects the strong near field signal through the AGC

control, and de-Q’ing the antenna circuit to reduce the

input signal amplitude.

5.28 Demodulator

The demodulator recovers the modulation data from

the received signal, containing carrier plus data, by

appropriate envelope detection. The demodulator has

a fast rise (charge) time (TDR) and a fall time (TDF)

appropriate to an envelope of input signal (see

Secti on 1 .0 “El ec tri ca l Sp eci f ica tio ns ” fo r TDR an d

TDF specifications). The demodulator contains the

full-wave rectifier, low-pass filter, peak detector and

data slicer.

FIGURE 5-6: Demodulator Charge and Discharge.

5.29 Power-On Reset

This circuit remains in a Reset state until a sufficient

supply voltage i s applied. Th e Reset release s when the

supply is sufficient for correct device operation,

nominally VPOR.

The C onfigu ration regis ters a re all cleared on a Pow er-

on Re se t. A s the Co nf i gu ra t io n reg i ster s a re pr o tec t ed

by odd row and column parity, the ALERT pin will be

pulled down – indicating to the ext erna l m ic roc ontroller

section that the configuration memory is cleared and

requires new programming.

5.30 LFDATA Output Selection

The LFDATA output can be configured to pass the

Demodulator output, Received Signal Strength Indi-

cator (RSSI) output, or Carrier Clock (CCLK). See

Configuration Register 1 (Register 5-2) for more

details.

5.30.1 DEMODULATOR OUTPUT

The demodulator output is the default configuration of

the output selection. This is the output of an envelope

detection circuit. See Figure 5-6 for the demodulator

output.

For a clea n dat a outp ut or to s ave opera ting po wer, the

input c ha nnels can b e in div id ual ly e nab led or disab le d.

If more than one channel is enabled, the output is the

sum of each output of all enabled channels. There will

be no valid output if all three channels are disabled.

When th e demod ulated output is select ed, th e output is

available in two different conditions depending on how

the options of Configuration Register 0 (Register 5-1)

are set: Output Enable Filter is disabled or enabled.

See Section 2.0 “Typical Performance Curves” for

various demodulated data output.

Related Configuration register bits:

• Configuration Register 1 (Register 5-2),

DATOUT <8:7>:

bit 8 bit 7

00: Demodulator Output

01: Carrier Clock Output

10: RSSI Output

01: RSSI Output

• Configu ration Register 0 (Register 5-1): all bits

Full-wave Rectifier output

Input at LC input pins

Demodulated LFDATA output

TDR TDF

MCP2030
DS21981A-page 44 © 2005 Microchip Technology Inc.
5.30.2 CARRIER CLOCK OUTPUT
When t h e c ar ri e r  cl oc k out p ut  i s s el ec ted ,  t he LF D ATA
output is a square pulse of the input carrier clock and
available as soon as the AGC stabilization time (TAGC)
is completed. There are two Configuration register
options for the carrier clock output: (a) clock divide-by
one or (b) clock divide-by four, depending on bit
DATOUT<7> of Configuration Register 2 (Register 5-
3). The carrier clock output is available immediately
after the AGC settling time. The Output Enable Filter,
AGCSIG, and MODMIN options are applicable for the
carrier clock output in the same way as the demodu-
lated output. The input channel can be individually
enabled or disabled for the output. If more than one
channel is enabled, the output is the sum of each out-
put of all ena bled channels . Therefore, the  carrier cl ock
output waveform is not as precise as when only one
channel is enabled. It is recommended to enable one
channel only if a precise output waveform is desired.
There will be no valid output if all three channels are
disabled. See Figure 2-32 for carrier clock output
examples.
Related Configuration register bits: 
• Configuration Register 1 (Register 5- 2), 
DATOUT <8:7>:
       bit 8   bit 7 
00: Demodulato r Output
01: Carrier Clock Output
10: RSSI Output
11: RSSI Output
• Configuration Register 2 (Register 5- 3), 
CLKDIV<7>:
0: Carrier Clock/1
1: Carrier Clock/4
• Configuration Register 0 (Register 5- 1): all b its 
are affected
• Configuration Register 5 (Register 5- 6)
5.30.3 RECEIVED SIGNAL STRENGTH 
INDICATOR (RSSI) OUTPUT
An analog current output is available at the RSSI pin
when the Received Signal Strength Indicator (RSSI)
output is selected by the Configuration register. The
analog  c urren t i s lin early  pr opor tiona l to  th e in put  sign al
strength.
All timers in the circuit, such as inactivity timer, alarm
timer, and AGC initialization time, are disabled during
the RSSI mode. Therefore, the RSSI output is not
affected by the AGC stabilization time, and available
immediately when the RSSI option is selected. The
device  enters Acti ve mode im mediately w hen the RSSI
output is selected.
When the d ev ic e recei ve s an  SPI c omma nd d urin g th e
RSSI output, the RSSI mode is temporary disabled
until the SPI communication is completed. It returns to
the RSSI mode again after the SPI communication is
completed. The RSSI mode is held until another
output type is selected (CS low turns off the RSSI
signal). To obtain the RSSI output for a partic ular in put
channel, or to save operating power, the input channel
can be individually enabled or disabled. If more than
one channel is enabled, the RSSI output is from the
strongest signal channel. There will be no valid output
if all three channels are disabled.
The RSSI output current is  linearly proportional to the
input signal strength. There are variations between
channel to channel and device to device. See
Figure 2-13 for examples. The linearity (ILRRSSI) of
the RSSI output current is tested by sampling the
outputs for three input points: 37 mVPP, 100 mVPP,
and 370 mVPP. The RSSI output current for 100 mVPP
of input signal is compared with the expected output
current obtained from the line that is connecting the
two endpoints (37 mVPP and 370 mVPP). Equation 5-1
and Figure 5-7 show the details for the RSSI linearity
specification.
EQUATION 5-1: RSSI LINEARITY 
SPECIFICATION
FIGURE 5-7: RSSI Linearity Test 
Example.
ILRRSSI(%) = 
Deviat i on at 100 mVPP of Input Signal
IRSSI for 37 0 m VPP of  I npu t Signal
where,
Deviation at  100 mVPP of Input Signal = 
[IRSSI meas ured  - IRSSI expected] at 100 mVPP of input
signal.
IRSSI expected = RSSI current obtained from the line
that is connecting two endpoints (RSSI output currents
for 37 m V PP and 370 m VPP of inputs).
x 100%
RSSI Output Cur r e nt  [μA]
y
x
37 mVPP 100 mVPP 370 mVPP
y = a+bx
= Measured
= Expected
dd = Deviation
Input Signal Amplitude

MCP2030

Related Configuration register bits:

• Configuration Register 1 (Register 5-2),

DATOUT<8:7>:

bit 8 bit 7

00: Demodulated Output

01: Carrier Clock Output

10: RSSI Output

11: RSSI Output

• Configuration Register 2 (Register 5-3),

RSSIFET<8>:

0: Pull-Down MOSFET off

1: Pull-Down MO SFET on.

• Configuration Register 0 (Register 5-1): al l bits

are affected.

FIGURE 5-8: RSSI Output Path.

Note: The pull-down MOSFET option is valid

only when the RSSI output is selected.

The MOSFET is not controllable by users

when demodulated or carrier clock output

option is selected.

RSSI Output Cur ren t

Generator

VDD

(controlled by Config. 2, bit 8)

RSSI Pull-down MOSFET

Curr ent Out put

LFDATA/CCLK Pin

RSSIFET(1)

Off

if RSSI active

RSSI Pin

Note 1: The RSSIFET is used to discharge any external

capacitor that is connected at the LFDATA pin.

MCP2030

5.30.3.1 ANALOG- TO-DIGITAL DATA

CONVERSION OF RSSI SIGNAL

The RSSI output is an analog current. It needs an

external Analog-to-Digital (ADC) data conversion

device for digitized output. The ADC data conversion

can be accomplished by using a stand-alone external

ADC device, an external MCU that has internal ADC

features , or an external MCU that has no ADC features

but instead uses firmware. The RSSIFET is used to

discharge any external charge on the LFDATA pin in

the RSSI Output mode. The MOSFET can be turned on

or off with bit RSSIFET<8> of Configuration Register 2

(Register 5-3). When it is turned on, the internal

MOSFET provides a discharge path for the external

capacitor that is connected at the LFDATA pin. This

MOSFET opti on is valid on ly if RSSI outp ut is sele cte d

and not controllable by users for demodula ted or carrier

clock output options.

See separate appl ication notes for various external ADC

implementation methods for this device.

See Figure 5-8 for RSSI output path.

5.31 Configuration Registers

5.31.1 SPI COMMUNICATION

The SPI communication is used to read from or write to

the Confi gu ratio n reg isters and to send comma nd-o nl y

messages. Three pins are used for SPI

communication: CS, SCLK/ALERT, and LFDA T A /RSSI/

CCLK/SDIO. Figure 5-9, Figure 5-10 and Figure 5-11

show examples of the SPI communication sequences.

When these pins are connected to the external MCU

I/O pins, the following are needed:

• Pin is permanently an input with an internal pull-up.

SCLK/ALERT

• Pin is an open collector output when CS is high.

An inter nal pull-up resistor exists to ensure no

spurious SPI communication between powering

and the MCU configuring its pins. This pin

becomes the SPI clock input when CS is low.

LFDATA/CCLK/SDIO

• Pin is a digital output (LFDATA) so long as CS is

high. During SPI communication, the pin is the

SPI data input (SDI) unless performing a register

Read, where it will be the SPI data outp ut (SDO).

FIGURE 5-9: Power-Up Sequence.

SCLK/ALERT

LFDATA/CCLK/SDIO

ALERT

LFDATA

(output)

(open collect or

CS pulled high by

internal pull-up

MCU pin is input.

MCU pin is input. MCU pin is input.

MCU pin output

Driving CS high

output)

SCLK pulled high

by internal pull-up

MCP2030

FIGURE 5-10: SPI Write Sequence.

SCLK/ALERT

LFDATA/CCLK/SDIO

TSU THD

TCSSC TSCCS

THI TLO

1/FSCLK

TCS1

TCSH

TCS0

ALERT

LFDATA SDI

(output) (input)

(output)

SCLK

(input) ALERT

(output)

Driven low by MCU

LFDATA

(output)

MCU pin to Input

Driven low by MCU

16 Clocks for Write Command, Address and Data

MCU pin to Output

MCU pin still Input

MCU SPI Write Details:

1. Drive the open collector ALERT output low .

• to ensure no false clocks occur when CS drops

2. Drop CS.

• SCLK/ALERT becomes SCLK input

• LFDATA/CCLK/SDIO becomes SDI input

3. Change LFDATA/CCLK/SDIO connected pin to output.

• driving SPI data

4. Clock in 16-bit SPI Write sequence – command, address, data and parity bit.

• command, address, data and parity bit

5. Change LFDATA/CCLK/SDIO connected pin to input.

6. Raise CS to complete the SPI Write.

7. Change SCLK/ALERT back to input.

LSbMSb

MCP2030

FIGURE 5-11: SPI Read Sequence.

LFDATA/RSSI/

CCLK/SDIO

Driven low by MCU

SCCS

1/F

SCLK

CS1

CSH

CS0

SDI

(input)

SCLK

(input) ALERT

(output)

LFDATA

(output)

MCU pin to Input

Driven low by MCU

MCU pin to Output

16 Clocks for Read Command, T

CSSC

CSH

CS0

SDO

SCLK

(input) ALERT

(output)

LFDATA

(output)

MCU pin to Input

Driven low by MCU

16 Clocks for Read Result

(output)

SCLK/ALERT

ALERT

LFDATA

(output)

Driven low by MCU

MCU pin still Input

MSb LSb

CSSC

Address and Dummy Data

MCU SPI Read Details:

1. Drive the open collector ALERT output low.

• To ensure no false clocks occur when CS drops.

2. Drop CS

• SCLK/ALERT becomes SCLK input.

• LFDATA/CCLK/SDIO becomes SDI input.

3. Change LFDATA/CCLK/SDIO connected pin to output.

• Driving SPI data.

4. Clock in 16-bit SPI Read sequence.

• Command, address and dummy data.

5. Change LFDATA/CCLK/SDIO connected pin to input.

6. Raise CS to complete the SPI Read entry of command and address.

7. Drop CS.

•AFE SCLK/ALERT becomes SCLK input.

• LFDATA/CCLK/SDIO becomes SDO output.

8. Clock out 16-bit SPI R ead result.

• First seven bits clocked-out are dummy bits.

• Next eight bits are the Configuration register data.

• The last bit is the Configuration register row parity bit.

9. Raise CS to complete the SPI Read.

10. Change SCLK/ALERT back to input.

Note: The TCSH is considered as one clock. Therefore, the

Configuration register data appears at 6th clock after TCSH.

MCP2030

5.31.2 COMMAND DECODER/

CONTROLLER

The circuit executes 8 SPI commands from the external

MCU. The command structure is:

Command (3 bits) + Configuration Address (4 bits) +

Data Byte and Row Parity Bit with the M ost Significant

bit first. Table 5-5 shows the available SPI commands.

The device operates in SPI mode 0,0. In mode 0,0 the

clock idles in the low state (Figure 5-12). SDI data is

loaded into the device on the rising edge of SCLK and

SDO data is clocked out on the falling edge of SCLK.

There must be multiples of 16 clocks (SCLK) while CS

is low or commands will abort.

TABLE 5-5: SPI COMMANDS

Command Address Data Row

Parity Description

Command only – Address and Data are “Don’t Care”, but need to be clocked in regardless.

000 XXXX XXXX XXXX X Clamp on – enable modulation circuit

001 XXXX XXXX XXXX X Clamp off – disable modulation circuit

010 XXXX XXXX XXXX X Enter Sleep mode (any o ther command wakes th e AFE)

011 XXXX XXXX XXXX X AGC Preserve On – to te mpora rily pre serve the curre nt AGC lev el

100 XXXX XXXX XXXX X AGC Preserve Off – AGC again tracks strongest input signal

101 XXXX XXXX XXXX X Soft Reset – resets various circuit blocks

Read Command – Data will be read from the specified register address.

110 0000 Config Byte 0 P General – options that may change during normal operation

0001 Config Byte 1 P LCX antenna tuning and LFDATA output format

0010 Config Byte 2 P LCY antenna tuning

0011 Config Byte 3 P LCZ antenna tuning

0100 Config Byte 4 P LCX and LCY sensitivity reduction

0101 Config Byte 5 P LCZ sensitivity redu ction and modu lation depth

0110 Column Parity P Column parity byte for Config Byte 0 -> Config Byte 5

0111 Status X Status – parity error, which input is active, etc.

Write Command – Data will be written to the specified register address.

111 0000 Config Byte 0 P Output enable filter, channel enable/disable, etc.

0001 Config Byte 1 P LCX antenna tuning and LFDATA output type

0010 Config Byte 2 P LCY antenna tuning

0011 Config Byte 3 P LCZ antenna tuning

0100 Config Byte 4 P LCX and LCY sensitivity reduction

0101 Config Byte 5 P LCZ sensitivity redu ction and modu lation depth

0110 Column Parity P Column parity byte for Config Byte 0 -> Config Byte 5

0111 Not Used X Register is readable, but not writable

Note: ‘P’ denotes the row parity bit (odd parity) for the respective data byte.

MCP2030

FIGURE 5-12: Detailed SPI Timing (AFE).

5.31.2.1 Clamp On Comman d

This command results in activating (turning on) the

modulation transistors of all enab led channels; channels

enabled in Configuration Regis ter 0 (Register 5-1).

5.31.2.2 Clamp Off Command

This command results in deactivating (turning off) the

modulation transistors of all channels.

5.31.2.3 Sleep Command

This command places the device in Sleep mode –

minimizing current draw by disabling all but the

essential circuitry. Any other command wakes the

device from Sleep (e.g., Clamp Off command).

5.31.2.4 Soft Reset Command

The device issues a Soft Reset when it receives an

external Soft Res et co mman d. The extern al Soft Reset

comma nd is typic ally used to end a SPI comm unication

sequence or to initialize the device for the next signal

detection sequence, etc. See Section 5.20 “Soft

Reset” for more details on Soft Reset.

If a Soft Reset command is sent during a “Clamp-on”

condition, the device still keeps the “Clamp-on” condi-

tion after the Soft Reset execution. The Soft Reset is

executed in Active mode only, not in Standby mode.

The SPI So ft Reset co mmand i s ignore d if the d evice is

not in Active mode.

5.31.2.5 AGC Preserve On Command

This command results in preserving the AGC level

during ea ch AGC ini tializ ation t ime an d appl y th e valu e

to the data slicing circuit for the following data stream.

The prese rved AGC val ue is rese t by a Soft Rese t, and

a new AGC value is acquired and preserved when it

starts a new AGC initialization time. This feature is

disabled by an AGC Preserve Off command (see

Section 5.19 “AGC Preserve”).

5.31.2.6 AGC Preserve Off Command

This co mm and disables t he AGC preserve fe ature and

returns to the normal AGC track ing mode, fas t trackin g

during AGC settling time and slow tracking after that

(see Section 5.19 “AGC Preserve”).

5.31.3 READ/WRITE COMMANDS FOR

CONFIGURATION REGISTERS

The device includes 8 Configuration registers, includ-

ing a Column Parity register and STATUS register. All

registers are readable and writable via SPI, except the

STATUS register, which is read-only. Bit 0 of each

7) that makes the register contents an odd number.

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

bit 2

SCLK

SDIO

Command Data Byte

bit 0

bit 8

bit 1

Address Row

Parity Bit

bit 0

bit 3

MSb LSb

bit 0

MCP2030

TABLE 5-6: CONFIGURATION REGISTERS SUMMARY

Configuration Register 0 OEH O EL ALRTIND LCZEN LCYEN LCXEN R0PAR

Configuration Register 1 DATOUT Channel X Tuning Capacitor R1PAR

Configuration Register 2 RSSIFET CLKDIV Channel Y Tuning Capacitor R2PAR

Configuration Register 3 Unimplemented Channel Z Tuning Capacitor R3PAR

Configuration Register 4 Channel X Sensitivity Control Channel Y Sensitivity Control R4PAR

Configuration Register 5 AUTOCHSEL AGCSIG MODMIN MODM IN Channel Z Sensitivity Control R5PAR

Column Parity Register 6 Column Parity Bits R6PAR

STATUS Register 7 Ac tive Channel Indicators AGCACT Wake-up Channel Indicators ALARM PEI

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

OEH1 OEH0 OEL1 OEL0 ALRTIND LCZEN LCYEN LCXEN R0PAR

bit 8 bit 0

bit 8-7 OEH<1:0>: Output Enable Filter High Time (TOEH) bi t

00 = Output Enable Filter disabled (no wake-up sequence required, passes all signal to LFDATA)

01 =1ms

10 =2ms

11 =4ms

bit 6-5 OEL<1:0>: Output Enable Filter Low Time (TOEL) bit

00 =1ms

01 =1ms

10 =2ms

11 =4ms

bit 4 ALRTIND: ALERT bit, output triggered by:

1 = Parity error and/or expired Alarm timer (receiving noise, see Section 5.1 4.3 “Alarm Timer”)

0 = Parity error

bit 3 LCZEN: LCZ Enable bit

1 = Disabled

0 = Enabled

bit 2 LCYEN: LCY Enable bit

1 = Disabled

0 = Enabled

bit 1 LCXEN: LCX Enable bit

1 = Disabled

0 = Enabled

bit 0 R0PAR: Register 0 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of

set bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is c leared x = Bit is unknown

MCP2030

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

DATOUT

1DATOUT

0LCXTUN5 LCXTUN4 LCXTUN3 LCXTUN2 LCXTUN1 LCXTUN0 R1PAR

bit 8 bit 0

bit 8-7 DATOUT<1:0>: LFDATA Output type bit

00 =Demodulated output

01 =Carrier clock output

10 =RSSI output

11 =RSSI output

bit 6-1 LCXT UN<5:0>: LCX Tuning Capacitance bit

000000 = +0 pF (Default)

111111 = +63 pF

bit 0 R1PAR: Register 1 Parity Bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B it is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

RSSIFET CLKDIV LCYTUN5 LCYTUN4 LCYTUN3 LCYTUN2 LCYTUN1 LCYTUN0 R2PAR

bit 8 bit 0

bit 8 RSSIFET: Pull-down MOSFET on LFDATA pad bit (controllable by user in the RSSI mode only)

1 = Pull-down RSSI MOSFET on

0 = Pull-down RSSI MOSFET off

bit 7 C LKDIV: Carrier Clock Divide-by bit

1 = Carrier clock/4

0 = Carrier clock/1

bit 6-1 LCYTUN<5:0>: LCY T uning Capacitance bit

000000 = +0 pF (Default)

111111 = +63 pF

bit 0 R2PAR: Register 2 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Va lue at POR ‘ 1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2030

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— LCZTUN5 LCZTUN4 LCZTUN3 LCZTUN2 LCZTUN1 LCZTUN0 R3PAR

bit 8 bit 0

bit 8-7 Unimplemented: Read as ‘0’

bit 6-1 LCZTUN<5:0>: LCZ Tuning Capacitance bit

000000 = +0 pF (Default)

111111 = +63 pF

bit 0 R3PAR: Register 3 Parity Bit – set/cleared so the 9-bit register contains odd p arity – an odd number of set bits

Legend:

R = Readable bit W = Wri table bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

LCXSEN3 LCXSEN2 LCXSEN1 LCXSEN0 LCYSEN3 LCYSEN2 LCYSEN1 LCYSEN0 R4PAR

bit 8 bit 0

bit 8-5 LCXSEN<3:0>(1): Typical LCX Sensitivity Reduction bit

0000 = -0 dB (Default)

0001 = -2 dB

0010 = -4 dB

0011 = -6 dB

0100 = -8 dB

0101 = -10 dB

0110 = -12 dB

0111 = -14 dB

1000 = -16 dB

1001 = -18 dB

1010 = -20 dB

1011 = -22 dB

1100 = -24 dB

1101 = -26 dB

1110 = -28 dB

1111 = -30 dB

bit 4-1 LCYSEN<3:0>(1): Typical LCY Sensitivity Reduction bit

0000 = -0 dB (Default)

1111 = -30 dB

bit 0 R4PAR: Register 4 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits

Note 1: Assured monotonic increment (or decrement) by design.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = B it is unknown

MCP2030

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

AUTOCHSEL AGCSIG MODMIN1 MODMIN0 LCZSEN3 LCZSEN2 LCZSEN1 LCZSEN0 R5PAR

bit 8 bit 0

bit 8 AUTOCHSEL: Auto-Channel Select bit

1 = Enabled – Device selects channel(s) that has demodulator output “high” at the end of TAGC; or ot herwise,

blocks the channel(s).

0 = Disabled – Device follows channel enable/disable bits defined in Register 0

bit 7 AGCSIG: Demodulator Output Enable bit, after the AGC loop is active

1 = Enabled – No output until AGC is regulating at around 20 mVPP at input pins. The A GC Active Stat us bit

is set when the AGC begins regulating.

0 = Disabled – The device passes signal of any level it is capable of detecting

bit 6-5 MODMIN<1:0>: Minimum Modulation Depth bit

00 =33%

01 =60%

10 =14%

11 =8%

bit 4-1 LCZSEN<3:0>(1): LCZ Sensitivity Reduction bit

0000 = -0 dB (Default)

1111 = -30 dB

bit 0 R5PAR: Register 5 Parity bit – set/cleared so the 9-bit register c ontains odd parity – an odd number of set bits

Note 1: Assured monotonic increment (or decrement) by design.

Legend:

R = Readable bit W = Writab le bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

COLPAR7 COLPAR6 COLPAR5 COLPAR4 COLPAR3 COLPAR2 COLPAR1 COLPAR0 R6PAR

bit 8 bit 0

bit 8 COLPAR7: Set/Cleared so that this 8th parity bit + the sum of the Config. register row parity bits contain an odd

number of set bits.

bit 7 COLPAR6: Set/Cleared suc h that this 7 th parity bi t + the sum of the 7th b its in Config. regi sters 0 through 5 cont ain

an odd number of set bits.

bit 6 COLPAR5: Set/Cleared suc h that this 6 th parity bi t + the sum of the 6th b its in Config. regi sters 0 through 5 cont ain

an odd number of set bits.

bit 5 COLPAR4: Set/Cleared suc h that this 5 th parity bi t + the sum of the 5th b its in Config. regi sters 0 through 5 cont ain

an odd number of set bits.

bit 4 COLPAR3: Set/Cleared suc h that this 4 th parity bi t + the sum of the 4th b its in Config. regi sters 0 through 5 cont ain

an odd number of set bits.

bit 3 COLPAR2: Set/Cleared such that this 3r d parity bit + the sum of the 3rd bi ts in Config. regist ers 0 through 5 contain

an odd number of set bits.

bit 2 COLPAR1: Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Config. registers 0 through 5 contain

an odd number of set bits.

bit 1 COLPAR0: Set/Cleared such that thi s 1st parity b it + the sum of the 1s t bits in Con fig. register s 0 through 5 cont ain

an odd number of set bits.

bit 0 R6PAR: Register 6 Parity bit – set/clear ed so the 9-bit register contains odd parity – an odd number of set bits

Legend:

R = Readable bit W = Wri table bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2030

See Table 5-7 for th e bit conditions o f the AFE ST A TUS

Power-on Reset.

R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI

bit 8 bit 0

bit 8 CHZACT: Channel Z Active(1) bit (cleared via Soft Reset)

1 = Channel Z is passing data after TAGC

0 = Channel Z is not passing data after TAGC

bit 7 CHYACT: Channel Y Active(1) bit (cleared via Soft Reset)

1 = Channel Y is passing data after TAGC

0 = Channel Y is not passing data after TAGC

bit 6 CHXACT: Channel X Active(1) bit (cleared via Soft Reset)

1 = Channel X is passing data after TAGC

0 = Channel X is not passing data after TAGC

bit 5 AGCACT: AGC Active Status bit (real time, cleared via Soft Reset)

1 = AGC is active (Input signal is strong). AGC is active when input signal level is approximately > 20 mVPP

range.

0 = AGC is inactive (Input signal is weak)

bit 4 WAKEZ: Wake-up Channel Z Indicator Stat us bit (cleared via Soft Reset)

1 = Channel Z caused a device wake-up (passed ÷64 clock counter)

0 = Channel Z did not cause a device wake-up

bit 3 WAKEY: Wake-up Channel Y Indicator Status bit (cleared via Soft Reset)

1 = Channel Y caused a device wake-up (passed ÷64 clock counter)

0 = Channel Y did not cause a device wake-up

bit 2 WAKEX: Wake-up Channel X Indicator Status bit (cleared via Soft Reset)

1 = Channel X caused a device wake-up (passed ÷64 clock counter)

0 = Channel X did not cause a device wake-up

bit 1 ALARM: Indicates whether an Alarm timer time-out has occurred (cleared via read “STATUS Register

command”)

1 = The Alarm timer time-out has occurred. It may cause the ALERT output to go low depending on the st ate

of bit 4 of the Configuration register 0

0 = The Alarm timer is not timed out

bit 0 PEI: Parity Error Indicator bit – indicates whether a Configuration register parity error has occurred (real time)

1 = A parity error has occurred and caused the ALERT output to go low

0 = A parity error has not occurred

Note 1: Bit is high whenever channel is passing data. Bit is low in Standby mode.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

MCP2030

TABLE 5-7: STATUS REGISTER BIT CONDITION

(AFTER POWER-ON RESET AND VARIOUS SPI COMMANDS)

Condition Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

CHZACT CHYACT CHXACT AGCACT WAKEZ WAKEY WAKEX ALARM PEI

POR 0 0 0 0 00001

Read Command

(STATUS Register only) u u u u uuu0u

Sleep Command u u u u uuuuu

Soft Reset Executed(1) 0 0 0 0 000uu

Legend: u = unchanged

Note 1: See Section 5.20 “Soft Reset” and Section 5.31.2.4 “Soft Reset Comm and ” for the condition of Soft

Reset execution.

MCP2030

6.0 PACKAGING INFORMATION

6.1 Package Marking Information

14-Lead PDIP

XXXXXXXXXXXXXX

YYWWNNN

Example

MCP2030-I/P

0510017

14-Lead SOIC

XXXXXXXXXXX

YYWWNNN

Example

MCP2030ISL

0510017

14-Lead TSSOP

XXXXXXXX

YYWW

NNN

Example

2030I

0510

017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanu meric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designat or ( )

can be found on the outer packaging for this package.

Note: In the event the fu ll Mic rochip part nu mber ca nnot be m arked o n one line, it w ill

be carried over to the next line, thus limiting the number of available

characte rs for customer-specific information.

MCP2030

14-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)

Units INCHES* MILLIMETERS

Dimen sion Li mits MIN NO M MAX MIN N OM MAX

Number of Pins n14 14

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.2 6

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overal l Length D .740 .75 0 .760 1 8.8 0 19. 05 19. 30

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacin g § eB .310 .370 .430 7.8 7 9.40 10.92

Mold Draft Angle Top α5 10 15 5 10 15

β5 10 15 5 10 15Mold Draft Angle Bottom

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-005

§ Significant Characteristic

MCP2030

14-Lead Plasti c Small Outline (SL) – Narrow, 150 mil Body (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.250.230.20.010.009.008

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.510.380.25.020.015.010hChamfer Distance 8.818.698.56.347.342.337DOverall Length 3.993.903.81.157.154.150E1Molded Pa ckag e Width 6.205.995.79.244.236.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Molded Pa ckag e Thick ness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 1414

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-065

§ Significant Characteristic

MCP2030

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body (TSSOP)

840840

Foot A ngle

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Length 5.105.004.90.201.197.193DMolded Package Length 4.504.404.30.177.173.169E1M old ed Pa ckag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002A1Standoff § 0.950.900.85.037.035.033A2Mold ed Packag e Thickness 1.10.043AOverall Height 0.65.026

Pitch 1414

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERS*INCHESUnits

A2A1

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-087

§ Significant Characteristic

MCP2030

APPENDIX A: REVISION HISTORY

Revision A (November 2005)

• Original Release of this Document.

MCP2030

NOTES:

MCP2030

PRODUCT IDENTIFICATION SYSTEM

To order or obtain inf orm ation, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO. X/XX XXX

PatternPackageTemperature

Range

Device

Device: MCP2030: Standard VDD range

MCP2030T: (Tape and Reel)

Temperature Range: I= -40°C to +85°C

Package: P = PDIP (300 mil, 14-pin)

SL = SOIC (Gull wing, 150 mil body, 14-pin)

ST = TSSOP (4.4 mm, 14-pin)

Examples:

a) MCP2030-I/P: Industrial Temp.,

14LD PDIP.

b) MCP2030-I/SL: Industrial Temp.,

14LD SOIC.

c) MCP2030-I/ST: Industrial Temp.,

14LD TSSOP.

MCP2030

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. U se of Microc hip’s products as critical com ponents in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, micro ID, MPLAB, PIC, PICmicro,

PICSTA RT, PRO MATE, Po w erSmart, rfPIC, and

SmartShunt are registered trademark s of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM. net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM, MPLIB, MPL I NK, MPSIM, PIC kit, PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, Powe rTool, rfLAB, rfPICD EM , Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet .

• Microchip believes that i t s family of products is one of the most secure families of it s kind on the market t oday, when used in the

intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are commit ted to continuously improving the code protect ion f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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Microchip:

MCP2030DM-TPR MCP2030AT-I/SL MCP2030AT-I/ST MCP2030A-I/P MCP2030A-I/SL MCP2030A-I/ST