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FEATURES
12
14
9
10
16
13
11
15
3
1
7
8
4
5
6
2
1R
1B
SN7534050...N OR NS PACKAGE
(TOP VIEW)
RE
2A
1A
2R
2B
GND
DE
1Y
1Z
2D
2Z
1D
2Y
VCC
12
14
9
10
16
13
11
15
3
1
7
8
4
5
6
2
1R
1B
SN7534051...N OR NS PACKAGE
(TOP VIEW)
1DE
2A
1A
2R
2B
GND
2DE
1Y
1Z
2D
2Z
1D
2Y
VCC
DESCRIPTION/ORDERING INFORMATION
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
•Meet or Exceed Standards TIA/EIA-422-B and •Receiver Input Sensitivity: ±200mVITU Recommendation V.11
•Receiver Input Impedance: 12 k ΩMin•Operate From Single 5-V Power Supply
•Driver 3-State Outputs•Driver Positive and Negative Current Limiting
•Receiver 3-State Outputs (SN7534050 Only)
The SN7534050 and SN7534051 dual differential drivers and receivers are monolithic integrated circuitsdesigned to meet the requirements of ANSI standards TIA/EIA-422-B and ITU Recommendations V.11.
The driver outputs provide limiting for both positive and negative currents and thermal shutdown protection fromline fault conditions on transmission bus line.
The SN7534050 combines dual 3-state differential drivers and dual 3-state differential input receivers. Thedrivers and receivers have active-high and active-low enables, respectively which can be externally connectedtogether to function as direction control. SN7534051 drivers each have an individual active-high enable.
ORDERING INFORMATION
T
A
PACKAGE
(1) (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
PDIP – N Tube of 25 SN7534050N SN7534050NReel of 1000 SN7534050NS SN7534050SOP – NS
Reel of 2000 SN7534050NSR SN7534050–20 °C to 85 °C
PDIP – N Tube of 25 SN7534051N SN7534051NReel of 1000 SN7534051NS SN7534051SOP – NS
Reel of 2000 SN7534051NSR SN7534051
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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FUNCTION TABLES
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
SN7534050, SN7534051
Each Driver
(1)
OUTPUTSINPUT ENABLE
D DE
Y Z
H H H LL H L HX L Z Z
(1) H = high level, L = low level,X = irrelevant, Z = highimpedance (off)
SN7534050
Each Receiver
(1)
DIFFERENTIAL
ENABLE OUTPUTINPUTS,
RE RA–B
V
ID
≥0.2 V L H–0.2 V < V
ID
< 0.2 V L ?V
ID
≤– 0.2 V L LX H Z
(1) H = high level, L = low level, ? = indeterminate, X = irrelevant,Z = high impedance (off)
SN7534051
Each Receiver
(1)
DIFFERENTIAL
OUTPUTINPUTS,
RA–B
V
ID
≥0.2 V H–0.2 V < V
ID
< 0.2 V ?V
ID
≤– 0.2 V L
(1) H = high level, L = low level,? = indeterminate
2
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LOGIC DIAGRAMS
1Y
3
1
14
12
910
7
13
5
11
6
15
4
2
1D
1R
2DE
1B
1Z
2D 2Y
2A
1DE
1A
2R
2Z
2B
DE
1Y
3
1
12
14
910
7
4
13
5
11
6
15
2
1R 1B
RE
1Z
2D 2Y
2A
1D
1A
2R
2Z
2B
SCHEMATIC OF INPUTS
All resistor values are nominal.
960 Ω
NOM
960 Ω
NOM
16.8 kΩ
NOM
EQUIVALENT OF RECEIVER INPUT
Driver input: R = 6 k nom
Enable input: R = 4 k nom
R = equivalent resistor
(eq)
(eq)
(eq)
Ω
Ω
EQUIVALENT OF DRIVER OR ENABLE INPUT
Input
VCC
R(eq)
Input
VCC
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
SN7534050 SN7534051
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SCHEMATIC OF OUTPUTS
All resistor values are nominal.
TYPICAL OF ALL RECEIVER OUTPUTS
TYPICAL OF ALL DRIVER OUTPUTS
Output
GND
VCC
Output
VCC
85 Ω
Nom
Absolute Maximum Ratings
(1)
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage
(2)
7 VV
I
Input voltage DE, RE, D inputs 7 VV
i
Receiver input voltage A or B inputs ±25 VV
ID
Receiver differential output voltage
(3)
±25 VV
O
Driver output voltage range –10 15 VI
OL
Receiver low-level output current 50 mAN package 66θ
JA
Package thermal impedance
(4)
°C/WNS package 68Operating free-air temperature range –20 85 °CT
stg
Storage temperature range –65 150 °CLead temperature, 1.6 mm (1/16 in) from case for 10 s 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltages, except differential input voltage, are with respect to the network GND.(3) Differential input voltage is measured at the noninverting terminal, with respect to the inverting terminal.(4) The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace lengthof zero.
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Recommended Operating Conditions
DRIVER SECTION
Electrical Characteristics
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
MIN NOM MAX UNIT
V
CC
Supply voltage 4.75 5 V 5.25V
IH
High-level input voltage 2 VDE, RE, DV
IL
Low-level input voltage 0.8 VV
IC
Common-mode input voltage
(1)
Receiver ±7 VV
ID
Differential input voltage Receiver ±12 VDriver 40 mAI
OH
High-level output current
Receiver –400 µADriver –40I
OL
Low-level output current mAReceiver 16T
A
Operating free-air temperature –20 85 °C
(1) Refer to TIA/EIA-422-B for exact conditions.
over recommended supply voltage and operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
OH
High-level output voltage V
IH
= 2 V, V
IL
= 0.8 V, I
OH
= –20 mA 3.7 VV
OL
Low-level output voltage V
IH
= 2 V, V
IL
= 0.8 V, I
OL
= 20 mA 1.1 VV
OD1
Differential output voltage I
O
= 0 mA 1.5 6 VV
OD2
Differential output voltage
(2)
R
L
= 100 Ω, See Figure 1 2 VChange in magnitude of∆V
OD
R
L
= 100 Ω, See Figure 1 ±0.4 Vdifferential output voltage
(2)
V
OC
Common-mode output voltage
(2)
R
L
= 100 Ω, See Figure 1 ±3 VChange in magnitude of∆V
OC
R
L
= 100 Ω, See Figure 1 ±0.4 Vdifferential common-mode voltage
(2)
V
O
= 6 V 100I
off
Output current with power off
(2)
V
CC
= 0 V µAV
O
= –0.25 V –100I
OZ
High-impedance-state output current V
O
= –0.25 V to 6 V ±100 µAI
IH
High-level input current V
I
= 2.7 V 20 µAI
IL
Low-level input current V
I
= 0.4 V –100 µAI
OS
Short-circuit output current
(2) (3)
V
O
= V
CC
or GND –30 –150 mAOutput enabled 80 110I
CC
Supply current (total package) No load mAOutput disabled 50 80
(1) All typical values are at V
CC
= 5 V and T
A
= 25 °C.(2) Refer to TIA-EIA-422-B for exact conditions.(3) Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
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Switching Characteristics
RECEIVER SECTION
Electrical Characteristics
Switching Characteristics
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
V
CC
= 5 V, C
L
= 50 pF, T
A
= 25 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(OD)
Differential output delay time R
L
= 100 Ω, C
L
= 50 pF, See Figure 3 20 25 nst
t(OD)
Differential output transition time R
L
= 100 Ω, C
L
= 50 pF, See Figure 3 27 35 nst
PLH
Propagation delay time, low- to high-level output R
L
= 27 Ω, See Figure 4 20 25 nst
PHL
Propagation delay time, high- to low-level output R
L
= 27 Ω, See Figure 4 20 25 nst
PZH
Output enable time to high level R
L
= 110 Ω, See Figure 5 80 120 nst
PZL
Output enable time to low level R
L
= 110 Ω, See Figure 6 40 60 nst
PHZ
Output disable time from high level R
L
= 110 Ω, See Figure 5 90 120 nst
PLZ
Output disable time from low level R
L
= 110 Ω, See Figure 6 30 45 ns
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going input threshold voltage, differential input 0.2 VNegative-going input threshold voltage, differentialV
IT–
–0.2
(2)
VinputV
hys
Input hysteresis (V
IT+
– V
IT–
) 50 mVV
IK
Input clamp voltage, RE SN7534050 I
I
= –18 mA –1.5 VV
ID
= 200 mV,V
OH
High-level output voltage See Figure 2 2.7 VI
OH
= –400 µA,
I
OL
= 8 mA 0.45V
ID
= –200 mV,V
OL
Low-level output voltage VSee Figure 2
I
OL
= 16 mA 0.5I
OZ
High-impedance-state output current SN7534050 V
O
= 0.4 V to 2.4 V ±20 µAV
I
= 10 V 1.5I
I
Line input current Other input at 0 V mAV
I
= –10 V –2.5I
IH
High-level enable input current, RE SN7534050 V
IH
= 2.7 V 20 µAI
IL
Low-level enable input current, RE SN7534050 V
IL
= 0.4 V –100 µAr
I
Input resistance 12 k ΩI
OS
Short circuit output current –15 –85 mAI
CC
Supply current (total package) No load, enabled 80 110 mA
(1) All typical values are at V
CC
= 5 V and T
A
= 25 °C.(2) The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet forcommon-mode input voltage and threshold voltage levels.
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ID
= 1.5 V, C
L
= 15 pF,t
PLH
Propagation delay time, low- to high-level output 20 35 nsSee Figure 7V
ID
= 1.5 V, C
L
= 15 pF,t
PHL
Propagation delay time, high- to low-level output 22 35 nsSee Figure 7t
PZH
Output enable time to high level SN7534050 C
L
= 15 pF, see Figure 8 17 25 nst
PZL
Output enable time to low level SN7534050 C
L
= 15 pF, See Figure 8 20 27 nst
PHZ
Output disable time from high level SN7534050 C
L
= 15 pF, See Figure 8 25 40 nst
PLZ
Output disable time from low level SN7534050 C
L
= 15 pF, See Figure 8 30 40 ns
6
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PARAMETER MEASUREMENT INFORMATION
VOD2
VOC
RL
2
RL
2
VID
VOH
IOH
IOL
VOL
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
Figure 1. Driver Test Circuit,V
OD
and V
OC
Figure 2. Receiver Test Circuit,V
OH
and V
OL
A. C
L
includes probe and jig capacitance.B. The pulse generator has the following characteristics: PRR ≤1 MHz, duty cycle = 50%, t
r
= t
r
≤6 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms,t
d(OD)
and t
t(OD)
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TEST CIRCUIT
C
(see Note A)
L= 50 pF
RL= 27 Ω
Output
2.3 V
Input
(see Note B)
VOLTAGE WAVEFORMS
Y
Z
Input
(see Note A) 0 V
1.5 V 1.5V
3 V
2.3 V
2.3 V
2.3 V
2.3 V
tPLH
tPLH
tPHL
tPHL VOH
VOL
VOL
VOH
Output
VOH
0 V
Input DE 1.5 V 1.5V
VOLTAGE WAVEFORMS
3 V
2.3 V
GND
0.5 V
tPZH tPHZ
TEST CIRCUIT
C
(see Note A)
L= 50 pF
(see Note B)
DE RL= 110 Ω
Output
0 V or 3 V
50 Ω
Pulse
Generator
Output
VOL
0 V
Input DE 1.5 V 1.5V
VOLTAGE WAVEFORMS
3 V
2.3 V
5 V
0.5 V
tPZL tPLZ
TEST CIRCUIT
C
(see Note A)
L= 50 pF
(see Note B)
DE
RL= 110 Ω
Output
5 V
0 V or 3 V
50 Ω
Pulse
Generator
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. The pulse generator has the following characteristics: PRR ≤1 MHz, duty cycle = 50%, t
r
= t
r
≤6 ns.
Figure 4. Driver Test Circuit and Voltage Waveforms,t
PLH
and t
PHL
A. C
L
includes probe and jig capacitance.B. The pulse generator has the following characteristics: PRR ≤1 MHz, duty cycle = 50%, t
r
= t
r
≤6 ns.
Figure 5. Driver Test Circuit and Voltage Waveforms,t
PZH
and t
PHZ
A. C
L
includes probe and jig capacitance.B. The pulse generator has the following characteristics: PRR ≤1 MHz, duty cycle = 50%, t
r
= t
r
≤6 ns.
Figure 6. Driver Test Circuit and Voltage Waveforms,t
PZL
and t
PLZ
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TEST CIRCUIT
(see Note B) C
(see Note A)
L= 15 pF
0 V
50 Ω
Pulse
Generator
VOLTAGE WAVEFORMS
Output
–1.5 V
Input 0 V 0V
1.5 V
1.3 V 1.3 V
tPLH tPHL VOH
VOL
TEST CIRCUIT
5 kΩ
2 kΩ
1N916 or Equivalent
C
(see Note A)
L= 15 pF
S1 S2
5 V
S3
–1.5 V
1.5 V
50 Ω
Generator
(see Note B)
VOLTAGE WAVEFORMS
Output
VOH
1.5 V
0 V
Input
1.5 V
S1 to 1.5 V
S3 Closed
S2 Open
3 V
0 V
tPZH Output
VOL
1.5 V
4.5 V
0 V
Input
1.5 V
S1 to –1.5 V
S3 Closed
S2 Open
3 V
tPZL
~
~
Output
VOL
1.5 V
1.3 V
0 V
Input
0.5 V
S1 to –1.5 V
S3 Closed
S2 Closed
3 V
tPLZ ~
~
Output
VOH
1.5 V
0 V
Input
0.5 V
S1 to 1.5 V
S2 Closed
S3 Closed
3 V
1.3 V
~
~
tPHZ
SN7534050, SN7534051DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS833 – MAY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
A. C
L
includes probe and jig capacitance.B. The pulse generator has the following characteristics: PRR ≤1 MHz, duty cycle = 50%, t
r
= t
r
≤6 ns.
Figure 7. Receiver Test Circuit and Voltage Waveforms,t
PLH
and t
PHL
A. C
L
includes probe and jig capacitance.B. The pulse generator has the following characteristics: PRR ≤1 MHz, duty cycle = 50%, t
r
= t
r
≤6 ns.
Figure 8. Receiver Test Circuit and Voltage Waveforms,t
PZH
, t
PZL
, t
PHZ
, t
PLZ
(SN7534050)
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN7534050N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7534050NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7534050NS ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534050NSE4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534050NSG4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534050NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534050NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534050NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534051N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7534051NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN7534051NS ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534051NSE4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534051NSG4 ACTIVE SO NS 16 50 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534051NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534051NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN7534051NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 1
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN7534050NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN7534051NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7534050NSR SO NS 16 2000 346.0 346.0 33.0
SN7534051NSR SO NS 16 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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