1/17
¡ Semiconductor MSM5116165D/DSL
¡ Semiconductor
MSM5116165D/DSL
1,048,576-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
E2G0154-18-X1
This version: Oct. 1998
DESCRIPTION
The MSM5116165D/DSL is a 1,048,576-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate
CMOS technology. The MSM5116165D/DSL achieves high integration, high-speed operation, and
low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/
double-layer metal CMOS process. The MSM5116165D/DSL is available in a 42-pin plastic SOJ or
50/44-pin plastic TSOP. The MSM5116165DSL (the self-refresh version) is specially designed for
lower-power applications.
FEATURES
• 1,048,576-word ¥ 16-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input : TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 4096 cycles/64 ms, 4096 cycles/128 ms (SL version)
• Fast page mode with EDO, read modify write capability
•CAS before RAS refresh, hidden refresh, RAS-only refresh capability
•CAS before RAS self-refresh capability (SL version)
• Package options:
42-pin 400 mil plastic SOJ (SOJ42-P-400-1.27) (Product : MSM5116165D/DSL-xxJS)
50/44-pin 400 mil plastic TSOP (TSOPII50/44-P-400-0.80-K)(Product : MSM5116165D/DSL-xxTS-K)
(TSOPII50/44-P-400-0.80-L) (Product : MSM5116165D/DSL-xxTS-L)
xx indicates speed rank.
PRODUCT FAMILY
MSM5116165D/DSL-70 70 ns 124 ns
84 ns
523 mW
633 mW
Family Access Time (Max.) Cycle Time
(Min.) Standby (Max.)
Power Dissipation
MSM5116165D/DSL-50
t
RAC
50 ns
35 ns
t
AA
25 ns
20 ns
t
CAC
13 ns
20 ns
t
OEA
13 ns
MSM5116165D/DSL-60 60 ns 104 ns 578 mW
30 ns 15 ns 15 ns
Operating (Max.)
5.5 mW/
1.1 mW (SL version)
2/17
¡ Semiconductor MSM5116165D/DSL
PIN CONFIGURATION (TOP VIEW)
A9R
A8R
A7
A6
A5
A4
A11R
A10R
A0
A1
A2
A3
A9R
A8R
A7
A6
A5
A4
A11R
A10R
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
21 22
30
31
32
33
34
35
36
37
38
39
40
41
42
VCC
DQ1
DQ2
DQ3
DQ4
VCC
DQ5
DQ6
DQ7
DQ8
NC
NC
WE
VCC VSS
UCAS
LCAS
NC
DQ9
DQ10
DQ11
DQ12
VSS
DQ13
DQ14
DQ15
DQ16
VSS
14 29
RAS OE
15 28
A11R A9R
16 27
A10R A8R
17 26
A0 A7
18 25
A1 A6
19 24
A2 A5
20 23
A3 A4
1
2
3
4
5
6
7
8
9
10
11
25 26
40
41
42
43
44
45
46
47
48
49
50
VCC
DQ1
DQ2
DQ3
DQ4
VCC
DQ5
DQ6
DQ7
DQ8
NC
VCC VSS
NC
DQ9
DQ10
DQ11
DQ12
VSS
DQ13
DQ14
DQ15
DQ16
VSS
15 36
NC NC
16 35
NC LCAS
17 34
WE UCAS
18 33
RAS OE
19 32
20 31
21 30
22 29
23 28
24 27
1
2
3
4
5
6
7
8
9
10
11
25
26
40
41
42
43
44
45
46
47
48
49
50 VCC
DQ1
DQ2
DQ3
DQ4
VCC
DQ5
DQ6
DQ7
DQ8
NC
VCC
VSS
NC
DQ9
DQ10
DQ11
DQ12
VSS
DQ13
DQ14
DQ15
DQ16
VSS
15
36 NC
NC
16
35 NC
LCAS
17
34 WE
UCAS
18
33 RAS
OE
19
32
20
31
21
30
22
29
23
28
24
27
42-Pin Plastic SOJ
50/44-Pin Plastic TSOP
(K Type)
50/44-Pin Plastic TSOP
(L Type)
,
,
Note : The same power supply voltage must be provided to every VCC pin, and the same GND
voltage level must be provided to every VSS pin.
Pin Name Function
A0 - A7, Address Input
RAS Row Address Strobe
LCAS Lower Byte Column Address Strobe
DQ1 - DQ16 Data Input/Data Output
OE Output Enable
WE Write Enable
V
CC
Power Supply (5 V)
NC No Connection
A8R - A11R
UCAS Upper Byte Column Address Strobe
V
SS
Ground (0 V)
3/17
¡ Semiconductor MSM5116165D/DSL
BLOCK DIAGRAM
Timing
Generator
Refresh
Control Clock
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
Row
Deco-
ders Word
Drivers
Memory
Cells
Sense Amplifiers
Column Decoders
I/O
Controller
I/O
Controller
I/O
Selector
Input
Buffers
Output
Buffers
Output
Buffers
Input
Buffers
On Chip
V
BB
Generator
V
CC
DQ1 - DQ8
DQ9 - DQ16
UCAS
WE
A0 - A7
8
16
88
16
88
88
88
12
OE
RAS
LCAS
8
8
4
A8R - A11R
On Chip
IV
CC
Generator
V
SS
FUNCTION TABLE
Function Mode
RAS
H
L
Input Pin
LCAS
*
H
L
UCAS
H
WE
H
H
H
L
L
OE
L
L
L
H
L
L
L
L
L
H
L
L
H
L
L
H
L
*
*
*
*
*
H
Lower Byte Read
Upper Byte Read
Word Read
Refresh
Standby
Lower Byte Write
DQ Pin
DQ1 - DQ8
High-Z
High-Z
D
OUT
D
IN
DQ9 - DQ16
High-Z
High-Z
High-Z
D
OUT
Don't Care
High-Z
D
OUT
D
OUT
Don't Care
D
IN
Upper Byte Write
LLLL H D
IN
D
IN
Word Write
HLLL H High-Z High-Z —
H
*: "H" or "L"
4/17
¡ Semiconductor MSM5116165D/DSL
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Voltage on Any Pin Relative to V
SS
Short Circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
V
IN
, V
OUT
Symbol
I
OS
P
D
*
T
opr
T
stg
–0.5 to V
CC
+ 0.5
50
1
0 to 70
–55 to 150
Rating
mA
W
°C
°C
Parameter
V
Unit
Voltage on V
CC
Supply Relative to V
SS
V
CC
–0.5 to 7 V
Recommended Operating Conditions
*: Ta = 25°C
Power Supply Voltage
Input High Voltage
Input Low Voltage
V
CC
Symbol
V
SS
V
IH
V
IL
5.0
0
—
—
Typ.Parameter
4.5
0
2.4
–0.5
*2
Min.
5.5
0
V
CC
+ 0.5
*1
0.8
Max.
(Ta = 0°C to 70°C)
V
Unit
V
V
V
Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width
is with respect to the point at which VCC is applied).
*2. The input voltage is VSS – 2.0 V when the pulse width is less than 20 ns (the pulse width
is with respect to the point at which VSS is applied).
Capacitance
Input Capacitance
(A0 - A7, A8R - A11R)
Input Capacitance
Output Capacitance (DQ1 - DQ16)
C
IN1
Symbol
C
IN2
C
I/O
5
7
7
Max.
pF
Unit
pF
pF
Parameter
(V
CC
= 5 V ±10%, Ta = 25°C, f = 1 MHz)
—
—
—
Typ.
(RAS, LCAS, UCAS, WE, OE)
5/17
¡ Semiconductor MSM5116165D/DSL
DC Characteristics
Parameter
Symbol
Condition
MSM5116165
D/DSL-50
MSM5116165
D/DSL-60
MSM5116165
D/DSL-70
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C)
I
OH
= –5.0 mAOutput High Voltage
I
OL
= 4.2 mAOutput Low Voltage
0 V £ V
I
£ 6.5 V;
All other pins notInput Leakage Current
under test = 0 V
DQ disable
Output Leakage Current 0 V £ V
O
£ V
CC
RAS, CAS cycling,
Average Power
t
RC
= Min.
Supply Current
(Operating)
RAS, CAS = V
IH
Power Supply RAS, CAS
Current (Standby)
RAS cycling,Average Power
CAS = V
IH
,Supply Current
t
RC
= Min.(RAS-only Refresh)
RAS = V
IH
,
Power Supply CAS = V
IL
,
Current (Standby) DQ = enable
Average Power
CAS before RAS
Supply Current
(CAS before RAS Refresh)
Average Power
RAS £ 0.2 V,Supply Current
CAS £ 0.2 V(CAS before RAS
V
OH
V
OL
I
LI
I
LO
I
CC1
I
CC2
I
CC3
I
CC5
I
CC6
I
CCS
≥ V
CC
–0.2 V
Min. Max. Min. Max. Min. Max.
Unit Note
RAS cycling,
2.4
0
–10
–10
—
—
—
—
—
—
—
V
CC
0.4
10
10
90
2
1
90
90
300
5
2.4
0
–10
–10
—
—
—
—
—
—
—
V
CC
0.4
10
10
85
2
1
85
85
300
5
2.4
0
–10
–10
—
—
—
—
—
—
—
V
CC
0.4
10
10
80
2
1
80
80
300
5
— 200 — 200 — 200
V
V
mA
mA
mA
mA
mA
mA
mA
mA
1, 2
1, 2
1, 2
1, 5
1
1
mA 1, 5
t
RC
= 125 ms,Average Power
CAS before RAS,Supply Current
t
RAS
£ 1 ms(Battery Backup)
I
CC10
— 400 — 400 — 400 mA1, 4,
RAS = V
IL
,Average Power
CAS cycling,Supply Current
t
HPC
= Min.(Fast Page Mode)
I
CC7
— 115 — 105 — 95 mA 1, 3
5
Self-Refresh)
Notes : 1. ICC Max. is specified as ICC for output open condition.
2. The address can be changed once or less while RAS = VIL.
3. The address can be changed once or less while CAS = VIH.
4. VCC – 0.2 V £ VIH £ VCC + 0.5 V, –0.5 V £ VIL £ 0.2 V.
5. SL version.
6/17
¡ Semiconductor MSM5116165D/DSL
AC Characteristics (1/2)
Parameter
MSM5116165
D/DSL-60
MSM5116165
D/DSL-70
MSM5116165
D/DSL-50
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
Access Time from RAS
Access Time from CAS
Access Time from Column Address
Access Time from CAS Precharge
CAS to Data Output Buffer Turn-off Delay Time
Transition Time
RAS Precharge Time
RAS Pulse Width
RAS Pulse Width (Fast Page Mode with EDO)
RAS Hold Time
CAS Pulse Width
CAS Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
CAS to RAS Precharge Time
Row Address Set-up Time
Row Address Hold Time
Column Address Set-up Time
Column Address Hold Time
Column Address to RAS Lead Time
Access Time from OE
OE to Data Output Buffer Turn-off Delay Time
Refresh Period
RAS Hold Time referenced to OE
Unit
Min. Max. Min. Max.
RAS Hold Time from CAS Precharge
Symbol
t
RC
t
RWC
t
HPC
t
HPRWC
t
RAC
t
CAC
t
AA
t
CPA
t
CEZ
t
T
t
RP
t
RAS
t
RASP
t
RSH
t
CAS
t
CSH
t
RCD
t
RAD
t
CRP
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
t
OEA
t
OEZ
t
REF
t
ROH
t
RHCP
Note
Min. Max.
Output Low Impedance Time from CAS t
CLZ
CAS Precharge Time (Fast Page Mode with EDO)
t
CP
4, 5, 6
4, 5
4, 6
4, 13
7, 8
15
5
6
13
12
12
4
7
4
3
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
84
131
20
58
—
—
—
—
0
0
1
30
50
50
7
7
7
35
11
9
5
0
7
0
7
25
—
0
—
7
30
—
—
—
—
50
13
25
30
—
13
50
—
10,000
100,000
—
—
10,000
—
37
25
—
—
—
—
—
—
13
13
64
—
—
124
185
30
78
—
—
—
—
0
0
1
50
70
70
13
10
13
45
14
12
5
0
10
0
13
35
—
0
—
13
40
—
—
—
—
70
20
35
40
—
20
50
—
10,000
100,000
—
—
10,000
—
50
35
—
—
—
—
—
—
20
20
64
—
—
104
155
25
68
—
—
—
—
0
0
1
40
60
60
10
10
10
40
14
12
5
0
10
0
10
30
—
0
—
10
35
—
—
—
—
60
15
30
35
—
15
50
—
10,000
100,000
—
—
10,000
—
45
30
—
—
—
—
—
—
15
15
64
—
—
Refresh Period (SL version) t
REF
ms— 128 — 128— 128
Data Output Hold After CAS Low
WE to Data Output Buffer Turn-off Delay Time
RAS to Data Output Buffer Turn-off Delay Time
t
DOH
t
WEZ
t
REZ
7, 8
7
ns
ns
ns
5— 5—5—
OE Hold Time from CAS (DQ Disable) t
CHO
ns5— 5—5—
0
0
13
13
0
0
20
20
0
0
15
15
13
7/17
¡ Semiconductor MSM5116165D/DSL
AC Characteristics (2/2)
MSM5116165
D/DSL-60
MSM5116165
D/DSL-70
MSM5116165
D/DSL-50
Write Command Pulse Width
Write Command to CAS Lead Time
Write Command to RAS Lead Time
Data-in Set-up Time
CAS to WE Delay Time
RAS to WE Delay Time
Column Address to WE Delay Time
RAS to CAS Hold Time (CAS before RAS)
CAS Active Delay Time from RAS Precharge
Data-in Hold Time
Write Command Hold Time
OE Command Hold Time
OE to Data-in Delay Time
(V
CC
= 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3
Write Command Set-up Time
t
WP
t
CWL
t
RWL
t
DS
t
CWD
t
RWD
t
AWD
t
CHR
t
RPC
t
DH
t
WCH
t
OEH
t
OED
t
WCS
Min. Max.
Parameter
Symbol
Unit Note
Min. Max. Min. Max.
RAS to CAS Set-up Time (CAS before RAS)t
CSR
CAS Precharge WE Delay Time t
CPWD
14
11, 12
10
10
10
12
13
12
11, 12
12
10, 12
10
10
10
10
0
34
79
49
5
10
5
10
10
10
15
0
54
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7
7
7
0
30
67
42
5
10
5
7
7
7
13
0
47
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
10
13
13
0
44
94
59
5
10
5
13
13
13
20
0
64
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RAS Pulse Width t
RASS
16100 — ms100 — 100 —
(CAS before RAS Self-Refresh)
RAS Precharge Time t
RPS
16110 — ns90 — 130 —
(CAS before RAS Self-Refresh)
CAS Hold Time t
CHS
16–50 — ns–50 — –50 —
(CAS before RAS Self-Refresh)
Read Command Set-up Time
Read Command Hold Time
Read Command Hold Time referenced to RAS
t
RCS
t
RCH
t
RRH
12
9, 12
9
ns
ns
ns
0
0
0
—
—
—
0
0
0
—
—
—
0
0
0
—
—
—
WE Pulse Width (DQ Disable) t
WPE
10 — ns7 — 10 —
OE Command Hold Time t
OCH
10 — ns7 — 10 —
OE Precharge Time t
OEP
10 — ns7 — 10 —
8/17
¡ Semiconductor MSM5116165D/DSL
Notes: 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 2 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tCEZ (Max.), tREZ (Max.), tWEZ (Max.) and tOEZ (Max.) define the time at which the
output achieves the open circuit condition and are not referenced to output voltage
levels.
8. tCEZ and tREZ must be satisfied for open circuit condition.
9. tRCH or tRRH must be satisfied for a read cycle.
10. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
11. These parameters are referenced to the UCAS and LCAS, leading edges in an early
write cycle, and to the WE leading edge in an OE control write cycle, or a read modify
write cycle.
12. These parameters are determined by the falling edge of either UCAS or LCAS,
whichever is earlier.
13. These parameters are determined by the rising edge of either UCAS or LCAS,
whichever is later.
14. tCWL should be satisfied by both UCAS and LCAS.
15. tCP is determined by the time both UCAS and LCAS are high.
16. Only SL version.
9/17
¡ Semiconductor MSM5116165D/DSL
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
IH
V
IL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,,,,
,
,,
t
RC
t
RAS
t
RP
t
CRP
t
RCD
t
CSH
t
RSH
t
CRP
t
CAS
t
RAD
t
RAH
t
ASR
t
ASC
t
CAH
Row Column
t
WCS
t
WCH
t
DS
t
DH
Valid Data-in
t
WP
t
RAL
Open
t
RWL
t
CWL
,
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
OH
V
OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,,
,
t
RC
t
RAS
t
RP
t
CRP
t
CSH
t
CRP
t
RCD
t
RSH
t
CAS
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
t
RAL
Row Column
t
RCS
t
RRH
t
RCH
t
AA
t
ROH
t
OEA
t
CAC
t
RAC
t
OEZ
t
CEZ
Open
t
CLZ
Valid Data-out
t
REZ
TIMING WAVEFORM
Read Cycle
Write Cycle (Early Write)
E2G0104-17-41Q
10/17
¡ Semiconductor MSM5116165D/DSL
Read Modify Write Cycle
"H" or "L"
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
DQ V
I/OH
V
I/OL
–
–
Address V
IH
V
IL
–
–
WE V
IH
V
IL
–
–
OE V
IH
V
IL
–
–
,
,,
t
RWC
t
RAS
t
RP
t
CRP
t
CSH
t
RCD
t
CRP
t
RSH
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
Row Column
t
CWD
t
CWL
t
RWD
t
RWL
t
WP
t
AA
t
AWD
t
OEA
t
OED
t
CAC
t
RAC
t
OEZ
t
DS
t
DH
t
CLZ
Valid
Data-out
Valid
Data-in
t
RAD
t
RCS
t
OEH
11/17
¡ Semiconductor MSM5116165D/DSL
Fast Page Mode Read Cycle (Part-1)
Fast Page Mode Read Cycle (Part-2)
–
–
–
–
–
–
–
–
V
IH
RAS
Address
WE
DQ
CAS
OE
–
–
–
–
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Row Column
t
CRP
t
CRP
t
RP
t
RASP
t
CAS
t
CSH
"H" or "L"
Column
Column
t
RCD
t
CP
t
CAS
t
CAS
t
HPC
t
CP
t
CAH
t
ASC
t
RAD
t
RCS
t
RCH
t
RAC
t
AA
,
,
t
CAC
t
CLZ
t
WEZ
t
OEA
Valid
Data-out
Valid
Data-out
Valid
Data-out
t
RAH
t
ASR
t
CAH
t
ASC
t
CAH
t
ASC
t
CAC
t
AA
t
DOH
t
CEZ
t
CPA
t
AA
t
CAC
t
RCS
t
WPE
t
RHCP
–
–
–
–
–
–
–
–
V
IH
RAS
Address
WE
DQ
CAS
OE
–
–
–
–
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
,
,
Row Column
t
CRP
t
RP
t
RASP
t
CAS
t
CSH
"H" or "L"
,
Column
,
Column
t
RCD
t
CP
t
CAS
t
CAS
t
HPC
t
CAH
t
ASC
t
RAD
t
RCS
t
AA
t
RRH
t
CAC
t
CLZ
t
CPA
t
OEA
Valid
Data-out
Valid*
Data-out
t
RAH
t
ASR
t
CAH
t
ASC
t
CAH
t
ASC
t
RAC
Valid
Data-out
t
AA
t
CAC
t
DOH
Valid*
Data-out
t
CAC
t
REZ
t
OEZ
t
OEZ
t
CHO
t
OCH
t
AA
t
OEA
t
OEP
t
OEP
t
OEA
* : Same Data,
t
CP
t
RHCP
12/17
¡ Semiconductor MSM5116165D/DSL
–
–
–
–
–
–
–
–
VIH
RAS
Address
WE
DQ
CAS
OE
–
–
–
–
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
,
,
tASR
Row Column
tCRP
tRP
tRASP
tCAS
tCSH
tRAH
,
Column
Column
tRCD tCP
tCAS tCAS
tHPC
tCP
tHPC
tASC tCAH tCAH tCAH
tASC tASC
tRAD
,
"H" or "L"
tDH
tDS
tWCH
Valid
Data-in
tDS tDH tDS tDH
tWCH tWCH
tRSH
Valid
Data-in
Valid
Data-in
tWCS
tWCS
tWCS
Fast Page Mode Read Modify Write Cycle
Fast Page Mode Write Cycle (Early Write)
–
–
–
–
–
–
–
–
V
IH
RAS
Address
WE
DQ
CAS
OE
–
–
–
–
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
I/OH
V
I/OL
t
ASR
Row
Column
t
RASP
t
CWD
t
RAH
Column
t
RCD
t
CP
t
ASC
t
CAH
t
CPA
t
ASC
t
RAD
t
RWD
"H" or "L"
Valid
Data-out
t
OEZ
t
OED
t
DS
t
WP
t
AWD
t
RCS
t
CWD
t
RWL
t
CAC
,
t
AWD
t
RAC
t
WP
t
CLZ
t
DH
t
OEH
Valid
Data-in
t
OEA
Valid
Data-out
t
OEZ
t
OED
t
CAC
t
DH
t
OEH
Valid
Data-in
t
OEA
t
CLZ
,
t
DS
t
AA
t
AA
t
RCS
t
CAH
t
CPWD
t
HPRWC
t
CRP
t
CWL
13/17
¡ Semiconductor MSM5116165D/DSL
RAS-Only Refresh Cycle
CAS before RAS Refresh Cycle
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
t
CHR
Note: WE, OE, Address = "H" or "L"
DQ V
OH
V
OL
–
–
t
RC
t
RP
t
RAS
t
RP
t
RPC
t
CP
t
CSR
t
RPC
t
CEZ
Open
RAS
CAS
V
IH
V
IL
–
–
V
IH
V
IL
–
–
Address V
IH
V
IL
–
–
,
t
RC
t
RAS
t
RP
t
CRP
t
RPC
t
ASR
t
RAH
Row
"H" or "L"
DQ V
OH
V
OL
–
–
Note: WE, OE = "H" or "L"
t
CEZ
Open
14/17
¡ Semiconductor MSM5116165D/DSL
Hidden Refresh Read Cycle
RAS
CAS
Address
OE
VIH
VIL
–
–
VIH
VIL
–
–
VIH
VIL
–
–
VIH
VIL
–
–
"H" or "L"
WE VIH
VIL
–
–
DQ VOH
VOL
–
–
,
,,
,
,,
tRC tRC
tRAS tRP tRAS tRP
tCRP tRCD tRSH tCHR
tRAD
tASR tRAH
tASC tCAH
Row Column
tRCS tRAL tRRH
tAA
tROH
tOEA
tCAC
tRAC tCLZ tOEZ
Valid Data-out
Open
–
–
–
–
–
–
–
–
V
IH
RAS
Address
WE
DQ
CAS
OE
–
–
–
–
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
"H" or "L"
,
,,
t
ASR
Row
Column
t
CRP
t
RC
t
ASC
t
RP
t
RAS
t
RCD
t
RSH
t
RAD
t
CAH
t
RAH
t
RAL
t
RWL
t
CHR
t
RAS
t
RC
t
RP
t
DS
t
WP
t
WCH
t
DH
Valid Data-in
t
WCS
Hidden Refresh Write Cycle
15/17
¡ Semiconductor MSM5116165D/DSL
CAS before RAS Self-Refresh Cycle
V
IH
RAS
CAS
–
–
–
–
V
IL
V
IH
V
IL
"H" or "L"
Note: WE, OE, Address = "H" or "L"
Only SL version
,
t
RASS
t
RPC
Open
t
RPS
t
RPC
t
CP
t
CSR
t
CHS
t
RP
–
–
DQ V
OH
V
OL
t
CEZ
16/17
¡ Semiconductor MSM5116165D/DSL
(Unit : mm)
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
SOJ42-P-400-1.27
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.86 TYP.
Mirror finish
17/17
¡ Semiconductor MSM5116165D/DSL
(Unit : mm)
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.60 TYP.
TSOPII50/44-P-400-0.80-K
Mirror finish
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1998 Oki Electric Industry Co., Ltd.
Printed in Japan
E2Y0002-28-41
