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PCKV857
70–190 MHz differential 1:10 clock driver
Product data
Supersedes data of 2001 Dec 03 2002 Sep 13
INTEGRATED CIRCUITS
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2
2002 Sep 13
FEATURES
•ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
•Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA
•Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications
•1-to-10 differential clock distribution
•Very low skew (< 100 ps) and jitter (< 100 ps)
•Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD
•SSTL_2 interface clock inputs and outputs
•CMOS control signal input
•Test mode enables buffers while disabling PLL
•Low current power-down mode
•Tolerant of Spread Spectrum input clock
•Full DDR solution provided when used with SSTL16877 or
SSTV16857
•Designed for DDR 200 and 266 DIMM applications
•Available in TSSOP-48, TVSOP-48, and VFBGA56
(8 no connects) packages
DESCRIPTION
The PCKV857 is a high-performance, low-skew, low-jitter zero delay
buffer designed for 2.5 V VDD and 2.5 V AVDD operation and
differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FBOUT, FBOUT) . The clock outputs are controlled by the clock
inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in
phase and frequency with CLK. When PWRDWN is low, all outputs
are disabled to high impedance state (3-State), and the PLL is shut
down (low power mode). The device also enters the low power
mode when the input frequency falls below 20 MHz. An input
frequency detection circuit will detect the low frequency condition
and after applying a > 20 MHz input signal, the detection circuit
turns on the PLL again and enables the outputs.
When AVDD is grounded, the PLL is turned off and bypassed for test
purposes. The PCKV857 is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70 °C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
21
22
23
24
41
42
43
44
45
46
47
48
GND
Y0
Y0
VDDQ
Y1
Y1
GND
Y2
GND
Y2
VDDQ
VDDQ
CLK
CLK
VDDQ
AVDD
AGND
GND
Y3
Y3
VDDQ
Y4
Y4
GND
GND
Y5
Y5
VDDQ
Y6
Y6
GND
GND
Y7
Y7
VDDQ
PWRDWN
FBIN
FBIN
VDDQ
FBOUT
FBOUT
GND
Y8
Y8
VDDQ
Y9
Y9
SW00691
GND
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER
48-Pin Plastic TSSOP 0 to +70 °C PCKV857DGG SOT362-1
48-Pin Plastic TSSOP (TVSOP) 0 to +70 °C PCKV857DGV SOT480-1
56-ball Plastic VFBGA10 to +70 °C PCKV857EV SOT702-1
NOTE:
1. 48 balls are connected, 8 balls are no-connects.
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 3
PIN DESCRIPTION
PINS SYMBOL DESCRIPTION
1, 7, 8, 18, 24, 25, 31, 41, 42, 48 GND SSTL_2 ground pins
2, 3, 5, 6, 9, 10, 19, 20, 22, 23, 26, 27, 29,
30, 32, 33, 39, 40, 43, 44, 46, 47 Yn, Yn, FBOUT, FBOUT SSTL_2 differential outputs
4, 11, 12, 15, 21, 28, 34, 38, 46 VDDQ SSTL_2 power pins
13, 14, 35, 36 CLKIN, CLKIN, FBIN, FBIN SSTL_2 differential inputs
16 AVDD Analog power
17 AGND Analog ground
37 PWRDWN Power-down control input
BALL CONFIGURATION
123456
A
B
C
D
E
F
G
H
J
K
SW00951
GND
GND
GND
AGND
GND
GND GND
GND
GND
GND
GND
VDD
VDD
VDD
VDD
AVDD
VDD VDD
VDD
VDD
VDD
NC NC NC NC
NC NC NC NC
CLK CLK
FBOUT
FBOUT
FBIN FBIN
PWRDWN
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 4
FUNCTION TABLE
INPUTS OUTPUTS
PLL ON/OFF
PWRDWN CLK CLK YnYnFBOUT FBOUT
PLL
ON/OFF
L L H Z Z Z1Z1OFF
L H L Z Z Z1Z1OFF
H L H L H L H ON
H H L H L H L ON
X2< 20 MHz < 20 MHz Z Z Z1Z1OFF
NOTES:
H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care
1. Subject to change. May cause conflict with FBIN pins.
2. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
BLOCK DIAGRAM
PLL
37 – PWRDWN
13 – CLK
14 – CLK
36 – FBIN
35 – FBIN
16 – AVDD
3 – Y0
2 – Y0
5 – Y1
6 – Y1
10 – Y2
9 – Y2
20 – Y3
19 – Y3
22 – Y4
23 – Y4
46 – Y5
47 – Y5
44 – Y6
43 – Y6
39 – Y7
40 – Y7
29 – Y8
30 – Y8
27 – Y9
28 – Y9
32 – FBOUT
33 – FBOUT
SW00692
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 5
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
CONDITION
MIN MAX
UNIT
VDDQ Supply voltage range 0.5 3.6 V
AVDD Supply voltage range 0.5 3.6 V
VIInput voltage range see Notes 2 and 3 –0.5 VDDQ + 0.5 V
VOOutput voltage range see Notes 2 and 3 –0.5 VDDQ + 0.5 V
IIK Input clamp current VI < 0 or VI >VDDQ —±50 mA
IOK Output clamp current VO < 0 or VO >VDDQ —±50 mA
IOContinuous output current VO = 0 to VDDQ —±50 mA
Continuous current to GND or VDDQ —±100 mA
Tstg Storage temperature range –65 +150 °C
NOTES:
1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 3.6 V maximum.
RECOMMENDED OPERATING CONDITIONS1
SYMBOL
PARAMETER
CONDITION
LIMITS
SYMBOL
PARAMETER
CONDITION
MIN TYP MAX
VDDQ Supply voltage range 2.3 — 2.7 V
AVDD Supply voltage range 2.2 — 2.7 V
VIL Low level input volta
g
eCLK, CLK,
FBIN, FBIN — — VDDQ/2 − 0.18 V
IL
g
PWRDWN −0.3 — 0.7
VIH Hi
g
h level input volta
g
eCLK, CLK,
FBIN, FBIN VDDQ/2 + 0.18 — — V
IH
gg
PWRDWN 1.7 — VDDQ + 0.3
DC input signal voltage Note 2 −0.3 — VDDQ V
V
DC differential input signal voltage CLK, FBIN Note 3 0.36 — VDDQ + 0.6 V
V
ID AC differential input signal voltage CLK, FBIN Note 3 0.7 — VDDQ + 0.6 V
VOX Output differential cross-voltage Note 4 VDDQ/2 − 0.2 VDDQ/2 VDDQ/2 + 0.2 V
VIX Input differential cross-voltage Note 4 VDDQ/2 − 0.2 — VDDQ/2 + 0.2 V
IOH High-level output current — — −12 mA
IOL Low-level output current — — 12 mA
SR Input slew rate 1 — 4 V/ns
Tamb Operating free-air temperature 0 — 70 °C
NOTES:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and
VCP is the complementary input level.
4. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 6
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST
CONDITIONS
MIN TYP MAX
UNIT
VIK Input voltage, all inputs VDDQ = 2.3 V, II = –18 mA — — −1.2 V
VO
High level out
p
ut voltage
VDDQ = min to max, IOH = –1 mA VDDQ − 0.1 — — V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
VDDQ = 2.3 V, IOH = –12 mA 1.7 — — V
VO
Low level out
p
ut voltage
VDDQ = min to max, IOL = 1 mA — — 0.1 V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
VDDQ = 2.3 V, IOL = 12 mA — — 0.6 V
IIInput current VDDQ = 2.7 V, VI = 0 V to 2.7 V — — ±10 µA
IOZ High-impedance-state output current VDDQ = 2.7 V, VO = VDDQ or GND — — ±10 µA
IDDPD Power-down current on VDDQ + AVDD CLK and CLK = 0 MHz,
PWRDWN = low;
Σ of IDD and AIDD — 30 100 µA
IDD Dynamic current on VDDQ fO = 67 MHz to 190 MHz — 200 300 mA
AIDD Supply current on AVDD fO = 67 MHz to 190 MHz — 8 10 mA
CIInput capacitance VCC = 2.5 V, VI = VCC or GND 2 2.8 3 pF
NOTE:
1. This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs.
2. All typical values are at respective nominal VDDQ.
3. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTS
Over recommended ranges of supply voltage and operating free-air temperature.
SYMBOL PARAMETER MIN MAX UNIT
fCK Operating clock frequency 60 190 MHz
Input clock duty cycle 40 60 %
Stabilization time1100 — µs
NOTE:
1. T ime required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power- up.
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 7
AC CHARACTERISTICS
GND = 0 V ; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
UNIT
SYMBOL
PARAMETER
WAVEFORM
CONDITION
MIN TYP MAX
UNIT
t(O) Static phase offset Figure 1 –150 0 150 ps
tSK(O) Output clock skew Figure 2 — — 75 ps
tSLR(O) Output clock skew rate Figure 3 1 — 2 V/ns
tJIT(PER) Jitter (period) Figure 4 fO = 67 MHz to 200 MHz –75 — 75 ps
tJIT(CC) Jitter (cycle-to-cycle) Figure 5 fO = 67 MHz to 200 MHz –75 — 75 ps
tJIT(HPER) Half-period jitter Figure 6 –100 — 100 ps
tPLH1Low to high level
propagation delay Test mode/CLK to any
output — 3.7 — ns
tPHL1High to low level
propagation delay Test mode/CLK to any
output — 3.7 — ns
NOTE:
1. Refers to transition of noninverting output.
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SW00688
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SSTL16877
or
SSTV16857 PCKV857
FRONT SIDE SSTL16877
or
SSTV16857
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 8
AC WAVEFORMS
SW00882
t(O) = Σ1
n =N t(O)n
N
t(O)n t(O)n + 1
(N is a large number of samples)
CLK
CLK
FBIN
FBIN
Figure 1. Static phase offset
SW00883
tsk(O)
Yx
Yx
Yx, FBOUT
Yx, FBOUT
Figure 2. Output skew
80% 80%
20%20%
CLOCK INPUTS
AND OUTPUTS
tSLR(I), tSLR(O) tSLR(I), tSLR(O)
VID, VOD
SW00886
Figure 3. Input and output slew rates
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 9
fO
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
tJIT(PER) = tcycle n – fO
1
SW00884
Figure 4. Period jitter
tcycle ntcycle n + 1
SW00881
tJIT(CC) = tcycle n – t cycle n+1
Yx, FBOUT
Yx, FBOUT
Figure 5. Cycle-to-cycle jitter
fO
Yx, FBOUT
Yx, FBOUT
thalf period n
1
tJIT(HPER) = thalf period n – 2*fO
1
SW00885
thalf period n + 1
Figure 6. Half-period jitter
skew ANY TWO OUTPUTS
SW00396
Figure 7. Skew between any two outputs.
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 10
t1t2
45% vt1
t1)t2v55%
SW00397
Figure 8. Duty cycle limits and measurement
TEST CIRCUIT
PCKV857
Z = 60 Ω
Z = 60 Ω
Z = 50 Ω
Z = 50 Ω
R = 10 Ω
R = 10 Ω
R = 50 Ω
R = 50 Ω
C = 14 pf
C = 14 pf
–VDD/2
–VDD/2 VTT
VTT
SCOPE
VDD/2
–VDD/2 NOTE: VTT = GND
SW00880
Figure 9. Output load test circuit
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 11
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 12
TSSOP48: plastic thin shrink small outline package; 48 leads;
body width 4.4 mm; lead pitch 0.4 mm SOT480-1
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 13
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls;
body 4.5 x 7 x 0.65 mm SOT702-1
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 14
REVISION HISTORY
Rev Date Description
_4 2002 Sep 06 Product data (9397 750 10343); fourth version supersedes Product data
2001 Dec 03.
Engineering Change Notice 853-2242 28874 (2002 Sep 09).
Modifications:
Add new package option (VFBGA) to existing product data sheet.
_3 2001 Dec 03 Product data (9397 750 09244); third version
Philips Semiconductors Product data
PCKV857
70–190 MHz differential 1:10 clock driver
2002 Sep 13 15
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may af fect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 2002
All rights reserved. Printed in U.S.A.
Date of release: 09-02
Document order number: 9397 750 10343
Philips
Semiconductors
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be
published at a later date. Philips Semiconductors reserves the right to change the specification
without notice, in order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply.
Changes will be communicated according to the Customer Product/Process Change Notification
(CPCN) procedure SNW-SQ-650A.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.