M25P40-VMN6TPB - Numonyx - Datasheet.Directory

June 2006 Rev 10 1/51

M25P40

4 Mbit, low voltage, Serial Flash memory

with 50MHz SPI bus interface

Feature summary

■4 Mbit of Flash Memory

■Page Program (up to 256 Bytes) in 1.5ms

(typical)

■Sector Erase (512 Kbit) in 1s (typical)

■Bulk Erase (4 Mbit) in 4. 5s (t ypic al)

■2.7 to 3.6V Single Supply Voltage

■SPI Bus Compatible Serial Interface

■50MHz Clock Rate (maximum)

■Deep Power-down Mode 1µA (typical)

■Electronic Signatures

– JEDEC Standard two-Byte Signature

(2013h)

– RES Instruction, One-Byte, Signature

(12h), for backward compatibility

■Packages

– ECOPACK® (RoHS compliant)

SO8 (MN)

150 mil width

VFQFPN8 (MP)

(MLP8)

www.st.com

Contents M25P40

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Contents

1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.2 Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.3 Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . 11

4.4 Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . 11

4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.6 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.7 Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3 Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.4 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4.3 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.4.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.5 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

M25P40 Contents

3/51

6.6 Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.7 Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 26

6.8 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.9 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 32

7 Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

9 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

12 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

List of tables M25P40

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List of tables

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 2. Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 3. Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Read Identification (RDID) Data-Out Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 6. Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 7. Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 8. Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 10. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 11. Data Retention and Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 12. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 13. DC Characteristics (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 14. DC Characteristics (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 15. Instruction Times (Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 16. Instruction Times (Device Grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 17. AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 18. AC Characteristics (25MHz Operation, Device Grade 6 or 3) . . . . . . . . . . . . . . . . . . . . . . 41

Table 19. AC Characteristics (40MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 20. AC Characteristics (50MHz Operation, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 22. VFQFPN8 (MLP8) 8- lea d Very thin Fin e Pitch Qu ad Fla t Pack ag e No lead ,

6x5mm, Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23. Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8

Table 24. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

M25P40 List of figures

5/51

List of figures

Figure 1. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SO and VFQFPN Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. Bus Master and memory devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. SPI Modes Supported. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 5. Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 6. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Write Enable (WREN) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 8. Write Disable (WRDI) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . 20

Figure 10. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . 22

Figure 11. Write Status Register (WRSR) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence. . . . . . . . . . . . . 25

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

and Data-Out Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 14. Page Program (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 15. Sector Erase (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 16. Bulk Erase (BE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 17. Deep Power-down (DP) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 18. Release from Deep Power-down and Read Electr onic Signature (RES) Instruction

Sequence and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 19. Release from Deep Power-down (RES) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . 33

Figure 20. Power-up Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 21. AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 22. Serial Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1. . . . . . . . . . . . . . . . . 44

Figure 24. Hold Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 25. Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . 46

Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6x5mm, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Summary description M25P40

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1 Summary description

The M25P40 is a 4 Mbit (512K x 8) Serial Flash Memory, with advanced write protection

mechanisms, accessed by a high speed SPI-co mpa tible bus.

The memory can be programmed 1 to 256 bytes at a time, using the Page Program

instruction.

The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes

wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288

bytes.

The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,

using the Sector Erase instruction.

In order to meet environmental requirements , ST offers these devices in ECOPACK®

packages.

ECOPACK® packages are Lead-fr ee and RoHS compliant.

ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

Figure 1. Logic Diagram

AI04090

VCC

M25P40

HOLD

VSS

M25P40 Summary description

7/51

Figure 2. SO and VFQFPN Connections

1. There is an exposed die paddle on the underside of the MLP8 package. This is pulled, internally, to VSS,

and must not be allowed to be connected to any other voltage or signal line on the PCB.

2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.

Table 1. Signal Names

C Serial Clock

D Serial Data Input

Q Serial Data Output

SChip Select

W Write Protect

HOLD Hold

VCC Supply Voltage

VSS Ground

AI04091B

5DVSS C

HOLDQ

M25P40

Signal description M25P40

8/51

2 Signal description

2.1 Serial Data Output (Q)

This output signal is used to tr ansf er data serially out of the de vice . Data is shifted out on the

falling edge of Serial Clock (C).

2.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are latched on the rising edge of Serial

Clock (C).

2.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on

Serial Data Output (Q) changes after the falling edge of Serial Clock (C).

2.4 Chip Select (S)

When this input signal is High, the de vice is deselected and Serial Data Output (Q) is at high

impedance. Unless an internal Program, Erase or Write Status Register cycle is in progr ess,

the device will be in the Standby Power mode (this is not the Deep Power-down mode).

Driving Chip Select (S) Low selects the device, placing it in the Active Power mode.

After Power-up, a falling edge on Chip Select (S) is required prior to the start of an y

instruction.

2.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any se rial communications with the de vice without

deselecting the device.

During the Hold condition, the Serial Data Output (Q) is high imp e danc e, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.

2.6 Write Protect (W)

The main purpose of this input signa l is to free ze the size of the area of memory that is

protected against pro g ram or er ase instructions (as specifie d by the values in the BP2, BP1

and BP0 bits of the Status Re gister).

M25P40 SPI modes

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3 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of

the two follo wing modes:

●CPOL=0, CPHA=0

●CPOL=1, CPHA=1

For these two modes , input data is latched in on the rising edge of Serial Clock (C), and

output data is available from the falling edge of Serial Clock (C).

The difference between t he t w o mod es, as shown in Figure 4, is the clock polarity when the

bus master is in Stand-by mode and not transferring data:

●C remains at 0 for (CPOL=0, CPHA=0)

●C remains at 1 for (CPOL=1, CPHA=1)

Figure 3. Bus Master and memory devices on the SPI Bus

1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

2. These pull-up resistors, R, ensure that the memory devices are not selected if the Bus Master leaves the S line in the high-

impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the same time

(e.g.: when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so that, when all

inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do not become

High at the same time, and so, that the tSHCH requirement is met).

AI12836

SPI Bus Master

SPI Memory

Device

SDO

SDI

SCK

CQD

SPI Memory

Device

CQD

SPI Memory

Device

CQD

CS3 CS2 CS1

SPI Interface with

(CPOL, CPHA) =

(0, 0) or (1, 1)

WHOLD WHOLD WHOLD

R(2) R(2) R(2)

VCC

VCC VCC VCC

VSS

VSS VSS VSS

R(2)

SPI modes M25P40

10/51

Figure 4. SPI Modes Supported

AI01438B

MSB

CPHA

CPOL

MSB

M25P40 Operating features

11/51

4 Operating features

4.1 Page Programming

To prog ram one data b yte, two in structions are required: Write Enable (WREN), which is one

byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is

followed by the internal Program cycle ( of duration t PP).

To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be

programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive

addresses on the same page of memory.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Progr am (PP) sequences with each containing only a few Bytes (see Page Program (PP),

Instruction Times (Device Grade 6) and Table 16: Instruction Times (Device Grade 3)).

4.2 Sector Erase and Bulk Erase

The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be

applied, the bytes of memory need to have been erased to all 1s (FFh). This can be

achie v ed either a se ctor at a time, using the Sector Erase (SE) instruction, or throughout the

entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of

duration tSE or tBE).

The Erase instruction must be preceded by a Write Enable (WREN) instruction.

4.3 Polling During a Write, Program or Erase Cycle

A further impro vement in the time to Write Status Register (WRSR), Prog r am (PP) or Er ase

(SE or BE) can be achieved b y no t waiting for the worst case delay (tW, tPP

, tSE, or tBE). The

Write In Progress (WIP) bit is pro vided in the Status Register so t hat the application progr am

can monitor its v alue , polling it to establish when the previous Write cycle, Prog r am cycle or

Erase cycle is complete.

4.4 Active Power, Standby Power and Deep Power-Down Modes

When Chip Select (S) is Low, the device is selected, and in the Active Power mode.

When Chip Select (S) is High, the de vice is deselected, b ut could remain in the Activ e Pow er

mode until all internal cycles have completed (Program, Erase, Write Status Register). The

device then goes in to the Standby Power mode. The device consumption drops to ICC1.

The Deep Power-down mode is entered when the specific instruction (the Deep Po wer-

down (DP) instruction) is executed. The device consumption drops further to ICC2. The

device remains in this mode until another specific instruction (the Release from Deep

Power-down and Read Electronic Signature (RES) instruction) is executed.

All other instructions are ignored while the d evice is in the Deep Power-down mode. This

can be used as an extra software protection mechanism, when the device is not in active

use, to protect the device from inadvertent Write, Program or Erase instructions.

Operating features M25P40

12/51

4.5 Status Register

The Status Regist er conta ins a n umber o f stat us and cont rol bit s that can be rea d or set (a s

appropriate) by specific instructions. For a detailed description of the Status Register bits,

see Section 6.4 : Re ad Status Register (RDSR).

4.6 Protection Modes

The environments where non-volatile memory devices are used can be very noisy. No SPI

device can operate correctly in the presence of excessiv e noise. To help combat this, the

M25P40 features the following data protection mechanisms:

●P ow er On Reset and an internal timer (tPUW) can provide prot ection against inadv ertant

changes while the power supply is outsid e the operating specification.

●Progr am, Er ase and Write Status Regist er instructions are chec ked that they consist of

a number of clock pulses that is a multiple of eight, before they are accepted for

execution.

●All instructions that modify data m ust be preceded by a Write Enable (WREN)

instruction to set the Write Enab le Latch (WEL) bit. This bit is retu rned to its rese t st ate

by the following events:

–Power-up

– Write Disable (WRDI) instruction completion

– Write Status Register (WRSR) instruction completion

– Page Program (PP) instruction completion

– Sector Erase ( SE) instruction co mpletion

– Bulk Erase (BE) instruction completion

●The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be con fig ur ed as

read-only. This is the Software Protected Mode (SPM).

●The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status

Mode (HPM).

●In addition to the low power consumption feature, the Deep Power-down mode offers

e xtra softw are protection from inadv ertant Write , Program and Erase instructions, as all

instructions are ignored except one particular instruction (the Release from Deep

Power-down instruction).

M25P40 Operating features

13/51

4.7 Hold Condition

The Hold (HOLD) signal is used to pause any se rial communications with the de vice without

resetting the clocking seque nce. However, taking this signal Low does not terminate any

Write Status Register, Program or Erase cycle that is current ly in progress.

To enter th e Hold condition, the device must be selected, with Chip Select (S) Low.

The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low (as shown in Figure 5).

The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this

coincides with Serial Clock (C) being Low.

If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition

starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes

Low. (This is shown in Figure 5).

During the Hold condition, the Serial Data Output (Q) is high imp e danc e, and Serial Data

Input (D) and Serial Clock (C) are Don’t Care.

Normally, the device is kept selected, with Chip Select (S) driv en Lo w, f or the whole dura tion

of the Hold conditi on. This is to ensure that the state of the internal logic remains unchanged

from the moment of entering the Hold condition.

If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of

resetting the internal logic of the device. To restart communication with the device, it is

necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents

the device from going back to the Hold condition.

Table 2. Protected Area Sizes

Status Register

Content Memory Content

BP2

Bit BP1

Bit BP0

Bit Protected Area Unprotected Area

0 0 0 none All sectors(1) (eight sectors: 0 to 7)

1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are

0 0 1 Upper eighth (Sector 7) Lower seven-eighths (seven sectors: 0 to

0 1 0 Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5)

0 1 1 Upper half (four sectors: 4 to 7) Lower half (four sectors: 0 to 3)

1 0 0 All sectors (eight sectors: 0 to 7) none

1 0 1 All sectors (eight sectors: 0 to 7) none

1 1 0 All sectors (eight sectors: 0 to 7) none

1 1 1 All sectors (eight sectors: 0 to 7) none

Operating features M25P40

14/51

Figure 5. Hold Condition Activation

AI02029D

HOLD

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)

M25P40 Memory organization

15/51

5 Memory organization

The memory is organized as:

●524,288 bytes (8 bits each)

●8 sectors (512 Kbits, 65536 bytes each)

●2048 pages (256 bytes each).

Each page can be individually pro grammed (bits are prog rammed from 1 to 0). The de vice is

Sector or Bulk Er asable (bits are erased from 0 to 1) but not Page Erasable.

Table 3. Memory Organization

Sector Address Range

7 70000h 7FFFFh

6 60000h 6FFFFh

5 50000h 5FFFFh

4 40000h 4FFFFh

3 30000h 3FFFFh

2 20000h 2FFFFh

1 10000h 1FFFFh

0 00000h 0FFFFh

Memory organization M25P40

16/51

Figure 6. Block Diagram

AI04986

HOLD

WControl Logic High Voltage

Generator

I/O Shift Register

Address Register

and Counter 256 Byte

Data Buffer

256 Bytes (Page Size)

X Decoder

Y Decoder

Size of the

read-only

memory area

Status

00000h

7FFFFh

000FFh

M25P40 Instructions

17/51

6 Instructions

All instruct ion s, addresses and dat a are shifted in and out of the device, most significan t bit

first.

Serial Data Input (D) is sampled on the firs t rising edge of Serial Clock (C) after Chip Select

(S) is drive n L ow. Then, t he on e- byte i nstruction cod e must be shifte d in to t he device, most

significant bit first, on Serial Data Input (D), each bit being lat ched on the rising edges of

Serial Clock (C).

The instruction set is listed in Table 4.

Every instruction sequence st arts with a one-byte instruction code. Depending on the

instruction, this might be followed by address bytes, or by data b ytes, or by both or none.

Chip Select (S) must be driven High after the last bit of the instruction sequence has be en

shifted in.

In the case of a Read Data Bytes (READ) , Read Data Bytes at Higher Speed (Fast_Read),

Read Identification (RDID), Read Status Register ( RDSR) or Release from Deep Power-

down, an d Read Electronic Signature (RES) instruction, the shifted-in instruction sequence

is followed by a data-out sequence. Chip Select (S) can be driven High after an y bit of the

data-out se quence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status

instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the

instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when

the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of

eight.

All attempts to access the memory array during a Write Status Register cycle, Program

cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program

cycle or Erase cycle continues unaffected.

Instructions M25P40

18/51

6.1 Write Enable (WREN)

The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.

The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector

Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.

The Write Enable (WREN) instruction is entere d b y driving Chip Select (S) Lo w, sending t he

instruction code, an d then driving Chip Select (S) High.

Figure 7. Write Enable (WREN) Instruction Sequence

Table 4. Instruction Set

Instruction Description One-byte Instruction

Code Address

Bytes Dummy

Bytes Data

Bytes

WREN Write Enable 0000 0110 06h 0 0 0

WRDI Write Disable 0000 0100 04h 0 0 0

RDID(1)

1. The Read Identification (RDID) instruction is available only in products with Process Technology code X

(see Application Note AN1995).

Read Identification 1001 1111 9Fh 0 0 1 to 3

RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞

WRSR Write Statu s Register 0000 0001 01h 0 0 1

READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞

FAST_READ Read Data Bytes at Higher

Speed 0000 1011 0Bh 3 1 1 to ∞

PP Page Program 0000 0010 02h 3 0 1 to 256

SE Sector Erase 1101 1000 D8h 3 0 0

BE Bulk Erase 1100 0111 C7h 0 0 0

DP Deep Power-down 1011 1001 B9h 0 0 0

RES

Release from Deep Power-

down, and Read Electronic

Signature 1010 1011 ABh 0 3 1 to ∞

Release from Deep Power-

down 0 0 0

AI02281E

21 34567

High Impedance

Instruction

M25P40 Instructions

19/51

6.2 Write Disable (WRDI)

The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.

The Write Disab le (WRDI) instruction is entered b y driving Chip Select (S) Lo w, sending th e

instruction code, an d then driving Chip Select (S) High.

The Write Enable Latch (WEL) bit is reset under the following conditions:

●Power-up

●Write Disable (WRDI) instruction completion

●Write Status Register (WRSR) instruction completion

●Page Progr am (PP) instruction completion

●Sector Erase (SE) instruction completion

●Bulk Erase (BE) instruction completion

Figure 8. Write Disable (WRDI) Instruction Sequence

AI03750D

21 34567

High Impedance

Instruction

Instructions M25P40

20/51

6.3 Read Identification (RDID)

The Read Identification (RDID) instruction is available in products with Process Technology

code X only.

The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be

read, followed by two bytes of device identification. The manufacturer identification is

assigned b y JEDEC, and has the v alue 20h f or STMicroe lectronics. T he de vice identification

is assigned b y the device manuf acturer, and indicates the memory type in the first byte

(20h), and the memory capacity of the device in the second byte (13h).

Any Read Id entification (RDID) instruction while an Erase or Pr ogram cycle is in progress , is

not decoded, and has no effect on the cycle that is in progress.

The Read Identification (RDID) instruction should not be issued while the device is in Deep

Pow er-down mode.

The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code

for the instruction is shifted in. This is followed by the 24-bit device identification, stored in

the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during

the falling edge o f Serial Clock (C).

The instruction sequence is shown in Figure 9.

The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at

any time during data output.

When Chip Select (S) is driven High, th e de vice is pu t in the Sta nd-b y Pow er mode . On ce in

the Stand-by Power mode, the device waits to be selected, so that it can rec eive, decode

and execute instructions.

Figure 9. Read Identification (RDID) Instruction Sequence and Data-Out Sequence

Table 5. Read Identification (RDID) Data-Out Sequence

Manufacturer Identification Device Identification

Memory Type Memory Capacity

20h 20h 13h

21 3456789101112131415

Instruction

AI06809b

Manufacturer Identification

High Impedance

MSB

15 1413 3210

Device Identification

MSB

16 17 18 28 29 30 31

M25P40 Instructions

21/51

6.4 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction allows the Status Register to be read. The

Status Register may be read at any time, even while a Program, Er ase or Write Status

check the Write In Progress (WIP) bit before sending a new instruction to the device. It is

also possible to read the Status Register co ntinuously, as show n in Figure 10.

The status and control bits of the Status Register are as follows:

6.4.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status

0 no such cycle is in progress.

6.4.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.

When set to 1 the inte rnal Write Enable Latch is set, when set to 0 t he internal Write Enable

Latch is reset and no Write Status Register, Program or Erase instruction is accepted.

6.4.3 BP2, BP1, BP0 bits

The Block Protect (BP2, BP1, BP0) bits are non-volatile. The y define the size of the area to

be software protected against Program and Erase instructions. These bits are written with

the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,

BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes

protected against P age Program (PP) and Sector Erase (SE) instructions. The Block Protect

(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not

been set. The Bulk Erase (BE) instruction is executed if, and only if, all Bloc k Protect (BP2,

BP1, BP0) bits are 0.

6.4.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write

Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)

signal allow the device to be put in the Hardware Protected mode (when the Status Register

Write Disable (SRWD) bit is set to 1, and Write Prot ect ( W ) is driv en Lo w). In this mode, the

non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and

the Write Status Register (WRSR) instruction is no longer accepted for e xecution.

Table 6. Status Register Format

b7 b0

SRWD 0 0 BP2 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

Instructions M25P40

22/51

Figure 10. Read Status Register (RDSR) Instruction Sequence an d Data-Out

Sequence

21 3456789101112131415

Instruction

AI02031E

Q76543210

Status Register Out

High Impedance

MSB

76543210

Status Register Out

MSB

M25P40 Instructions

23/51

6.5 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction allows new values to be written to the Status

have been executed. After the Write Enable (WREN) instruction has been decoded and

executed, the device sets the Write Enable Latch (WEL).

The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,

followed by the instruction code and the data byte on Serial Data Input (D).

The instruction sequence is shown in Figure 11.

The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the

Status Register. b6 and b5 are always read as 0.

Chip Select (S) must be driv en Hig h after the eighth bit of the d ata b yte has bee n latched in.

If not, the Write Status Register ( WRSR) instruction is not e x e cuted. As soon as Chip Sele ct

(S) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is

initiated. While the Write Status Register cycle is in progress, the Status Register may still

be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)

bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.

When the cycle is completed, the Write Enab le Latch (WEL) is reset.

The Write Status Register (WRSR) instruction allo ws the user to change the values of the

Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as

read-only, as defined in Table 2. The Write Status Register (WRSR) ins truction also allows

the user to set or reset th e Status Register Write Disable (SR WD) bit in accordance with the

Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect

(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write

Status Register (WRSR) instruction is not executed once the Har dware Protected Mode

(HPM) is entered.

Figure 11. Write Status Register (WRSR) Instruction Sequence

AI02282D

21 3456789101112131415

High Impedance

Instruction Status

765432 0

MSB

Instructions M25P40

24/51

The protection features of the device are summarized in Table 7.

When the Status Register Write Disab le (SRWD) bit of the Status Register is 0 (its initial

delivery state), it is possible to write to the St atus Register provided that the Write Enable

Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless

of the whether Write Protect (W) is driven High or Low.

When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two

cases need to be considered, depending on the state of Write Protect (W):

●If Write Protect (W) is driven High, it is possible to write to the St atus Register pro vided

that the Write Enable Latch (WEL) bit has previously been set by a Write Enable

(WREN) instruction.

●If Write Protect (W) is driven Low, it is not possible to write to the Status Register even

if the Write Enable Lat ch (WEL) bi t has previously been set by a Write Enab le (WREN)

instruction. (Attempts to write to the Status Re gister are r ejected, an d are n ot accepted

for execution). As a consequence, all the data bytes in the memory area t hat are

software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status

Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be

entered:

●by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)

Low

●or by driving Write Protect (W) Low after setting the Status Register Write Disable

(SRWD) bit.

The only way to exit the Hardware Protected Mode (H PM) once entered is to pull Write

Protect (W) High.

If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can

never be activated, and only the Software Protected Mode (SPM), using the Block Protect

(BP2, BP1, BP0) bits of the Status Register, can be used.

Table 7. Protection Modes

Signal SRWD

Bit Mode Write Prot ectio n of the

Status Register

Memory Content

Protected Area(1)

1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in .

Unpr o tected Area (1)

Software

Protected

(SPM)

Status Register is

Writable (if the WREN

instruction has set the

WEL bit)

The values in the SRWD,

BP2, BP1 and BP0 bits

can be changed

Protec ted against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

Hardware

Protected

(HPM)

Status Register is

Hardware write protected

The values in the SRWD,

BP2, BP1 and BP0 bits

cannot be changed

Protec ted against

Page Program,

Sector Erase and

Bulk Erase

Ready to accept Page

Program and Sector

Erase instructions

M25P40 Instructions

25/51

6.6 Read Data Bytes (READ)

The de vice is first selected by driving Chip Select (S) Low. Th e instruction code f or the Read

Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being

latched-in during the rising edge of Serial Clock (C). Then the memory content s, at that

address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum

frequency fR, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 12.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes (READ) instruction. When the highest

address is reached, the address counter rolls over to 000000h, allowing the read sequence

to be continued indefinitely.

The Read Data Bytes (READ) instruction is terminated b y driving Chip Select (S) High. Chip

Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)

instruction, while an Erase , Prog ra m or Write cycle is in progress, is rejected without having

any effects on the cycle that is in progress.

Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence

1. Address bits A23 to A19 are Don’t Care.

AI03748D

21 345678910 2829303132333435

2221 3210

36 37 38

76543 1 7

High Impedance Data Out 1

Instruction 24-Bit Address

MSB

Data Out 2

Instructions M25P40

26/51

6.7 Read Data Bytes at Higher Speed (FAST_READ)

The de vice is first selected by driving Chip Select (S) Low. Th e instruction code f or the Read

Data Bytes at Higher Speed (FAST_READ) instruction is f ollo w ed by a 3-byte address (A23-

A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).

Then the memory contents , at that address, is shift ed out on Serial Data Output (Q), each

bit being shifted out, at a maximum fr equency fC, during the falling edge of Serial Clock (C).

The instruction sequence is shown in Figure 13.

The first byte addressed can be at any location. The address is automatically incremented

to the next higher address after each byte of data is shifted out. The whole memory can,

therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)

instruction. When the highest address is reached, the add ress counter rolls over to

000000h, allowing the read sequence to be continued indefinitely.

The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving

Chip Select (S) High. Chip Select (S) can be driv en High at an y time during data output. An y

Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or

Write cycle is in progress, is rejected without having any effects on the cycle that is in

progress.

Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence

and Data-Out Sequence

1. Address bits A23 to A19 are Don’t Care.

AI04006

21 345678910 28293031

2221 3210

High Impedance

Instruction 24 BIT ADDRESS

32 33 34 36 37 38 39 40 41 42 43 44 45 46

765432 0

DATA OUT 1

Dummy Byte

MSB

76543210

DATA OUT 2

MSB MSB

765432 0

M25P40 Instructions

27/51

6.8 Page Program (PP)

The Page Program (PP) instruction allows b ytes to be programmed in the memory

(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction

must previously have been executed . After the Write Enable (WREN) instruction has been

decoded, the device sets the Write Enable Latch (WEL).

The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by

the instruction code , three address b ytes and at least one data b yte on Serial Data Input (D).

If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes

beyond the end of the current page are programmed from the start address of the same

page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 14.

If more tha n 256 bytes are sent t o the device, previously latched data are discard ed an d the

last 256 dat a bytes ar e guaranteed to be progr ammed corr ectly within the same pag e. If less

than 256 Data bytes are sent to device, they are correctly programmed at the requested

addresses without having any effects on the other bytes of the same page.

For optimized timings, it is recommended to use the Page Program (PP) instruction to

program all consecutive targeted Bytes in a single sequence versus using several Page

Progr am (PP) sequences with each containing only a few Bytes (see Instruction Times

(Device Grade 6) and Table 16: Instruction Times (Device Grade 3)).

Chip Select (S) must be driven High after the eighth bit of the last data b yte has been

latched in, otherwise the Page Program (PP) instruction is not executed.

As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose

duration is tPP) is initiated. While the Page Prog ram cycle is in progre ss, th e Status Register

may be read to check the value of the Write In Progress (WIP) bit. The Write In Prog ress

(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is

reset.

A Page Program (PP) instruction applied to a page which is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Instructions M25P40

28/51

Figure 14. Page Program (PP) Instruction Sequence

1. Address bits A23 to A19 are Don’t Care.

AI04082B

4241 43 44 45 46 47 48 49 50 52 53 54 5540

21 345678910 2829303132333435

2221 3210

36 37 38

Instruction 24-Bit Address

765432 0

Data Byte 1

765432 0

Data Byte 2

765432 0

Data Byte 3 Data Byte 256

2079

2078

2077

2076

2075

2074

2073

765432 0

2072

MSB MSB

MSB MSB MSB

M25P40 Instructions

29/51

6.9 Sector Erase (SE)

The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it

can be accepted, a Write Enable (WREN) instruction must previously have been executed.

After the Write Enable (WREN) instruction has been decoded, the device sets the Write

Enable Latch (WEL).

The Sector Erase (SE) instruction is entered by driving Chip Select (S) Lo w, followed by the

instruction code, an d three address bytes on Serial Data Input (D). Any address inside the

Sector (see Table 3) is a valid add ress for the Sector Erase (SE) instruction. Chip Select (S)

must be driven Low for the entire duration of the sequence.

The instruction sequence is shown in Figure 15.

Chip Select (S) must be driven High after the eighth bit of the last address byte has been

latched in, otherwise the Sector Erase (S E) instruction is not executed. As soon as Chip

Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is tSE) is

initiated. While the Sector Erase cycle is in progress, the Status Register may be read to

check the value of the Write In Progr ess (WIP) bit. The Write In Progress (WIP) bit is 1

during the self-timed Sector Erase cycle , and is 0 when it is completed. At some unspe cified

time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect

(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.

Figure 15. Sector Erase (SE) Instruc tion Sequence

1. Address bits A23 to A19 are Don’t Care.

24 Bit Address

AI03751D

21 3456789 293031

Instruction

23 22 2 0

MSB

Instructions M25P40

30/51

6.10 Bulk Erase (BE)

The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accept ed, a Write

Enable (WREN) instruction must previously have been executed. After the Write Enable

(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).

The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the

instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire

duration of the sequence.

The instruction sequence is shown in Figure 16.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)

is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the

Bulk Erase cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk

Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is

completed, the Write Enable Latch (WEL) bit is reset.

The Bulk Era se (BE) instruction is e x ecuted only if all Bloc k Protect (BP2, BP1, BP0) bits are

0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.

Figure 16. Bulk Erase (BE) Instruction Sequence

AI03752D

21 345670

Instruction

M25P40 Instructions

31/51

6.11 Deep Power-down (DP)

Executing the Deep Po wer-down (DP) instruction is the only way to put the device in the

lowest consumption mode (the Deep Power-down mode). It can also be used as an extra

softwar e protecti on mechanism, wh ile the device is not in activ e use , since in this m ode , the

device ignores all Write, Program and Erase instructions.

Driving Chip Select (S) High d eselects the de vice, and puts the de vice in the St andb y P o wer

mode (if there is no internal cycle currently in progress). But this mode is not the Deep

Power-down mode. The Deep Power-down mode can only be entered by executing the

Deep P o wer-do wn (DP) instruction, subsequently reducing th e standby current (from ICC1 to

ICC2, as specified in Table 13).

Once the device has entered the Deep Power-down mode, all instructions are ignored

except the Release from Deep Power-down and Read Electr onic Signature (RES)

instruction. This releases the device from this mode. The Release from Deep Power-down

and Read Electronic Signature (RES) instruction and the Read Identification (RDID)

instru ctio n als o allow the Electron i c Signat ur e of th e device to be output on Ser ial Da ta

Output (Q).

The Deep Power-down mode automatically stops at Power-down, and t he device always

Powers-up in the Stan d by Power mode.

The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed

by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the

entire duration of the sequence.

The instruction sequence is shown in Figure 17.

Chip Select (S) must be driven High after the eighth bit of the instruction code has been

latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as

Chip Select (S) is driven High, it requires a delay of tDP bef ore th e supply curr ent is redu ced

to ICC2 and the Deep Power-down mode is entered.

Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in

progress, is rejected without having any effects on the cycle that is in progress.

Figure 17. Deep Power -down (DP) Instruction Sequence

AI03753D

21 345670tDP

Deep Power-down Mode

Stand-by Mode

Instruction

Instructions M25P40

32/51

6.12 Release from Deep Power-down and Read Electronic

Signature (RES)

Once the device has entered the Deep Power-down mode, all instructions are ignored

except the Release from Deep Power-down and Read Electr onic Signature (RES)

instruction. Executing this instruction takes the device out of the Deep Power-down mode.

The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic

Signature, whose value for the M25P40 is 12h.

Except while an Erase, Program or Write Status Register cycle is in progress, the Relea se

from Deep Power-do wn and Read Electronic Signature (RES) instruction always provides

access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep

Power-down mode has not been entered.

Any Relea se from Deep P o wer-do wn and Read Ele ctronic Signature (R ES) instruction while

an Erase , Progr am or Write Status Register cycle is in progress, is not decoded, and has no

effect on the cycle that is in progress.

The device is first selected by driving Chip Select (S) Low. The instruction code is followed

by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge

of Serial Clock ( C). The n, the 8-bit Electronic Sig natu re , sto red in t he memory, is shifted out

on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock

(C).

The instruction sequence is shown in Figure 18.

The Release from Deep Power-down and Read Electronic Signature (RES) instruction is

terminated by driving Chip Select (S) High after the Electronic Signature has been read at

least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is

driven Low, cause the Electronic Signature to be output repeatedly.

When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the

device was not previously in the Deep Power-down mode, the transition to the Standby

Power mode is immediate. If the device was previously in the Deep Power-do wn mode,

though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select (S)

must remain High for at least tRES2(max), as specified in Table 18. Once in the Standby

Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions.

Driving Chip Select (S) High after the 8-bit inst ruction byte has been received by the device,

but before the whole of the 8-bit Electronic Signature has been transmitted for the first time

(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the

device was not previously in the Deep Power-down mode, the transition to the Standby

Power mode is immediate. If the device was previously in the Deep Power-do wn mode,

though, the transition to the Standby Power mode is delayed by tRES1, and Chip Select (S)

must remain High for at least tRES1(max), as specified in Table 18. Once in the Standby

Power mode, the device waits to be selected, so that it can receive, decode and execute

instructions.

M25P40 Instructions

33/51

Figure 18. Release fro m Deep Power-down and Read Electronic Signature (RES) Instruction

Sequence and Data-Out Sequence

1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h.

Figure 19. Release fro m Deep Power-down (RES) Instruction Seq uence

AI04047C

21 345678910 2829303132333435

2221 3210

36 37 38

765432 0

High Impedance Electronic Signature Out

Instruction 3 Dummy Bytes

MSB

Stand-by Mode

Deep Power-down Mode

MSB

tRES2

AI04078B

21 345670tRES1

Stand-by Mode

Deep Power-down Mode

QHigh Impedance

Instruction

Power-up and Power-down M25P40

34/51

7 Power-up and Power-down

At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must

follow the voltage applied on VCC) until VCC reaches the correct value:

●VCC(min) at Power-up, and then for a further delay of tVSL

●VSS at Powe r-down

Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper

Power-up and Power-down.

To avoid data corruption and inadvertent write operations during po wer-up, a Power On

Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less

than the Power On Reset (POR) threshold voltage, VWI – all operations are disabled, and

the device does not respond to any instruction.

Moreover, the de vice ignores all Write Enable (WREN), Page Program (PP), Sector Erase

(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of

tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the

correct opera tion of t he device is not guaranteed if, by this time, V CC is still belo w VCC(min).

No Write Status Register, Program or Erase instructions should be sent until the lat er of:

●tPUW after VCC passed the VWI threshold

●tVSL after VCC passed the VCC(min) level

These values are specified in Table 9.

If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be

selected for READ instructions even if the tPUW delay is not yet fully elapsed.

At Power-up, the device is in the following state:

●The device is in the Standby Power mode (not the De ep Power-down mode).

●The Write Enable Latch (WEL) bit is reset.

Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.

Each de vice in a system should ha v e the V CC rail decoupled b y a suitab le capacitor close to

the package pins. (Gener ally, this capacitor is of the order of 0.1µF).

At Power-down, when VCC drops from the operating voltage, to below the Power On Reset

(POR) threshold voltage, VWI, all operations are disabled and the device does not respond

to any instruction. (The designer needs to be aware that if a Power-down occurs while a

Write, Program or Erase cycle is in prog ress, some data corruption can result.)

M25P40 Power-up and Power-down

35/51

Figure 20. Power-up Timing

Table 8. Power-Up Timing and VWI Threshold

Symbol Parameter Min. Max. Unit

tVSL(1)

1. These parameters are characterized only.

VCC(min) to S low 10 µs

tPUW(1) Time delay to Write instruction 1 10 ms

VWI(1) Write Inhibit Voltage (Device grade 6) 1 2 V

Write Inhibit Voltage (Device grade 3) 1 2.2 V

VCC

AI04009C

VCC(min)

VWI

Reset State

of the

Device

Chip Selection Not Allowed

Program, Erase and Write Commands are Rejected by the Device

tVSL

tPUW

time

Read Access allowed Device fully

accessible

VCC(max)

Initial delivery state M25P40

36/51

8 Initial delivery state

The device is delivered with the memory arr ay erased: all bits are set t o 1 (each byt e

contains FFh). The Status Register contains 00h (all Status Register bits are 0).

9 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant qu ality documents.

Table 9. Absolute Maximum Rating s

Symbol Parameter Min. Max. Unit

TSTG Storage Temperature –65 150 °C

VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V

VCC Supply Voltage –0.6 4.0 V

VESD Electrostatic Discharge Voltage (Human Body model)(1)

1. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).

–2000 2000 V

M25P40 DC and AC parameters

37/51

10 DC and AC parameters

This section summarizes the operating and measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC Characteristic tables that

follow are derived from tests performed under the Measurement Conditions summarized in

the relevant tables. Designers should check that the operating conditions in their circuit

match the measurem ent conditions when relying on the quoted parameters.

Table 10. Operating Conditions

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.7 3.6 V

TAAmbient Operating Temperature (Device Grade 6) –40 85 °C

Ambient Operating Temperature (Device Grade 3) –40 125

Table 11. D ata Retention and Endu rance

Parameter Condition Min. Max. Unit

Erase/Program

Cycles Device Grade 6 100,000 cycles per sector

Device Grade 3 10,000

Data Retention at 55°C 20 years

Table 12. Capacitance(1)

1. Sampled only, not 100% tested, at TA=25°C and a frequency of 20MHz.

Symbol Parameter Test Condition Min.Max.Unit

COUT Output Capacitance (Q) VOUT = 0V 8 pF

CIN Input Capacitance (other pins) VIN = 0V 6 pF

DC and AC parameters M25P40

38/51

Table 13. DC Charac teristics (Device Grade 6)

Symbol Parameter T est Condition (in addition to

those in Table 10)Min. Max. Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 10 µA

ICC3 Operating Current (READ)

C = 0.1VCC / 0.9.VCC at

40MHz and 50MHz, Q = open 8mA

C = 0.1VCC / 0.9.VCC at

20MHz, Q = open 4mA

ICC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage –0.5 0.3VCC V

VIH Input High Voltage 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

VOH Output High Voltage IOH = –100µAV

CC–0.2 V

M25P40 DC and AC parameters

39/51

Table 14. DC Charac teristics (Device Grade 3)

Symbol Parameter Test Condition (in additio n to

those in Table 10)Min(1)

1. This is preliminary data.

Max(1) Unit

ILI Input Leakage Current ± 2 µA

ILO Output Leakage Current ± 2 µA

ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 µA

ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 50 µA

ICC3 Operating Current (READ)

C = 0.1VCC / 0.9.VCC at 25MHz,

Q = open 8mA

C = 0.1VCC / 0.9.VCC at 20MHz,

Q = open 4mA

ICC4 Operating Current (PP) S = VCC 15 mA

ICC5 Operating Current (WRSR) S = VCC 15 mA

ICC6 Operating Current (SE) S = VCC 15 mA

ICC7 Operating Current (BE) S = VCC 15 mA

VIL Input Low Voltage – 0.5 0.3VCC V

VIH Input High Voltage 0.7VCC VCC+0.4 V

VOL Output Low Voltage IOL = 1.6mA 0.4 V

VOH Output High Voltage IOH = –100µAV

CC–0.2 V

Table 15. Instruction Times (Device Grade 6)

Test conditions specified in Table 10 and Table 17

Symbol Alt. Parameter Min. Typ. Max. Unit

tWWrite Status Register Cycle Time 5 15 ms

tPP (1)

1. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are

obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤

256)

Page Program Cycle Time (256 Bytes) 1.4 5ms

Page Program Cycle Time (n Bytes) 0.4+

n*1/256

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 4.5 10 s

DC and AC parameters M25P40

40/51

1. Output Hi-Z is defined as the point where data out is no longer driven.

Figure 21. AC Measurement I/O Waveform

Table 16. Instruction Times (Device Grade 3)

Test conditions specified in Table 10 and Table 17

Symbol Alt. Parameter Min. Typ.(1) (2)

1. At 85°C

2. Preliminary data.

Max.(2) Unit

tWWrite Status Register Cycle Time 8 15 ms

tPP(3)

3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are

obtained with one sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤

256)

Page Program Cycle Time (256 Bytes) 1.5 5ms

Page Progr am Cycle Time (n Bytes) 0.4+

n*1.1/256

tSE Sector Erase Cycle Time 1 3 s

tBE Bulk Erase Cycle Time 4.5 10 s

Table 17. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CLLoad Capacitance 30 pF

Input Rise and Fall Times 5 ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input Timing Reference Voltages 0.3VCC to 0.7VCC V

Output Timing Reference Voltages VCC / 2 V

AI07455

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Input and Output

Timing Reference Levels

Input Levels

0.5VCC

M25P40 DC and AC parameters

41/51

Table 18. AC Characteristics (25MHz Operation, Device Grade 6 or 3)

Test conditions specified in Table 10 and Table 17

Symbol Alt. Parameter Min Typ. Max Unit

fCfC

Clock Frequency for the following

instructions: FAST_READ, PP, SE, BE, DP,

RES, WREN, WRDI, RDSR, WRSR D.C. 25 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH(1)

1. tCH + tCL must be greater than or equal to 1/ fC

tCLH Clock High Time 18 ns

tCL(1) tCLL Clock Low Time 18 ns

tCLCH(2)

2. Value guaranteed by characterization, not 100% tested in production.

Clock Rise Time(3) (peak to peak)

3. Expressed as a slew-rate.

0.1 V/ns

tCHCL(2) Clock Fall Time(3) (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relati ve to C) 10 ns

tCHSL S Not Active Hold Time (relative to C) 10 ns

tDVCH tDSU Data In Setup Time 5 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 10 ns

tSHCH S Not Active Setup Time (relative to C) 10 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ(2) tDIS Output Disable Time 15 ns

tCLQV tVClock Low to Output Valid 15 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 10 ns

tCHHH HOLD Hold Time (relative to C) 10 ns

tHHCH HOLD Setup Time (relative to C) 10 ns

tCHHL HOLD Hold Time (relative to C) 10 ns

tHHQX(2) tLZ HOLD to Output Low-Z 15 ns

tHLQZ(2) tHZ HOLD to Output High-Z 20 ns

tWHSL(4)

4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

Write Protect Setup Time 20 ns

tSHWL(4) Write Protect Hold Time 100 ns

tDP(2) S High to Deep Power-down Mode 3 µs

tRES1(2) S High to Standby Power mode without

Electronic Signature Read 3 or 30(5)

5. It is 30µs in devices produced with the “X” process technology (grade 3 devices are only produced using

the “X” process technology). Details of how to find the process letter on the device marking are given in the

Application note AN1995.

µs

tRES2(2) S High to Standby Power mode with

Electronic Signature Read 1.8 or 30(5) µs

DC and AC parameters M25P40

42/51

Table 19. AC Characteristics (40MHz Operation, Device Grade 6)

40MHz available for products marked since week 20 of 2004, only(1)

Test conditions specified in Table 10 and Table 17

1. Details of how to find the date of marking are given in Application Note, AN1995.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock Frequency for the f ollo wing instructions:

FAST_READ, PP, SE, BE, DP, RES, WREN,

WRDI, RDSR, WRSR D.C. 40 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH(2)

2. tCH + tCL must be greater than or equal to 1/ fC

tCLH Clock High Time 11 ns

tCL(2) tCLL Clock Low Time 11 ns

tCLCH(3)

3. Value guaranteed by characterization, not 100% tested in production.

Clock Rise Time(4) (peak to peak)

4. Expressed as a slew-rate.

0.1 V/ns

tCHCL(3) Clock Fall Time(4) (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relative to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ(3) tDIS Output Disable Time 9 ns

tCLQV tVClock Low to Output Valid 9 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX(3) tLZ HOLD to Output Low-Z 9 ns

tHLQZ(3) tHZ HOLD to Output High-Z 9 ns

tWHSL(5)

5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

Write Protect Setup Time 20 ns

tSHWL(5) Write Protect Hold Time 100 ns

tDP(3) S High to Deep Power-down Mode 3 µs

tRES1(3) S High to Standby Power mode without

Electronic Signature Read 3 or 30(6)

6. It is 30µs in devices produced with the “X” process technology. Details of how to find the process letter on

the device marking are given in the Application note AN1995.

µs

tRES2(3) S High to Standby P o wer mode with Electronic

Signature Read 1.8 or 30(6) µs

M25P40 DC and AC parameters

43/51

Table 20. AC Characteristics (50MHz Operation, Device Grade 6)

50MHz available only in products with Process Technology code X(1)

Test conditions specified in Table 10 and Table 17

1. Details of how to find the date of marking are given in Application Note, AN1995.

Symbol Alt. Parameter Min. Typ. Max. Unit

fCfC

Clock Frequency for the following

instructions: FAST_READ, PP, SE, BE, DP,

RES, WREN, RDID, WRDI, RDSR, WRSR D.C. 50 MHz

fRClock Frequency for READ instructions D.C. 20 MHz

tCH(2)

2. tCH + tCL must be greater than or equal to 1/ fC

tCLH Clock High Time 9 ns

tCL(2) tCLL Clock Low Time 9 ns

tCLCH(3)

3. Value guaranteed by characterization, not 100% tested in production.

Clock Rise Time(4) (peak to peak)

4. Expressed as a slew-rate.

0.1 V/ns

tCHCL(3) Clock Fall Time(4) (peak to peak) 0.1 V/ns

tSLCH tCSS S Active Setup Time (relati ve to C) 5 ns

tCHSL S Not Active Hold Time (relative to C) 5 ns

tDVCH tDSU Data In Setup Time 2 ns

tCHDX tDH Data In Hold Time 5 ns

tCHSH S Active Hold Time (relative to C) 5 ns

tSHCH S Not Active Setup Time (relative to C) 5 ns

tSHSL tCSH S Deselect Time 100 ns

tSHQZ(3) tDIS Output Disable Time 8 ns

tCLQV tVClock Low to Output Valid 8 ns

tCLQX tHO Output Hold Time 0 ns

tHLCH HOLD Setup Time (relative to C) 5 ns

tCHHH HOLD Hold Time (relative to C) 5 ns

tHHCH HOLD Setup Time (relative to C) 5 ns

tCHHL HOLD Hold Time (relative to C) 5 ns

tHHQX(3) tLZ HOLD to Output Low-Z 8 ns

tHLQZ(3) tHZ HOLD to Output High-Z 8 ns

tWHSL(5)

5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

Write Protect Setup Time 20 ns

tSHWL(5) Write Protect Hold Time 100 ns

tDP(3) S High to Deep Power-down Mode 3 µs

tRES1(3) S High to Standby Power mode without

Electronic Signature Read 30 µs

tRES2(3) S High to Standby Power mode with

Electronic Signature Read 30 µs

DC and AC parameters M25P40

44/51

Figure 22. Serial Input Timing

Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1

MSB IN

tDVCH

High Impedance

LSB IN

tSLCH

tCHDX

tCHCL

tCLCH

tSHCH

tSHSL

tCHSHtCHSL

High Impedance

tWHSL tSHWL

AI07439

M25P40 DC and AC parameters

45/51

Figure 24. Hold Timing

Figure 25. Output Timing

AI02032

HOLD

tCHHL

tHLCH

tHHCH

tCHHH

tHHQXtHLQZ

AI01449e

LSB OUT

DADDR.

LSB IN

tSHQZ

tCH

tCL

tQLQH

tQHQL

tCLQX

tCLQV

tCLQX

tCLQV

Package mechanical M25P40

46/51

11 Package mechanical

Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, package

outline

1. Drawing is not to scale.

2. The ‘1’ that appears in the top view of the package shows the position of pin 1.

Table 21. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,

package mechanical data

Symbol millimeters inches

Typ Min Max Typ Min Max

A1.750.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.28 0.48 0.011 0.019

c 0.17 0.23 0.007 0.009

ccc 0.10 0.004

D 4.90 4.80 5.00 0.193 0.189 0.197

E 6.00 5.80 6.20 0.236 0.228 0.244

E1 3.90 3.80 4.00 0.154 0.150 0.157

e1.27– –0.050– –

h 0.25 0.50 0.010 0.020

k0°8°0°8°

L 0.40 1.27 0.016 0.050

L1 1.04 0.041

SO-A

ccc

h x 45˚

0.25 mm

GAUGE PLANE

M25P40 Package mechanical

47/51

Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6x5mm, Package Outline

1. Drawing is not to scale.

2. The circle in the top view of the package indicates the position of pin 1.

Table 22. VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead,

6x5mm, Package Mechanical Data

Symbol millimeters inches

Typ. Min. Max. Typ. Min. Max.

A 0.85 1.00 0.0335 0.0394

A1 0.00 0.05 0.0000 0.0020

A2 0.65 0.0256

A3 0.20 0.0079

b 0.40 0.35 0.48 0.0157 0.0138 0.0189

D6.00 0.2362

D1 5.75 0.2264

D2 3.40 3.20 3.60 0.1339 0.1260 0.1417

E5.00 0.1969

E1 4.75 0.1870

E2 4.00 3.80 4.20 0.1575 0.1496 0.1654

e1.27 0.0500

L 0.60 0.50 0.75 0.0236 0.0197 0.0295

θ12° 12°

VFQFPN-01

eE2

Part numbering M25P40

48/51

12 Part numbering

F o r a list of availab le opt ions (spee d, package, etc.) or for further inf ormation on an y aspect

of this device, ple ase contact your nearest ST Sales Office.

The category of second-Level Inte rconnect is marked on the package and on the inner box

label, in compliance with JEDEC Standar d JESD97. The maximu m ratings relat ed to

soldering conditions are also marked on the inner box label.

Table 23. Ordering Information Scheme

Example: M25P40 – V MN 6 T P /X

Device Type

M25P = Serial Flas h Memory for Code Storage

Device Function

40 = 4 Mbit (512K x 8)

Operating Voltage

V = VCC = 2.7 to 3.6V

Package

MN = SO8 (150 mil width)

MP = VFQFPN8 6x5mm (MLP8)

Device Grade

6 = Industrial temperature range, –40 to 85 °C.

Device tested with standard test flow

3(1) = Device tested with High Reliability Certified Flow(2).

A u tomotive temperature range (–40 to 125 °C)

1. Device grade 3 available in an SO8 ECOPACK® (RoHS compliant) package.

2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment.

The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801. Please ask your

nearest ST sales office for a copy.

Option

blank = Standard Packing

T = Tape and Reel Packing

Plating Technology

P or G = ECOPA CK® (RoHS compliant)

Process(3)

3. The process letter (/X) is specified in the ordering information of Grade 3 devices only.

For Grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on

the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office.

For more information on how to identify products by the Process Identification Letter, please refer to

AN1995: Serial Flash Memory Device Marking.

/X = T7Y

M25P40 Revision history

49/51

13 Revision history

Table 24. Document Revision History

Date Revision Changes

12-Apr-2001 1.0 Document written

25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory

11-Sep-2001 1.2

Changes to te xt: Signal Description/Chip Select; Hold Condition/1st para;

Protection modes; Release from Power-down and Read Electronic

Signature (RES); Power-up

Repositionin g of several tables and illustrations without changing their

contents

Power-up timing illustration; SO8W package removed

Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL

16-Jan-2002 1.3

FAST_READ instruction added. Document revised with new timings , VWI,

ICC3 and clock slew rate. Descriptions of Polling, Hold Condition, Page

Programming, Release for Deep Power-down made more precise. Value

of tW(max) modified.

12-Sep-2002 1.4

Clarification of descriptions of entering Standby Power mode from Deep

Power-down mode, and of terminating an instruction sequence or data-

out sequence.

VFQFPN8 package (MLP8) added. Document promoted to Preliminary

Data.

13-Dec-2002 1.5

Typical Page Program time improved. Deep Power-down current

changed. Write Protect setup and hold times specified, for applications

that switch Write Protect to exit the Hardware Protection mode

immediately before a WRSR, and to enter the Hardware Protection mode

again immediately after.

12-Jun-2003 1.6 Document promoted from Preliminary Data to full Datasheet

24-Nov-2003 2.0

Table of contents, warning about exposed paddle on MLP8, and Pb-free

options added.

40MHz AC Characteristics table included as well as 25MHz. ICC3(max),

tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8

package

12-Mar-2004 3.0 Automotive range added. Soldering temperature information clarified for

RoHS compliant devices

05-Aug-2004 4.0 Device Grade informa tion clarified. Data-rete ntion measurement

temperature corrected. Details of how to find the date of marking added.

03-Jan-2005 5.0 Small text changes. Notes 2 and 3 removed from Table 23: Ordering

Information Scheme.

End timing line of tSHQZ modified in Figure 25: Output Timing.

01-Aug-2005 6.0 Upda ted Page Program (PP) instructions in Page Programming, Page

Program (PP), Instruction Times (Device Grade 6) and Instruction Times

(Device Grade 3).

Revision history M25P40

50/51

24-Oct-2005 7.0

50MHz operation added (see Table 20: AC Characteristics (50MHz

Operation, Device Grade 6)). All packages are ECOPACK®. Blank option

remov ed from under Plating Technology in Table 23: Ordering Information

Scheme. MLP package renamed as VFQFPN, silhouette and package

mechanical drawing updated (see on page 1 and Figure 27: VFQFPN8

(MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead, 6x5mm,

Package Outline.

22-Dec-2005 8.0

Note 2 added below Figure 26 and note 1 added below Figure 27

tRES1 and tRES2 modified in Table 20: AC Characteristics (50MHz

Operation, Device Grade 6).

Read Identification (RDID) added. Titles of Figure 27 and Table 22

corrected.

14-Apr-2006 9

The data contained in Table 11, Table 16 and Table 18 is no longer

preliminary data.

Figure 3: Bus Master and memory devices on the SPI Bus modified and

Note 2 added.

40MHz frequency condition modified for ICC3 in Ta ble 14: DC

Characteristics (Device Grade 3).

Table 16: Instruction Times (Device Grade 3) shows preliminary data.

Condition changed for the Data Retention parameter in Table 11: Data

Retention and Endurance. VWI parameter f or Device Grade 3 added to

Table 8: Power-Up Timing and VWI Threshold.

SO8 package specifications updated (see Figure 26 and Table 21).

/X Process added to Table 23: Ordering Information Scheme.

05-Jun-2006 10

tRES1 and tRES2 parameter timings changed for de vices produced with the

“X” process technology in Table 18 and Table 19.

SO8 Narrow package specifications updated (see Figure 26 and

Table 21).

Table 24. Document Re vision History (continued)

Date Revision Changes

M25P40

51/51

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