K3N3C3000D-D(G)C CMOS MASK ROM
Pin Name Pin Function
A0 - A18 Address Inputs
Q0 - Q7Data Outputs
CE Chip Enable
OE Output Enable
VCC Power(+5V)
VSS Ground
N.C No Connection
4M-Bit (512Kx8) CMOS MASK ROM
The K3N3C3000D-D(G)C is a fully static mask programmable
ROM organized 524,288 x 8 bit. It is fabricated using silicon
gate CMOS process technology.
This device operates with a 5V single power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N3C3000D-DC is packaged in a 32-DIP and the
K3N3C3000D-GC in a 32-SOP.
GENERAL DESCRIPTIONFEATURES
• 524,288x8 bit organization
• Access time : 80ns(Max.)
• Supply voltage : single +5V
• Current consumption
Operating : 50mA(Max.)
Standby : 50µA(Max.)
• Fully static operation
• All inputs and outputs TTL compatible
• Three state outputs
• Package
-. K3N3C3000D-DC : 32-DIP-600
-. K3N3C3000D-GC : 32-SOP-525
A18 X
AND
DECODER
BUFFERS
A0
Y
AND
DECODER
BUFFERS
MEMORY CELL
SENSE AMP.
CONTROL
LOGIC
MATRIX
(524,288x8)
BUFFERS
CE
OE
.
.
.
.
.
.
.
.
Q0Q7
. . .
PIN CONFIGURATION
N.C
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1CE
OE
Q0
Q1
Q4
Q5
Q6
Q7
A9
A10
A11
DIP
K3N3C3000D-D(G)C
FUNCTIONAL BLOCK DIAGRAM
1
2
3
4
5
6
7
8
32
31
9
10
30
29
11
12
28
27
13
14
26
25
15
16
24
23
21
21
20
19
18
17
Q2
VSS
VCC
A18
A17
A14
A13
A8
Q3
&
SOP
A0
K3N3C3000D-D(G)C CMOS MASK ROM
ABSOLUTE MAXIMUM RATINGS
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the
conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Item Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN -0.3 to +7.0 V
Temperature Under Bias TBIAS -10 to +85 °C
Storage Temperature TSTG -55 to +150 °C
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70°C)
Item Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Supply Voltage VSS 000V
MODE SELECTION
CE OE Mode Data Power
HXStandby High-Z Standby
LHOperating High-Z Active
LOperating Dout Active
CAPACITANCE(TA=25°C, f=1.0MHz)
NOTE : Capacitance is periodically sampled and not 100% tested.
Item Symbol Test Conditions Min Max Unit
Output Capacitance COUT VOUT=0V -10 pF
Input Capacitance CIN VIN=0V -10 pF
DC CHARACTERISTICS
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
Parameter Symbol Test Conditions Min Max Unit
Operating Current ICC Cycle=5MHz, all outputs open
CE=OE=VIL, VIN=0.6V to 2.4V (AC Test Condition) -50 mA
Standby Current(TTL) ISB1 CE=VIH, all outputs open -1mA
Standby Current(CMOS) ISB2 CE=VCC, all outputs open -50 µA
Input Leakage Current ILI VIN=0 to VCC -10 µA
Output Leakage Current ILO VOUT=0 to VCC -10 µA
Input High Voltage, All Inputs VIH 2.2 VCC+0.3 V
Input Low Voltage, All Inputs VIL -0.3 0.8 V
Output High Voltage Level VOH IOH=-400µA2.4 -V
Output Low Voltage Level VOL IOL=2.1mA -0.4 V
K3N3C3000D-D(G)C CMOS MASK ROM
TEST CONDITIONS
Item Value
Input Pulse Levels 0.6V to 2.4V
Input Rise and Fall Times 10ns
Input and Output timing Levels 0.8V and 2.0V
Output Loads 1 TTL Gate and CL=100pF
AC CHARACTERISTICS(TA=0°C to +70°C, VCC=5V±10%, unless otherwise noted.)
READ CYCLE
Item Symbol K3N3C3D-D(G)C08 K3N3C3D-D(G)C10 K3N3C3D-D(G)C12 Unit
Min Max Min Max Min Max
Read Cycle Time tRC 80 100 120 ns
Chip Enable Access Time tACE 80 100 120 ns
Address Access Time tAA 80 100 120 ns
Output Enable Access Time tOE 40 50 60 ns
Output or Chip Disable to
Output High-Z tDF 20 20 20 ns
Output Hold from Address Change tOH 0 0 0 ns
TIMING DIAGRAM
READ
ADD
CE
OE
DOUT
ADD1 ADD2
VALID DATA VALID DATA
tOH
tDF(Note)
tRC
tACE
tOE tAA
NOTE : tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or
VOL level.
