Rev. 4807A–AUDR–05/04
Features
•On-chip Control Functions are Available for System Gain Adjust
(dB Linear versus DC Current)
•Low Noise LO Design
•ESD Protected
Benefits
•All Front-end Functions of a High-performance FM Receiver Except the RF
Preamplifier are Integrated
•Improved Dynamic Range by High Current Double-balanced Mixer Design and a New
AGC Conception with 3 Loops On-chip
•Improved Blocking and Intermod Behavior Due to a Unique “Interference” Sensor
Controlling the AGC
•Easy Cascading of 3 IF Filters (Ceramic) Enabled by Two On-chip IF Preamplifiers
Description
The IC U4065B is a bipolar integrated FM front-end circuit. It contains a mixer, an
oscillator, two IF preamplifiers and an unique interference sensor. The device is
designed for high-performance car radio and home receiver applications.
FM Receiver IC
U4065B
2U4065B
4807A–AUDR–05/04
Figure 1. Block Diagram
VS
22 111 9810 6
17
13
35
7
421
1819
16
14
23
24
+
IF BPF IF BPF
IF BPF
IF output
IF 2
IF 1
IF gain adjust
VS
Voltage
regulator
IF BPF
ANT
Interference
mixer
Mixer
RF
PIN
ATT
RF tank
VTUNE
RF tank
Local
oscillator
IF tank
LO output
VREF = 4 V
20
2
LO tank
AGC adjust
AGC level
VS
12
NC
(wide band)
AGC
wide band
and IF
IF and
detector
Interference
VS
3
U4065B
4807A–AUDR–05/04
Pin Configuration
Figure 2. Pinning SO24
1
2
3
4
5
6
7
8
10
9
23
18
17
16
14
15
13
12
11
24
21
22
19
20
VS
IF1OUT
GND2
IMIFIN
AGCOUT
IMMIXOUT
GAINIF1
IF2IN
NC
IF2OUT
GND1
LOBUFF
MIXOUT2
MIXOUT1
VREF
MIXIN2
MIXIN1
GND3
IF1IN
GND4
AGCWB
GND5
LOE
LOB
4U4065B
4807A–AUDR–05/04
Pin Description
Pin Symbol Function
1 LOBUFF Buffered local oscillator output
2 GND1 Ground of the second IF amplifier
3 IF2OUT Output of the second IF amplifier
4 GAINIF1 Gain control of the first IF amplifier
5 IF2IN Input of the second IF amplifier
6 VS Supply voltage
7 IF1OUT Output of the first IF amplifier
8 GND2 Ground
9 IMIFIN Input of the amplifier for the IM sensor
10 AGCOUT Output of the automatic gain control
11 IMMIXOUT Output of the intermodulation mixer
12 NC Not connected
13 AGCWB Threshold adjustment of the wideband AGC
14 GND3 Mixer ground
15 MIXIN1 Input 1 of the double-balanced mixer
16 MIXIN2 Input 2 of the double-balanced mixer
17 VREF Reference voltage output
18 MIXOUT1 Mixer output 1
19 MIXOUT2 Mixer output 2
20 GND4 Ground of the first IF amplifier
21 IF1IN Input of the first IF amplifier
22 GND5 Oscillator ground
23 LOE Local oscillator (emitter)
24 LOB Local oscillator (base)
5
U4065B
4807A–AUDR–05/04
LOBUFF Figure 3. Buffered Local Oscillator Output
The buffered local oscillator used for output, drives the FM input of the PLL circuit (for
example, U428xBM family). The typical parallel output resistance at 100 MHz is 70 Ω,
the parallel output capacitance is about 10 pF. When using an external load of 500 Ω/10
pF, the oscillator swing is about 100 mV. The second harmonic of the oscillator fre-
quency is less than -15 dBc.
GND1 Figure 4. Ground of the Second IF Amplifier
There is no internal connection to the other ground pins.
IF2OUT Figure 5. Output of the Second IF Amplifier
The parallel output capacitance to ground is about 7 pF. The external load resistance
must be connected to VS. The DC current into the pin is typically 3 mA.
Note: The supply voltage VS has to be protected against IF distortion.
ESD
50
23
1
+
1 V
ESD
8
2
ESD
3
VS
VREF
6U4065B
4807A–AUDR–05/04
GAINIF1 Figure 6. Gain Control of the First IF Amplifier
The gain of the first IF amplifier can be adjusted by a resistor to ground. This is useful,
for example, to compensate for the insertion loss tolerances of the ceramic BPFs. It
must be ensured that the output current of the pin does not exceed 150 µA in any case.
Linear increasing in the current out of GAINIF1 results in a linear dB increase of the gain
(0.15 dB/µA).
I4 = 0, thus, G = Gmin = 2 dB
I4 = 140 µA, thus, G = Gmax = 22 dB
IF2IN Figure 7. Input of the Second IF Amplifier
The parallel input resistance is 330 Ω. The parallel input capacitance is about 12 pF. No
DC current is allowed. To avoid overload of this stage, an internal detector watches the
input level and causes current at the AGCOUT pin.
2 kΩ
4ESD
17 VREF
ESD
5
VREF
7
U4065B
4807A–AUDR–05/04
IF1OUT Figure 8. Output of the First IF Amplifier
The parallel output resistance is 330 Ω which allows the use of standard ceramic BPF.
The parallel output capacitance is about 7 pF. The DC voltage at the pin is 0.5 V less
than VS.
IMIFIN Figure 9. Input of the IF Amplifier for the IM Sensor
The parallel input resistance is 330 Ω. The amplifier is extremely sensitive to AC signals.
An IF signal with a few hundred µV at this pin will cause current at the AGC output.
Therefore, attention needs to be paid when connecting the standard ceramic filter
between IMOUT and this pin. The reference point of the filter has to be free of any AC
signal, no DC current shall appear at this pin.
330
VS
ESD
7
ESD
9
8U4065B
4807A–AUDR–05/04
AGCOUT Figure 10. Output of the Automatic Gain Control
The AGC output is an open collector output. The current of the pin diode is this current
multiplied by the current gain of the external PNP transistor. The DC voltage at the pin
may vary from 2 V to VS, therefore, this pin can easily be used as an indicator of the
AGC regulation state.
IMMIXOUT Figure 11. Output of the Intermodulation Mixer
The parallel output resistance is 330 Ω which allows the use of standard ceramic BPF
without any further matching network. It must be ensured that the ground pin of the filter
is free of AC signals.
AGCWB Figure 12. Threshold Adjustment of the Wideband AGC
The threshold of the wideband AGC can be adjusted by an external resistor to ground.
The setting range is 10 dB. For minimum blocking, this pin is connected to ground. To
set the threshold to lower levels, the resistance should have a value of up to a few hun-
dred kΩ.
10
1k
1 V
ESD
11
ESD
300
1 V
VS
35k
32k
ESD
13
VREF
9
U4065B
4807A–AUDR–05/04
MIXIN1 Figure 13. Input 1 of the Double-balanced Mixer
The parallel input resistance is 1.2 kΩ. The parallel input capacitance is about 9 pF.
When using the mixer in an unbalanced way, this pin needs to be grounded for RF sig-
nals by an external capacitance of a few nF. DC current is not allowed.
MIXIN2 Figure 14. Input 2 of the Double-balanced Mixer
The parallel input resistance is 1.6 kΩ. The parallel input capacitance is about 7 pF. The
double sideband noise figure of the unbalanced mixer is about 7 dB. If using the mixer in
balanced mode, the noise figure will be reduced by about 0.8 dB.
VREF Figure 15. Reference Voltage Output
The internal temperature-compensated reference voltage is 3.9 V and it is used as bias
voltage for most blocks. Therefore, the electrical characteristics of the U4065B are
mainly independent of the supply voltage. The internal output resistance of the refer-
ence voltage is less than 10 Ω. To avoid internal coupling across this pin, external
capacitors are required. The maximum output current is IREF = 5 mA.
15
ESD
2.5k
VREF
16
ESD
2.5k
VREF
17
ESD
4.6 V
200
VS
10 U4065B
4807A–AUDR–05/04
MIXOUT1, MIXOUT2 Figure 16. Mixer Output 1, 2
The mixer output is an open collector of a bipolar transistor. The minimum voltage at
these pins is 5 V (VS - voltage swing). The DC current into these pins is typically 9 mA.
Good LO and RF suppression at the mixer output can be achieved by symmetrical load
conditions at the pins MIXOUT1 and MIXOUT2.
IF1IN Figure 17. Input of the First IF Amplifier
The typical input resistance is 330 Ω. The DC voltage is almost identical to the reference
voltage. DC current must be avoided at this pin.
19
18 ESD
330
21
ESD
VREF
11
U4065B
4807A–AUDR–05/04
LOE Figure 18. Emitter of the Local Oscillator
An external capacitor is connected between LOE and ground. The ground pin of this
capacitor must be connected to pin GND5, the chip-internal ground of the local
oscillator.
LOB Figure 19. Base of the Local Oscillator
The tank of the local oscillator is connected at pin LOB. The ground pin of this tank
needs to be connected to pin GND5, the chip-internal ground of the local oscillator’s
pin 24. The resonant resistance of the tank should be about 250 Ω. Minimum Q of the
unloaded tank is 50.
ESD
23
ESD
24
12 U4065B
4807A–AUDR–05/04
Functional Description
The U4065B FM-frontend IC is the dedicated solution for high-end car radios. A new
design philosophy enables to build up tuners with superior behavior. This philosophy is
based on the fact that the sensitivity of state of the art designs is at the physical border
and cannot be enhanced any more. On the other hand, the spectral power density in the
FM-band increases. An improvement of reception can only be achieved by increasing
the dynamic range of the receiver. This description is to give the designer an introduc-
tion to get familiar with this new product and its philosophy.
The Signal Path The U4065B offers the complete signal path of an FM-frontend IC including a highly lin-
ear mixer and two IF preamplifiers. The mixer is a double-balanced, high-current Gilbert
Cell. A high transit frequency of the internal transistors enables the use of the emitter
grounded circuit with its favorable noise behavior. The full balanced output offers LO
carrier reduction.
The first IF preamplifier has a dB-linear gain adjustment by DC means. Thus, different
ceramic filter losses can be compensated and the overall tuner gain can be adapted to
the individual requirements. The low noise design suppresses post stage noise in the
signal path. Input and output resistance is 330 Ω to support standard ceramic filters. This
is achieved without feedback, which would cause different input impedances when vary-
ing the output impedance.
The second IF preamplifier enables the use of three ceramic filters with real 330 Ω input-
and output termination. Feedthrough of signals is kept low. The high level of output com-
pression is necessary to keep up a high dynamic range.
Beneath the signal path the local oscillator part and the AGC signal generation can be
found on chip. The local oscillator uses the collector grounded colpitts type. A low phase
noise is achieved with this access. A mutual coupling in the oscillator coil is not
necessary.
The AGC Concept Special care was taken to design a unique AGC concept. It offers 3 AGC loops for differ-
ent kinds of reception conditions. The most important loop is the interference sensor
part.
In today’s high-end car radios, the FM AGC is state of the art. It is necessary to reduce
the influence of 3rd and higher order intermodulation to sustain reception in the pres-
ence of strong signals in the band. On one hand, it makes sense to reduce the desired
signal level by AGC as few as possible to keep up stereo reception, on the other hand
two or more strong out-of-channel signals may interfere and generate an intermodula-
tion signal on the desired frequency. By introducing input attenuation, the level of the
intermod signal decreases by a higher order, whereas the level of the desired signal
shows only a linear dependency on the input attenuation. Therefore, input attenuation
by pin diodes may keep up reception in the presence of strong signals.
The standard solution to generate the pin diode current is to pick up the RF-signal in
front of the mixer. Because the bandwidth at that point is about 1.5 MHz, this is called
wideband AGC. The threshold of AGC start is a critical parameter. A low threshold does
not allow any intermodulation but has the disadvantage of blocking if there is only one
strong station on the band or if the intermod signals do not cover the desired channel. A
higher AGC threshold may tolerate a certain ground floor of intermodulation. This avoids
blocking, but it has the disadvantage, that no reception is possible, if the interfering sig-
nals generate an intermod signal inside the desired channel. This contradiction could
not be overcome in the past.
13
U4065B
4807A–AUDR–05/04
With the new U4065B IC, there is a unique access to this problem. This product has an
interference sensor on chip. Thus, an input signal attenuation is only performed if the
interfering signals do generate an intermod signal inside the desired channel. If they do
not, the existing wideband AGC is active but up to 20 dB higher levels. The optimum
AGC state is always generated.
The Figure 20 to Figure 23 on page 14 illustrate the situation. In Figure 20 the AGC
threshold of a standard tuner is high to avoid blocking. But then the intermod signal sup-
presses the desired signal. The interference sensor of the U4065B ensures that the
AGC threshold is kept low as illustrated in Figure 21 on page 14.
In Figure 22 on page 14 the situation is reversed. The AGC threshold of a standard
tuner is kept low to avoid intermod problems. But then blocking makes the desired sig-
nal level drop below the necessary stereo level. In this case, the higher wideband AGC
level of the U4065B enables perfect stereo reception.
By principle, this interference sensor is an element with a third order characteristic. For
input levels of zero, the output level is zero, too. With increasing input level, the output
level is increased with the power of three, thus preferring intermod signals compared to
linear signals. At the same time, a down conversion to the IF level of 10.7 MHz is per-
formed. If a corresponding 10.7 MHz IF filter selects the intermod signals, only an output
is generated, if an intermod signal inside the 10.7 MHz channel is present.
The circuit blocks interference sensor and IF, and detector build up a second IF chain. In
an FM system, the maximum deviation of a 3rd order intermod signal is the triple max
deviation of the desired signal. Therefore, the ceramic IF BPF between pin 11 and pin 9
may be a large bandwidth type. This is all that is needed for this unique feature.
A further narrow band AGC avoids overriding the second IF amplifier. The amplitude
information of the channel is not compressed in order to maintain multipath detection in
the IF part of the receiver.
Figure 20. A High AGC Threshold Causes the Intermod Signal to Suppress the Desired
Signal
Level
Frequency
Noise floor
Stereo-level
Desired
frequency
Desired
signal
Interfering signals
Intermod signal Intermod signal
14 U4065B
4807A–AUDR–05/04
Figure 21. AGC Threshold Settings
Figure 22. A Low AGC Threshold Causes the Blocking Signal to Suppress the Desired
Signal
Figure 23. The Correct AGC Threshold Enables Optimum Reception
Level
Frequency
Noise floor
Stereo-level
Desired
frequency
Desired
signal
Interfering signals
Intermod
signal Intermod signal
Level
Frequency
Noise floor
Stereo-level
Desired
frequency
Desired
signal
Strong signal
Level
Frequency
Noise floor
Stereo-level
Desired
frequency
Desired
signal
Strong signal
15
U4065B
4807A–AUDR–05/04
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Reference point is ground (pins 2, 8, 14, 20 and 22)
Parameters Symbol Value Unit
Supply voltage VS10 V
Power dissipation at Tamb = 85°C Ptot 470 mW
Junction temperature Tj125 °C
Ambient temperature range Tamb -30 to +85 °C
Storage temperature range Tstg -50 to +125 °C
Electrostatic handling: Human body model (HBM),
all I/O pins tested against the supply pins ±V
ESD 2000 V
Thermal Resistance
Parameters Symbol Value Unit
Thermal resistance RthJA 90 K/W
Electrical Characteristics
VS = 8.0 V, fRF = 98 MHz, fOSC ≅ 108.7 MHz, fIF = fOSC - fRF = 10.7 MHz
Reference point is ground (pins 2, 8, 14, 20, and 22),Tamb = 25°C, unless otherwise specified.
Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
Supply voltage 3, 6, 10, 18, 19 VS7810V
Supply current 3, 6, 10, 18, 19 Itot 37 47 mA
Oscillator (GND5 Has to be Connected to External Oscillator Components)
Oscillator voltage RG24 = 220 Ω, unloaded Q
of LOSC = 70, RL1 =520Ω
24
23
1
VLOB
VLOE
VLOBUFF 70
160
100
90 220
mV
Harmonics 1 -15 dBc
Output resistance 1 RLO 70 Ω
Voltage gain Between 1 and 23 0.9
Mixer (GND3 Has to be Separated from GND1, GND2 and GND4)
Conversion power gain Source impedance:
RG15,16 = 200 Ω
Load impedance:
RL18,19 = 200 Ω
GC5710dB
3rd-order input intercept IP34 6 14 dBm
Conversion transconductance gC8mA/V
Noise figure NFDSB 7dB
Input resistance to ground f = 100 MHz 15 Rignd15 1.2 kΩ
Input capacitance to ground f = 100 MHz 15 Cignd15 9pF
Input resistance to ground f = 100 MHz 16 Rignd16 1.6 kΩ
Input capacitance to ground f = 100 MHz 16 Cignd16 7pF
Input-input resistance Between 15 and 16 Rii15,16 1.6 kΩ
Input-input capacitance Between 15 and 16 Cii15,16 5pF
Output capacitance to GND 18 and 19 Cignd18,19 9pF
16 U4065B
4807A–AUDR–05/04
First IF Preamplifier (IF 1)
Gain control deviation by I44 172024dB
Gain control slope 4 dGIF1/dI40.15 dB/µA
External control current to ground
At Gmin
At Gnom
At Gmax
I4min
I4nom
I4max
0
70
140
µA
Power gain
At I4min
At I4nom
At I4max
Source impedance:
RG21 = 200 Ω,
Load impedance:
RL7 = 200 Ω
Between 21 and 7 Gmin
Gnom
Gmax
-2.5
11
19
2
12
22
2.5
16
28
dB
Noise figure
At Gmax
At Gnom
At Gmin
Between 21 and 7 NFmin
NFnom
NFmax
7
9
15
dB
Temperature coefficient of the gain
at Gnom TKnom +0.045 dB/K
1 dB compression at Gnom 7V
cnom 70 mV
-3 dB cut-off frequency at Gnom 7f
cnom 50 MHz
Input resistance f = 10 MHz 21 RiIF1 270 330 400 Ω
Input capacitance f = 10 MHz 21 CiIF1 5pF
Output resistance f = 10 MHz 7 RoIF1 270 330 400 Ω
Output capacitance f = 10 MHz 7 CoIF1 7pF
Second IF Preamplifier (IF 2)
Power gain
Source impedance:
RG5 = 200 Ω
Load impedance:
RL3 = 200 Ω
Between 5 and 3 GIF2 15 18 19 dB
Noise figure NFIF2 7dB
1 dB compression 3 Vcomp 500 mV
-3 dB cutoff frequency 3 fc50 MHz
Parallel input resistance f = 10 MHz 5 RiIF2 270 330 400 Ω
Parallel input capacitance f = 10 MHz 5 CiIF2 12 pF
Parallel output resistance f = 10 MHz 3 RoIF2 50 kΩ
Parallel output capacitance f = 10 MHz 3 CoIF2 7pF
Voltage Regulator
Regulated voltage 17 Vref 3.7 3.9 4.9 V
Maximum output current 17 Iref 5mA
Internal differential
resistance, dc17/di17 when I17 =0 17 rd17 750Ω
Power supply suppression f = 50 Hz 17 psrr 36 50 dB
Electrical Characteristics (Continued)
VS = 8.0 V, fRF = 98 MHz, fOSC ≅ 108.7 MHz, fIF = fOSC - fRF = 10.7 MHz
Reference point is ground (pins 2, 8, 14, 20, and 22),Tamb = 25°C, unless otherwise specified.
Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
17
U4065B
4807A–AUDR–05/04
Figure 24. Test Circuit
AGC Input Voltage Thresholds (AGC Threshold Current is 10 µA at Pin 10)
IF2 input 5 VthIF2 85 86 92 dBµV
IF and detector 9 VthIFD 42 43 48 dBµV
Mixer input level of
wideband sensor
fiRF = 100 MHz
V at pin 13 = 0 V
I through pin 13 = 0 A
Between 15 and 16 VthWB1
VthWB2
95
85
98
87
100
90
dBµV
dBµV
Electrical Characteristics (Continued)
VS = 8.0 V, fRF = 98 MHz, fOSC ≅ 108.7 MHz, fIF = fOSC - fRF = 10.7 MHz
Reference point is ground (pins 2, 8, 14, 20, and 22),Tamb = 25°C, unless otherwise specified.
Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit
IF 1 IF 2
AGC
block
Mixer
Interference
mixer
amplifier
Local
oscillator
21
50
15
62
4.7n
420 752
3
10 I10
1
5
6
2
VS
VO IF
50
1
5
6
24.7n
4.7n
18
19
14
15
16
24
23
50
VI RF
LOSC
47p
33p
12
470p
RL1
VLOBUFF
fLOBUFF
1
22 11
1
5
6
2VO IF
50
15
6
2
50
VI IF
4.7n
1µ
9
17
6
1
5
62 VS
50
1
5
6
21
5
6
2
Voltage
regulator
4.7n
50
4.7n
50
VI IF
VO IF
VO IF
Gain IF 1
I18,19
8
I6
13
I3
RG15,16
RL18,19
RG21
I4RL7 RG5
RL3
R13
RG9
RG11
RLOBUFF
1
56
2
00
4
50 200
Z/Ω
RF Transformers MCL
Type TMO 4 - 1
VI IF
0 to 140 µA
RG24
VREF = 4 V
IL = 0.7 dB
8p
fOSC
COSC
AGC adjust
(wide band)
I13
4.7n
Interference
VS
VS
18 U4065B
4807A–AUDR–05/04
Local Oscillator
Figure 25. LO Principle Application
Figure 26. Oscillator Swing versus Temperature
24
23
fOSC 33p
47p
VOSC24
Local
oscillator
Oscillator
output
buffer
1VOSC1, fOSC
520
Tamb
RG24
Free running oscillator frequency fOSC ≈ 110 MHz, VOSC24 = 160 mV, RG24 = 220 Ω, QL = 70
0
20
40
60
80
100
120
140
160
180
-30 -10 10 30 50 70 90
Tamb (°C)
V
OSC1
(mV)
19
U4065B
4807A–AUDR–05/04
Mixer fOSC = 110.7 MHz, VOSC24 ≅ 160 mV, fIF = 10.7 MHz
Figure 27. Mixer Principle Application
Figure 28. Mixer Characteristic
Mixer
Local
oscillator
1
56
2
50
1
5
6
2
50
Tamb
IL1
VOIF
18
19
14
15
VS
fOSC
47p
RG24 24
23
fRF1
2 VIRF1
22p
IL2
Conversion power gain GC = 20 log (VOIF/VIRF) + IL1 (dB) + IL2 (dB)
IL1, IL2 insertion loss of the RF transformers
2 VIRF2
fRF2
0
20
40
60
80
100
120
0 20 40 60 80 100 120
VIRF1, VIRF2 (dBµV)
VO
IF
(dBµV)
Conversion characteristic
3rd order
IM-characteristic
20 U4065B
4807A–AUDR–05/04
Figure 29. Conversion Power Gain of the Mixer Stage versus Temperature
Figure 30. Current of the Mixer Stage versus Temperature
0
1
2
3
4
5
6
7
8
-30 -10 10 30 50 70 90
Tamb (°C)
G
C
(dB)
8.0
8.3
8.6
8.9
9.2
9.5
9.8
10.1
10.4
10.7
11.0
-30 -10 10 30 50 70 90
Tamb (°C)
I
18
, I
19
(mA)
21
U4065B
4807A–AUDR–05/04
First IF Preamplifier
Figure 31. First IF Preamplifier Principle Application
Figure 32. Power Gain of the First IF Amplifier versus I4
1
56
2
50 1
5
6
250
IF
21 7
I4
Tamb
IL1
1 : 2 2 : 1
IL2
4
fIF
VOIF
RG21 = 200
VIIF21 VOIF7
V (pin 4)
RL7 = 200
2VIIF
Power gain GIF = 20 log (VOIF/VIIF) + IL1 (dB) + IL2 (dB)
IL1, IL2 = insertion loss of the RF transformers
-5
0
5
10
15
20
25
0 20 40 60 80 100 120 140
I4 (µA)
G
IF
(dB)
T = 90°C
T = -30°C
T = 30 °C
22 U4065B
4807A–AUDR–05/04
Figure 33. Power Gain of the First IF Amplifier versus Frequency
Figure 34. V (Pin 4) versus I4
-10
-5
0
5
10
15
20
25
10 20 30 40 50 60 70 80 90 100
f (MHz)
G
IF1
(dB)
Gmax
Gnom
Gmin
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
0 20 40 60 80 100 120 140
I4(µA)
V
4
(V)
T = -30°C
T = 90°C
T = 30°C
23
U4065B
4807A–AUDR–05/04
Second IF Preamplifier
Figure 35. Second IF Preamplifier Principle Application
Figure 36. Power Gain of the Second IF Amplifier versus Temperature
1
56
2
50 1
5
6
250
IF
Tamb
IL1
1 : 2 2 : 1
IL2
fIF
VOIF
RL3 = 200
330
VS
3VOIF3
VIIF5
RG5 = 200
5
2 VIIF
Power gain GIF = 20 log (VOIF/VIIF) + IL1 (dB) + IL2 (dB)
IL1; IL2 = insertion loss of the RF transformers
15.0
15.5
16.0
16.5
17.0
17.5
18.0
18.5
-30 -20 -10 0 10 20 30 40 50 60 70 80 90
Tamb (°C)
G
IF2
(dB)
24 U4065B
4807A–AUDR–05/04
Figure 37. Power Gain of the Second IF Amplifier versus Frequency
Figure 38. AGC Threshold (110 = 1 µA) of the Second IF Amplifier versus Temperature
Figure 39. AGC Characteristic of the Second IF Amplifier Input
0
2
4
6
8
10
12
14
16
18
20
10 20 30 40 50 60 70 80 90 100
f (MHz)
G
IF2
(dB)
86.0
86.2
86.4
86.6
86.8
87.0
-30 -10 10 30 50 70 90
Tamb (°C)
Threshold (dBµV)
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
80 85 90 95 100 105
VIIF (dBµA)
I
10
(µA)
110 (90°C)/µA
110 (30°C)/µA
110 (-30°C)/µA
25
U4065B
4807A–AUDR–05/04
Interference Sensor (Mixer)
Figure 40. Interference Sensor Principle Application
Test conditions for characteristic VOIF versus VIRF1:
fLO = 100 MHz, fRF1 = 89.3 MHz, VIRF2 = 0, fIF = fLO - fRF1 = 10.7 MHz
Test conditions for 3rd order IM-characteristic VOIF versus VIRF1, VIRF2:
fLO = 100 MHz, fRF1 = 89.4 MHz, fRF2 = 89.5 MHz, fIF = fLO - (2 fRF1 - 1 fRF2) = 10.7 MHz
IL1, IL2 = insertion loss of the RF transformer
Figure 41. Characteristics of the Interference Sensor (Mixer)
Local
oscillator
Interference
mixer
1
56
2
50
1
5
6
2
50
IL1
VOIF
15
VS
11
RL11 = 200
2 VIRF1
fIRF1
fLO
fIF
RG15/16
= 200 IL2
16
IL1 = IL2 = 0.7 dB
2 VIRF2
fIRF2
0
10
20
30
40
50
60
70
80
90
60 65 70 75 80 85 90 95 100
VIRF (dBµV)
VO
IF
(dBµV)
Conversion
characteristic
3rd order
IM-characteristic
26 U4065B
4807A–AUDR–05/04
Figure 42. Conversion Characteristic of the Interference Sensor (Mixer)
Figure 43. Third-order Interference Characteristic of the Interference Sensor (Mixer)
0
10
20
30
40
50
60
70
80
90
100
70 75 80 85 90 95 100 105 110 115
VIRF (dBµV)
VO
IF
(dBµV)
-30°C
30°C
90°C
20
30
40
50
60
70
80
70 75 80 85 90 95 100 105 110 115
VIRF (dBµV)
VO
IF
(dBµV)
-30°C
30°C
90°C
27
U4065B
4807A–AUDR–05/04
Interference Sensor (Amplifier)
Figure 44. Interference Sensor Principle Application
AGC Thresholds Figure 45. AGC Threshold of the Interference IF Amplifier versus Temperature
Figure 46. Wideband AGC Threshold (I10 = 1 µA) versus I13
1
56
2
50
Tamb
IL1
1 : 2
fIF
RG9 = 200
VIIF9 910
VS
I10
IF
IL1 = 0.7 dB
2 VIIF
41.0
41.5
42.0
42.5
43.0
43.5
44.0
44.5
45.0
-30 -20 -10 0 10 20 30 40 50 60 70 80 90
Tamb (°C)
Threshold (dBµV
85
90
95
100
105
0 5 10 15 20 25 30 35 40 45 50 55
I13 (µA)
VI
RF
(dBµV)
88 MHz
108 MHz
98 MHz
28 U4065B
4807A–AUDR–05/04
Figure 47. Wideband AGC Threshold (I10 = 1 µA) versus Temperature
AGC Characteristics Figure 48. AGC Characteristic of the Interference IF and Detector Block
Figure 49. Characteristic of the Wideband AGC (I13 = 0 V)
80
82
84
86
88
90
92
94
96
98
100
-30 -20 -10 0 10 20 30 40 50 60 70 80 90
Tamb (°C)
VI
RF
15/16
U13 = 0 V
I13 = 30 µA
I13 = 0 A
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
35 45 55 65 75 85 95
VIIF (dBµV)
I
10
(µA)
-30°C
30°C
90°C
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
80 85 90 95 100 105 110 115 120
VIIF (dBµV)
I
10
(µA)
-30°C
90°C
30°C
29
U4065B
4807A–AUDR–05/04
Figure 50. Characteristic of the Wideband AGC (V13 = 0 V)
DC Characteristics Figure 51. Supply Current versus Supply Voltage
Figure 52. Reference Voltage versus Temperature
0.01
0.10
1.00
10.00
100.00
1000.00
10000.00
90 95 100 105 110 115 120
VIRF (dBµV)
I
10
(µA)
-30°C
90°C
30°C
0
2
4
6
8
10
12
14
16
18
6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0
VS (V)
I (mA)
I18, I19
I6
I3
3.81
3.82
3.83
3.84
3.85
3.86
3.87
3.88
-30 -20 -10 0 10 20 30 40 50 60 70 80 90
Tamb (°C)
V
REF
(V)
30 U4065B
4807A–AUDR–05/04
Figure 53. Supply Current versus Temperature
Figure 54. Reference Voltage versus I17
0
5
10
15
20
25
30
35
40
-30 -10 10 30 50 70 90
Tamb (°C)
I (mA)
I3 + I6 + I18 + I19
I6
I18, I19
I3
3.75
3.80
3.85
3.90
3.95
4.00
-10-8-6-4-2 0 2 4
I17 (mA)
V
REF
(V)
31
U4065B
4807A–AUDR–05/04
Figure 55. Application Diagram
(Tracking adj.)
R
10
1.5k
R
4
470
C
7
1n
appr. 8 mA
R
7
56kC
12
18p
R
13
120k
R
16
15
R
19
10k
C
21
1n
L
6
OSC
L
5
IF
CF3
R
17
470
D
5
C
18
100p
R
14
160k
D
4
C
13
1n
R
11
56k
C
8
10p
R
6
47k
L
2
2.2 µH
R
5
22
C
10
1p5
Q
1
L
4
C
14
1n
C
16
6.8p
C
17
150n
C
20
22p
C
22
6.8p
C
23
47p
1
24
U4065B
12
13
C
11
10n
D
3
L
3
R
1
22R
2
100
D
2
S391D
R
3
56k
C
5
10n
C
1
2p7
D
1
S392D
C
2
1n
C
3
10nC
4
1nQ2
BC858
CF1CF2
C
19
22n
R
18
330
R
20
22k
R
21
100k
Gain adj.
C
24
1n
CF4
R
15
22
R
9
220
R
12
330kC
15
100n
C
9
470n
C
6
1n
L
1
220nHC
25
27p
75Ω
ANTVAGCVTUN
1.7 - 6.5 V
V
S
= 8.5 VIF OUTLO OUT
1
34
6
BFR93A
1
2
34
6
820
C26
4.7p
32 U4065B
4807A–AUDR–05/04
Part List
Item Description
Q1 BFR93AR (BFR93A)
Q2 BC858
D1 S392D
D2 S391D
D3, D4, D5 BB804
L1 11 turns, 0.35 mm wire, 3 mm diameter (approximately 220 nH)
L2 2.2 mH (high Q type)
L3 TOKO® 7KL-type, # 600ENF-7251x
L4 TOKO 7KL-type, # 291ENS 2341IB
L5 TOKO 7KL-type, # M600BCS-1397N
L6 TOKO 7KL-type, # 291ENS 2054IB
CF1 TOKO type SKM 2 (230 KHZ)
CF2, CF3, CF4 TOKO type SKM 3 (180 KHZ)
33
U4065B
4807A–AUDR–05/04
Package Information
Ordering Information
Extended Type Number Package Remarks
U4065B-AFL SO24 plastic –
U4065B-AFL3 SO24 plastic Taping according to ICE-286-3
technical drawings
according to DIN
specifications
Package SO24
Dimensions in mm 15.55
15.30
2.35
0.4
1.27 13.97
9.15
8.65
0.25
0.10
7.5
7.3
0.25
10.50
10.20
24 13
112
Printed on recycled paper.
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
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4807A–AUDR–05/04
© Atmel Corporation 2004. All rights reserved.
Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries.
TOKO® is a registered trademark of TOKO KABUSHIKI KAISHA TA Toko, Inc.
Other terms and product names may be the trademarks of others.
