1 PS8131A 03/17/98
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Product Features
•PI74ALVCT16260 is designed for low voltage operation
•VCC = 2.3V to 3.6V
•5V tolerant inputs and outputs
•Hysteresis on all inputs
•Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
•Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
•Industrial operation at 40°C to +85°C
•Packages available:
56-pin 240 mil wide plastic TSSOP (A)
56-pin 300 mil wide plastic SSOP (V)
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch
with 3-STATE Outputs
Product Description
Pericom Semiconductor’s PI74ALVCT series of logic circuits are
produced in the Company’s advanced 0.5 micron CMOS technology,
achieving industry leading speed.
The PI74ALVCT16260 is a 12-bit to 24-bit multiplexed D-type latch
designed for 2.3V to 3.6 Vcc operation. It is used in applications
where two separate datapaths must be multiplexed onto, or
demultiplexed from, a single data path.
Typical applications include multiplexing and/or demulti-plexing
address and data information in microprocessor or bus-interface
applications. This device is also useful in memory-interleaving
applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
for address and/or data transfer. The output-enable (OE1B, OE2B,
and OEA) inputs control the bus transceiver functions. The OE1B
and OE2B control signals also allow bank control in the A-to-B
direction.
Address and/or data information can be stored using the internal
storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B)
inputs are used to control data storage. When the latch-enable input
is HIGH, the latch is transparent. When the latch-enable input goes
LOW, the data present at the inputs is latched and remains latched
until the latch-enable input is returned HIGH.
To ensure the high-impedance state during power up or power down,
OE should be tied to Vcc through a pullup resistor, the minimum value
of the resistor is determined by the current-sinking capability of the
driver.
The ALVCT16260 can be driven from either 3.3V or 5V devices
allowing it to be used in mixed 3V/5V systems.
Logic Block Diagram
G1
OE2B
C1
1D
1
B
1
TO 11 OTHER CHANNELS
OE1B
OEA
A1
LE1B
LE2B
LEA1B
LEA2B
SEL
1
1
C1
1D
C1
1D
C1
1D
2
B
1
23
6
28
8
1
29
56
55
30
27
2
2
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PS8131A 03/17/98
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
Pin Name Description
OE Output Enable Input (Active LOW)
SEL Select
LE Latch Enable
A,1B,2B Data Inputs
A,1B,2B 3-State Outputs
GND Ground
VCC Power
Product Pin Description Truth Tables(1)
B to A (OEB = H)
Inputs Output
A
1B 2B SEL LE1B LE2B OEA
HXH H X L H
LXH H X L L
XXH L X L A
0
XH L X H L H
XL L X H L L
XX L X L L A
0
XXX X X H Z
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
25
26
27
28
32
31
30
29
Note:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
Product Pin Configuration
56-PIN
V56
A56
OEA
LE1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
LE2B
SEL
OE2B
LEA2B
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
LEA1B
OE1B
A to B (OEA = H)
stupnIstuptuO
AB1AELB2AELB1EOB2EOB1B2
HH H L L H H
LH H L L L L
HH L L L H 0B2
LH L L L L 0B2
HL H L L 0B1H
LL H L L 0B1L
XL L L L 0B10B2
XX X H H Z Z
XX X L H evitcAZ
XX X H L Z evitcA
XX X L L evitcAevitcA
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
3PS8131A 03/17/98
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Storage Temperature ........................................................... 65°C to +150°C
Ambient Temperature with Power Applied ........................ 40°C to +85°C
Input Voltage Range, VIN ...................................................... 0.5V to VCC +0.5V
Output Voltage Range, VOUT ............................................... 0.5V to VCC +0.5V
DC Input Voltage .................................................................... 0.5V to +5.0V
DC Output Current ............................................................................ 100 mA
Power Dissipation .................................................................................. 1.0W
Note:
Stresses greater than those listed under MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
DC Electrical Characteristics (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%)
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4
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PS8131A 03/17/98
PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
Notes:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. Unused Control Inputs must be held HIGH or LOW to prevent them from floating.
DC Electrical Characteristics-Continued (Over the Operating Range, TA = 40°C to +85°C, VCC = 3.3V ± 10%)
Timing Requirements over Operating Range
Note:
1. Unused control inputs must be held HIGH or LOW to prevent them from floating.
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PI74ALVCT16260
12-Bit To 24-Bit Multiplexed D-Type Latch with 3-State Outputs
5PS8131A 03/17/98
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Switching Characteristics Over Operating Range(1)
Notes:
1. See test circuit and wave forms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25ºC
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