a CDMA Power Management System
Preliminary Technical Data ADP3500
FEATURES
Handles all CDMA Baseband and RF/IF Power Management
Functions
LDOs Optimized for Specific CDMA Subsystems
Four Backup LDOs for Stand-By mode operation
Four Li-Ion Battery Charge Modes
5mA Pre Charge
Low Current Charge
Full Current Charge
Regulator mode (no current limit)
Ambient Temperature: -30 °
°°
°Cto+85°
°°
°C
64pin 7x7 LQFP package
APPLICATIONS
CDMA/CDMA2000/PCS Handsets
GENERAL DESCRIPTION
The ADP3500 is a multifunction power system chip optimized
for CDMA cell phone power management. It contains 15 LDOs.
Sophisticated controls are available for power up during battery
charging, keypad interface, GPIO/INT function and RTC
function. The battery charger has four modes as Pre-charge, Low
Current Charge, Full Current Charge, and Regulator modes, and
is designed for Li-Ion/Li-Polymer batteries.
REV. PrP 2/6/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or apatent rights of Analog Devices.
RESET OUTPUT
RESET
32KHz OUTPUT
CONTROL
POWER ON
KEYPAD I/F
GPIO
SERIAL I/F
DELAY 10mS
INTERRUPT
CONTROL
LDO CONTROL
BATTERY
CHARGER
REFERENCE
LDO1 to 11
VOLTAGE
DETECTOR
ANALOG
BLOCK
RTC COUNTER
STAY-ALIVE
TIMER
LOGIC
BLOCK
ADP3500
Figure 1. Functional Block Diagram
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-87ß3 ANALOG DEVICES, INC., 2002
PRELIMINARY TECHNICAL DATA
REV.PrP 2/6/02 - 2 -
ADP3500 - SPECIFICATIONS
MAIN FUNCTIONS
TA=-30 to +85°C, CVBAT=1µF MLCC, VBAT=3.6V unless otherwise noted. See Table 2 for COUT.
Parameter Symbol Conditions Min Typ Max Units
SHUTDOWN GND CURRENT
Power OFF IGND LDO3b : ON, connect to RTCV
through Schottky diode.
RTC/32K OSC : Active
AllotherLDOs:OFF
All logic inputs : VBAT or GND
MVBAT: OFF
25 40 µA
OPERATING GND CURRENT
Stand-by mode operation (light load)
Stand-by mode operation (Mid-load)
Active operation
IGND LDO1b, 2b, 3b, 6b: ON
Io=1mA for LDO1b & 3b
Io=300µA for LDO2b & 6b
AllotherLDOs:OFF
RTC/32K OSC: Active
MVBAT: OFF
All logic output: no load
LDO1, 2, 3, 6, all Sub-LDO: ON,
Io=70% load
AllotherLDOs:OFF
RTC/32K OSC: Active
MVBAT: ON
All logic outputs: no load
LDO5: OFF
All other LDOs: ON, 70% load
RTC/32K OSC: Active
All logic outputs: no load
MVBAT: ON
60
275
650
125 µA
µA
µA
Thermal Shutdown Threshold 160 °C
Thermal Shutdown Hysteresis 35 °C
Operational Temperature range Tope -30 +85 °C
Adapter Voltage range (recommendation) VADP 5.5 12 V
VBAT Voltage range VBAT 3.3 5.5 V
LDO SPECIFICATIONS
TA=25°C, CVBAT=1µF MLCC, VBAT = Vout+1V, NRCAP=0.1µF. See Table 2 for COUT.
Baseband VDD Main-LDO (LDO #1a)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE VLDO#1 Io = 1 to 150 mA
Ta= -30 to +85°C2.81 2.90 2.99 V
OUTPUT CAPACITOR REQUIRED FOR
STABILITY CLDO#1 2.2 µF
DROPOUT VOLTAGE VDO Io = 150 mA 200 mV
Start-up time from shutdown 250 µS
GND Current ILDO#1 Io = 150 mA 50 µA
Baseband VDD Sub-LDO (LDO #1b)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE VLDO#1b Io = 1mA
Ta= -30 to +85°C2.8 2.87 3.0 V
GND Current ILDO#1b 10 µA
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 3 -
Baseband AVDD Main-LDO (LDO #2a)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT Voltage VLDO#2 16 steps, 20mV/step, Ta= 25C,
Io=50mA
Code : 1000
Code : 0111 2.30
2.60 2.36
2.66 2.43
2.74 V
V
OUTPUT default voltage VLDO#2 Io=50mA,Ta=25°C2.46 2.52 2.6 V
OUTPUT Voltage VLDO#2 16 steps, 20mV/step, Io=50mA, Ta=
-30to+85°C
Code : 1000
Code : 0111 2.29
2.57 2.36
2.66 2.47
2.81 V
V
OUTPUT default voltage VLDO#2 Io=50mA,Ta=-30to+85°C2.42 2.52 2.66 V
OUTPUT CAPACITOR REQUIRED FOR
STABILITY CLDO#2 1µF
DROPOUT VOLTAGE VDO Io = 50 mA 210 mV
RIPPLE REJECTION f = 1KHz 50 dB
OUTPUT NOISE VOLTAGE VNOISE f = 100 Hz to 100 kHz 120 µVRMS
Start-up time from shutdown 250 µS
GND Current ILDO#2 Io = 50 mA 50 µA
Baseband AVDD Sub-LDO (LDO #2b)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT Voltage VLDO#2b Io = 300 µA, VLDO#2a=2.6V
Ta= -30 to +85°C2.50 2.70 V
GND Current ILDO#2b 5µA
REFO switch
Parameter Symbol Conditions Min Typ Max Units
On resistance RON Ta= -30~+85°C, Io=500µA50 130 Ω
Off leak ILEAK LDO2: ON, Switch: OFF 0.01 1 µA
Coin Cell Main-LDO (LDO #3a)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE VLDO#3 Io = 1 to 50 mA
Ta= -30 to +85°C2.85 3.0 3.09 V
Dropout Voltage VDO Io= 50 mA 140 mV
OUTPUT CAPACITOR REQUIRED FOR
STABILITY CLDO#3 1µF
Start-up time from shutdown 250 µS
GND Current ILDO#3 Io = 50 mA 50 µA
Coin Cell Sub-LDO (LDO #3b)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE VLDO#3b Io=1mA
Ta= -30 to +85°C2.85 2.97 3.15 V
GND Current ILDO#3b 10 µA
Audio LDO (LDO #4)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE VLDO#4 Io = 1 to 180 mA
Ta=-30to+85°C2.81 2.90 2.99 V
OUTPUT CAPACITOR REQUIRED FOR
STABILITY CLDO#4 2.2 µF
Dropout Voltage VDO Io = 180 mA 200 mV
RIPPLE REJECTION f = 1KHz 50 dB
OUTPUT NOISE VOLTAGE VNOISE f = 100 Hz to 10 kHz 50 µVRMS
Start-up time from shutdown 250 µS
GND Current ILDO#4 Io = 180 mA 50 µA
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 4 -
Vibrator LDO (LDO #5)
Parameter Symbol Conditions Min Typ Max Units
Output Voltage VLDO#5 Io = 1 to 150 mA
Ta= -30 to +85°C2.75 2.9 3.05 V
Dropout Voltage VDO Io = 150mA 200 mV
Output capacitor required for stability CLDO#5 2.2 µF
GND Current ILDO#5 Io = 150 mA 50 µA
Baseband Core Main-LDO (LDO #6a)
Parameter Symbol Conditions Min Typ Max Units
Output Voltage VLDO#6 Io = 1 to 50 mA
Ta= -30 to +85°C2.52 2.60 2.68 V
Output capacitor required for stability CLDO#6 1µF
Dropout Voltage VDO Io = 50 mA 160 mV
Start-up time from shutdown 250 µS
GND Current ILDO#6 Io = 50 mA 50 µA
Baseband Core Sub-LDO (LDO #6b)
Parameter Symbol Conditions Min Typ Max Units
OUTPUT VOLTAGE VLDO#6b Io = 300 µA
Ta= -30 to +85°C2.5 2.57 2.7 V
GND Current ILDO#6b 5µA
RF Rx1 LDO (LDO #7)
Parameter Symbol Conditions Min Typ Max Units
Output voltage VLDO#7 Io = 1 to 100 mA
Ta= -30 to +85°C2.81 2.9 2.99 V
Output capacitor required for stability CLDO#7 1.5 µF
Dropout voltage VDO Io = 100 mA 200 mV
Ripple rejection f = 1KHz 50 dB
Output noise voltage VNOISE f = 100 Hz to 100KHz 40 µVRMS
Start-up time from shutdown 250 µS
GND Current ILDO#7 Io=100mA 50 µA
RF Tx LDO (LDO #8)
Parameter Symbol Conditions Min Typ Max Units
Output voltage VLDO#8 Io = 1 to 150 mA
Ta= -30 to +85°C2.81 2.9 2.99 V
Output capacitor required for stability CLDO#8 2.2 µF
Dropout voltage VDO Io = 150mA 200 mV
Ripple Rejection f = 1KHz 50 dB
Output noise voltage VNOISE f = 100 Hz to 100KHz 40 µVRMS
Start-up time from shutdown 250 µS
GND Current ILDO#8 Io=150mA 50 µA
RF Rx 2 LDO (LDO #9)
Parameter Symbol Conditions Min Typ Max Units
Output voltage VLDO#9 Io = 1 to 50 mA
Ta= -30 to +85°C2.81 2.9 2.99 V
Output capacitor required for stability CLDO#9 1µF
Dropout voltage VDO Io = 50mA 150 mV
Ripple Rejection f = 1KHz 50 dB
Output noise voltage VNOISE f = 100 Hz to 100KHz 40 µVRMS
Start-up time from shutdown 250 µS
GND Current ILDO#9 Io=50mA 50 µA
RF Optional LDO (LDO #10)
Parameter Symbol Conditions Min Typ Max Units
Output voltage VLDO#10 Io= 1 to 50 mA
Ta= -30 to +85°C2.81 2.9 2.99 V
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 5 -
Output capacitor required for stability CLDO#10 1µF
Dropout voltage VDO Io = 50mA 150 mV
Ripple rejection f = 1KHz 50 dB
Output noise voltage VNOISE f = 100 Hz to 100KHz 40 µVRMS
Start-up Time from Shutdown 250 µS
GND Current ILDO#10 Io=50mA 50 µA
Optional LDO (LDO #11)
Parameter Symbol Conditions Min Typ Max Units
Output voltage VLDO#11 Io = 1 to 100 mA
Ta= -30 to +85°C1.42 1.5 1.58 V
Output capacitor required for stability CLDO#11 2.2 µF
Ripple rejection f = 1KHz 50 dB
Output noise voltage VNOISE f = 100 Hz to 100KHz 50 µVRMS
Start-up Time from Shutdown 250 µS
GND Current ILDO#11 Io=150mA 50 µA
Voltage Detector for LDO1 and LDO6
Parameter Symbol Conditions Min Typ Max Units
LDO1 detect voltage VDET1 Ta= -30 to +85°C2.7 2.72 V
LDO1 release voltage VDET1 Ta= -30 to +85°C2.77 VLDO1
-NOM
V
LDO1 Hysteresis VHYS1 Ta= -30 to +85°C35 52 85 mV
LDO6 detect voltage VDET6 Ta= -30 to +85°C2.3 2.33 V
LDO6 release voltage VDET6 Ta= -30 to +85°C2.40 VLDO6
-NOM
V
LDO6 Hysteresis VHYS6 Ta= -30 to +85°C40 60 100 mV
BATTERY VOLTAGE DIVIDER: MVBAT
TA=-30 to 85°C, CVBAT=10µF MLCC, CAdapter=1µFMLCCunless otherwise noted
Parameter Symbol Conditions Min Typ Max Units
MVBAT Output voltage
5 – bit programmable VMVBAT
VBAT=4.35V, MVEN = 1
code 10000
code 01111 2.484
2.673 2.508
2.697 2.533
2.727 V/V
V/V
MVBAT Output voltage step Vstep VBAT=4.35V, MVEN = 1 6 mV/lsb
Output drive current capability Iout 1 2 mA
MVBAT Load Regulation ∆ΜVBAT 0 < Iout < 100 µA35mV
MVBAT Output Voltage Step VBAT = 4.35 V, MVEN = 1 6 mV
Operating Battery Current VBAT = 4.35 V, MVEN = 1 65 85 µA
Shutdown Current VBAT = 4.35 V, MVEN = 0 1 µA
BATTERY CHARGER
TA=-30 to 85°C, CVBAT =10µF MLCC, CAdapter =1µF MLCC, 4.0V ≤ADAPTER ≤12V unless otherwise noted
Parameter Symbol Conditions Min Typ Max Units
Charger Control Voltage Range
2 – bit programmable VBAT
SENSE Ta= 25 °C,
VR_SENSE = 6mV & 115mV,
5.5V ≤ADAPTER ≤12V (note 1)
code 00 (default)
code 01
code 10
code 11
3.926
4.150
4.170
4.190
3.980
4.190
4.210
4.230
4.034
4.230
4.250
4.270
V
V
V
V
Charger Control Voltage Range
2 – bit programmable VBAT
SENSE Ta= -20 to 55°C,
VR_SENSE = 6mV & 115mV,
5.5V ≤ADAPTER ≤12V (note 1)
code 00 (default)
code 01
code 10
code 11
3.905
4.130
4.146
4.166
3.980
4.190
4.210
4.230
4.065
4.250
4.278
4.300
V
V
V
V
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 6 -
Charger Detect On Threshold ADAPT
ER-
VBAT
110 165 225 mV
Charger Detect Off Threshold ADAPT
ER-
VBAT
52350mV
Charger Supply Current IADAPTER ADAPTER=5V, VBAT=4.3V 2 mA
Current Limit Threshold
High Current Limit
(Full charge current enabled)
Low Current Limit
(Full charge current disabled)
ADAPT
ER-VISNS
ADAPTER=5V
VBAT=3.6V
VBAT=3.0 V
135
40
160
55
185
70
mV
mV
Pre-Charge Current Source VBAT ≤DDLO 357mA
Base Pin Drive Current Note 2. 15 28 mA
Deep Discharge Lock-Out (Releasing voltage) DDLO VBAT<DDLO, Ta=25C, 5mA Pre-
charge, VBAT ramping up 2.675 2.78 V
Deep Discharge Lock-Out Hysteresis 200 mV
ISENSE Bias Current IISNS VISNS=5V 1 µA
BATID pull-up resistor to ADAPTER RBATID 70 100 130 KΩ
Minimum Load for Stability ILBATID=H. Note 3. 10 mA
Note 1: Overhead includes external components, including sense resistor, PNP and isolation diode.
2: DDLO hysteresis is dependent upon DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at
maximum at the same time.
3: Guaranteed but not tested.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 7 -
LOGICS
DC Specifications
TA=25°C, CVBAT=1µF MLCC, VBAT = 3.6 V
Parameter Symbol Conditions Min Typ Max Units
CS, CLKIN, RESETIN-, TCXO_ON, SLEEP-,
KEYPADROW (Internal 10KΩpull-up)
Input High Voltage
Input Low Voltage
Hysteresis
GPIO, DATA
Input High Voltage
Input Low Voltage
Hysteresis
Output High Voltage
Output Low Voltage
INT-
Output High Voltage
Output Low Voltage
BLIGHT (Open Drain Output)
Output Low Voltage
KEYPADCOL (Open Drain Output)
Output Low Voltage
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
VOL
VOL
IOH=400µA
IOL=-1.8mA
IOH=400µA
IOL=-1.8mA
IOL=-100mA
IOL=-1.8mA
2.25
2.25
2.69
2.69
470
470
0.5
0.5
0.28
0.28
0.4
0.15
V
V
mV
V
V
V
mV
V
V
V
V
V
V
PWRONKEY-, OPT1 (Internal 140KΩPull-up)
Input High Voltage
Input Low Voltage
Hysteresis
OPT2- (Input/Open Drain Output)
Input High Voltage
Input Low Voltage
Hysteresis
Output Low Voltage
OPT3
Input High Voltage
Input Low Voltage
Hysteresis
VIH
VIL
Vhys
VIH
VIL
Vhys
VOL
VIH
VIL
Vhys
IOL=-1.8mA
0.8xVBAT
0.8xVBAT
0.7xVBAT
950
950
300
0.2xVBAT
0.2xVBAT
0.1xVBAT
0.2xVBAT
V
V
mV
V
V
mV
V
V
V
mV
32KOUT
Output High Voltage
Output Low Voltage VOH
VOL IOH=400µA
IOL=-1.8mA 0.9xRTCV 0.1xRTCV V
V
RESET+ (Open Drain Output)
Output Low Voltage
OFF Leak
RSTDELAY-, RESETOUT- (Open Drain Output)
Output Low Voltage
VOL
OFFLEAK
VOL
IOL=-1.8mA
IOL=-1.8mA
0.005 0.1xRTCV
1
0.1xRTCV
V
µA
V
BATID (Internal 100KΩpull-up)
Input High Voltage
Input Low Voltage
Hysteresis
VIH
VIL VADP=5 to 12V 0.8xVADP
0.16 x
VADP
0.2xVADP V
V
V
Supply Current of RTCV IOSC RTCV=3V,
VBAT=0V
All logic: No load.
1µA
VADP: Adapter voltage
AC Specifications
All specs include temperature unless otherwise noted
Parameter Symbol Conditions Min Typ Max Units
Operational Supply Range RTCV 2 3.1* V
Oscillator Frequency FCLK 32.768 KHz
Start-up Time (note) tSTART RTCV=0V to 3V 100 200 mS
Frequency deviation fDEV RTCV=2 to 3V TBD
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 8 -
Frequency Jitter
Cycle to Cycle
>100cycles
fJITTER/S
EC RTCV=3V, TA=25°C40*
50* nS
nS
Long term Drift RTCV=3V, 3 minutes 10* ppm
SERIAL INTERFACE
Parameter Min. Typ. Max Units Test Condition/Comments
tCKS 50 nS CLK set-up time
tCSS 50 nS CS set-up time
tCKH 100 nS CLK “High” Duration
tCKL 100 nS CLK “Low” Duration
tCSH 100 nS CS hold time
tCSR 62 µSCS recovery time
tDS 50 nS Input data set-up time
tDH 40 nS Input data hold time
tRD 50 nS Data output delay time
tRZ 50 nS Data output floating time
tCSZ 50 nS Data output floating time after CS goes low.
Note: These parameters are not tested.
ABSOLUTE MAXIMUM RATINGS
Voltage on ADAPTER pin to GND ……………………………..... -0.3, 15Vmax
Voltage on VBAT pin to GND …………………………………… -0.3, 7Vmax
Voltage on Pin 6-13, 21-28 to GND ……………………………… -0.3, VLDO1+0.3Vmax
Voltage on Pin 1, 62-64 ………………………………………….. - 0.3, VBAT+0.3V max
Voltage on Pin 20, 32 …………………………………………….. - 0.3, VRTCV+0.3V max
Voltage on Pin 60, 61 ……………………………………………... - 0.3, VADAPTER+0.3V max
Voltage on Pin 2-5, 14, 30, 31, 33 …………………………………. - 0.3, 7V max
Storage Temperature Range ………………………………………. - 65 to +150 °C
Operating Temperature Range ……………………………………. - 30 to +85°C
Maximum Junction Temperature …………………………………. 125°C
θJA Thermal Impedance (LQFP-64) ………………………………. 2 layer board 76°C/W
θJA Thermal Impedance (LQFP-64) ………………………………. 4 layer board 54°C/W
Lead Temperature Range (Soldering, 60sec) ……………………... 300°C
ORDERING GUIDE
Model Temperature Range Package
ADP3500AST -30 C to 85 C LQFP 64 pins
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 9 -
PIN CONFIGURATION
OPT2-
PW
RONKEY-
OPT1-
OPT3
INT-
KEYPADCOL0
KEYPADROW0
OSC
IN
OSCOUT
32KOUT
RSTDELAY-
RESET+
TEST
RTCV
RESETIN-
GPIO3
GPIO2
GPIO1
GPIO0
DATA
CLKIN
CS
REFO
LDO1 (Baseband VDD)
LDO2 (Baseband AVDD)
LDO3 (RTC/Coin-cell)
LDO11 (Option)
LDO4 (Audio)
LDO6 (Baseband Core)
LDO5 (Vibrator)
LDO7 (RF Rx1)
LDO8(RFTx)
LDO9(RFRx2)
LDO10(RFOption)
ADAPTER
ISENSE
BASE
BVS
AGND
BATID
MVBAT
NRCAP
VBAT
BLIGHT
TCXO_ON
DGND
RESETOUT-
SLEEP-
KEYPADCOL1
KEYPADCOL2
KEYPADCOL3
KEYPADROW1
KEYPADROW2
KEYPADROW3
KEYPADROW4
KEYPADROW5
AGND
AGND
AGND
VBAT
VBAT
VBAT
VBAT
VBAT
64 49
48
1
33
32
17
16
Figure 2. Pin Configuration
PIN DESCRIPTION
Pin Mnemonic I/O Supply Function
1 OPT3 I VBAT Optional Power ON input. ADP3500 will keep “power ON” during this pin goes “High”.
2 KEYPADCOL0 O LDO1 Keypad Column Strobe 0 (Open Drain, pull low)
3 KEYPADCOL1 O LDO1 Keypad Column Strobe 1 (Open Drain, pull low)
4 KEYPADCOL2 O LDO1 Keypad Column Strobe 2 (Open Drain, pull low)
5 KEYPADCOL3 O LDO1 Keypad Column Strobe 3 (Open Drain, pull low)
6 KEYPADROW0 I LDO1 Keypad Row Input 0. Pulled up internally, 10KΩ
7 KEYPADROW1 I LDO1 Keypad Row Input 1. Pulled up internally, 10KΩ
8 KEYPADROW2 I LDO1 Keypad Row Input 2. Pulled up internally, 10KΩ
9 KEYPADROW3 I LDO1 Keypad Row Input 3. Pulled up internally, 10KΩ
10 KEYPADROW4 I LDO1 Keypad Row Input 4. Pulled up internally, 10KΩ
11 KEYPADROW5 I LDO1 Keypad Row Input 5. Pulled up internally, 10KΩ
12 TCXO_ON I LDO1 Logic input pin for Main LDOs (LDO1, LDO2, LDO3, LDO6) turning on control. L: OFF, H
:
ON
13 SLEEP- I LDO1 Logic input pin for RF Rx LDOs (LDO7 and LDO9). Gating register data with this input for
these LDOs. LDO7 and LDO9 are turned OFF when SLEEP- goes Low even if the registers
set to ON.
14 BLIGHT O VBAT LED drive. Open drain output.
15 DGND - - Digital Ground
16 INT- O LDO1 Interrupt signal output
17 RTCV - - Supply input for RTC, 32KHz OSC, and some other logics. Connects to Coin cell battery in
typical operation.
18 OSCOUT - RTCV Connect to 32.768KHz crystal.
19 AGND - - Analog Ground
20 OSCIN - RTCV Connect to 32.768KHz crystal.
21 GPIO0 I/O LDO1 General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both
falling and raising edge.
22 GPIO1 I/O LDO1 General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both
falling and raising edge.
23 GPIO2 I/O LDO1 General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both
falling and raising edge.
24 GPIO3 I/O LDO1 General Purpose Input and Output port. Integrated Interrupt function. Interrupt occurs both
falling and raising edge.
25 DATA I/O LDO1 Serial Interface data input and output.
26 CS I LDO1 Serial Interface Chip Select input. Active High input.
27 CLKIN I LDO1 Serial Interface Clock input.
28 RESETIN- I LDO1 Reset input signal for internal reset signal and starts Stay-Alive timer.
29 32KOUT O RTCV 32.768KHz output. Output after 30mS when Reset is released.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 10 -
30 RESET+ O RTCV Reset output. Invert signal of RESETOUT-. Open drain and low OFF leak.
31 RESETOUT- O RTCV Reset output. Follows Voltage Detector operation. Open drain output.
32 TEST I RTCV Test pin. If the pin tied to RTCV, test mode runs. Connect to GND for normal operation.
33 RSTDELAY- O RTCV Reset output. 50mS delayed. Connect to baseband’ reset input as typical application. Open
drain output.
34 VBAT - - Supply input. Connect to Battery.
35 LDO11 O VBAT Regulator #11 output. Use for Optional circuit.
36 LDO1 O VBAT Regulator #1 output. Use for Baseband I/O supply.
37 VBAT - - Supply input. Connect to Battery.
38 LDO3 O VBAT Regulator #3 output. If VBAT>2.7V, the output is always active. Use for Coin cell supply.
39 AGND - - Analog Ground
40 REFO O VBAT Output of LDO2 through FET switch.
41 LDO2 O VBAT Regulator #2 output. Use for Baseband analog supply.
42 VBAT - - Supply input. Connect to Battery.
43 LDO4 O VBAT Regulator #4 output. Use for General analog supplies. Ex. Speaker Amp.
44 LDO5 O VBAT Regulator #5 output. Use for Vibrator.
45 VBAT - - Supply input. Connect to Battery.
46 LDO6 O VBAT Regulator #6 output. Use for Baseband core supply.
47 LDO7 O VBAT Regulator #7 output. Use for RF Rx IC supply. Gated with SLEEP- signal input.
48 VBAT - - Supply input. Connect to Battery.
49 LDO8 O VBAT Regulator #8 output. Use for RF Tx IC supply.
50 AGND - - Analog Ground
51 LDO9 O VBAT Regulator #9 output. Use for RF Rx IC supply. Gated with SLEEP- input signal.
52 VBAT - - Supply input. Connect to Battery.
53 LDO10 O VBAT Regulator #10 output. Use for Optional circuit.
54 BVS - - Battery Voltage Sense input for Charger. Connect to Battery.
55 NRCAP O VBAT Noise reduction capacitor. 0.1µF MLCC.
56 AGND - - Analog Ground
57 MVBAT O VBAT Battery voltage divider output. Buffered internally. Connect to Baseband ADC.
58 BASE O ADAPTER Base drive output for PNP pass transistor
59 ADAPTER - - AC adapter input. Use to charger supply.
60 BATID I ADAPTER Battery identification. 100KΩpulled up internally. “L”: Battery exist, “H”: No battery. If
BATID=”H”, Charger operates with “No current Limit”.
61 ISENSE I ADAPTER Charge current sense input
62 PWRONKEY- I VBAT Power ON/OFF key input. Pulled up internally (140KΩ).
63 OPT1- I VBAT Optional Power ON input. ADP3500 will keep “power ON” during this pin goes “Low”.
64 OPT2- I/O VBAT Optional Power ON input. ADP3500 will keep “power ON” during this pin goes “Low”.
While the part is powered up, the input is pulled to Low (GND) internally. Don’t connect to
any supply or signal source.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 11 -
BLOCK DIAGRAM
Serial
I/F
LPF
OPT2-
PWRONKEY-
OPT1-
OPT3
INT-
KEYPADCOL0
KEYPADROW0
6
OSC IN
OSC OUT
32K OUT
VBAT Charger_Detect
Delay
10mS
Data
In
32KHz
Delay
30mS
RTC
/clock
Stay/Alive
Timer
0.25-8sec
CLKs
Data
Delay
50mS RSTDELAY-
RESET+
TEST
RTCV
DGND
DGND
RESETIN-
GPIO3
GPIO2
GPIO1
GPIO0
DATA
CLKIN
CS
REFO
Voltage
Detector
LDO1 (Baseband VDD)
LDO2 (Baseband AVDD)
LDO3 (RTC/Coin-cell)
LDO11 (Option)
LDO4 (Audio)
LDO6 (Baseband Core)
LDO5 (Vibrator)
LDO7 (RF Rx1)
LDO8 (RF Tx)
LDO9 (RF Rx2)
LDO10 (RF Option)
ADAPTER ISENSE
Battery Charger
BASE BVS
AGND
BATID
MVBAT (VBAT Measure)
REF
NRCAP
VBAT
Charger Control
PWROFF
INT
RTC
Alarm
KEY
PAD
I/F
4
GPIO
+
INT
BLIGHT
LDO1
LDO2
LDO3
LDO6
LDO11
LDO4
LDO5
LDO7
LDO8
LDO9
LDO10
ON/OFF
LOGIC
ON/OFF
LOGIC
ON/OFF
LOGIC
ON/OFF
LOGIC
Main
Sub
Main
Sub
Main
Main
Sub
TCXO_ON
DGND
RTCV
RESETOUT-
voltage_detect
CLK
RESETIN_N
Data
Open Drain
BATID
DDLO
LDO_EN
SLEEP-
GPIO_INT / gpi_intrst
DATA
DATA
POWERON_N
OPT1_N
OPT2_N
OPT3
INT_N
power_on
CLKs
5
sync
5
LDO1
LDO1
Level
trans
30
31
33
32
17
13
12
28
REF
LDO1
Level
trans
35
53
51
49
47
44
43
46
38
41
36
55
40
57
60
5458615934374245485219395056
62
63
64
1
16
3
4
5
6
7
8
9
10
11
2
Level
trans
LDO1
14
KEYPADCOL1
KEYPADCOL2
KEYPADCOL3
KEYPADROW1
KEYPADROW2
KEYPADROW3
KEYPADROW4
KEYPADROW5
15
26
27
25
21
22
23
24
20
18
29
LDO1
RTCV
Level Translator
Level
trans
Level
trans
CLK
140KΩ
100KΩ
Level Translator
VBAT & RTCV
Figure 3. Overall Block Diagram
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 12 -
Theory of Operations
As illustrated in Figure 1 at the beginning, ADP3500 can be divided into two high level blocks – Analog and Logic.TheAnalog
block mainly consists of LDO regulators, battery charger, reference voltage, and voltage detector sub-blocks, all of which are
powered by the main power source(VBAT), namely the main battery or the charging adapter. On the other hand, the Logic block is
more complicated. All the Logic sub-blocks are also powered by VBAT except the RTC counter, 32MHz Output control, RESET
Output, and Stay-Alive Timer. These sub-blocks are powered from RTCV pin, as indicated in Figure 4 in shaded area.
[VBAT]
5
4
3
2
1
POWER ON
KEYPAD I/F
GPIO
SERIAL I/F
RESET
[RTCV]- RTC BLOCK
10
32K OUTPUT
CONTROL
RESET OUTPUT
9
11
RTC COUNTER
STAY-ALIVE TIMER
LDO CONTROL
INTERRUPT
CONTROL
DELAY 10mS6
7
8ANALOG
BLOCK
Figure 4. Power partitioning of sub-blocks
1. ANALOG BLOCKS
1.1 LOW DROP-OUT(LDO) REGULATORS
There are total four Sub-LDOs for each LDO1, 2, 3, and 6, in order to meet lower power consumption at light load (stand-by
operation). They are used at low load condition, but they are continuously ON even if the each Main-LDOs are ON. The LDO3 and
3b are used for Coin cell and LDO3b is always ON until Main battery (VBAT) is downed to 2.5V due to DDLO function. LDO7 and
9 are controlled with SLEEP- signal. For detail of LDO ON/OFF control, please refer to Section “2.8 LDO Control”.
Table 1. Ground currents of LDOs with each handset operations.
LDO names Baseband
VDD Baseband
Core Coin Cell Audio Vibrator Baseband
AVDD RF
Rx1 RF
Tx RF
Rx2 RF
Option Option Main
REF Total LDO
IGND
LDO # 1 6 3 4 5 2 7 8 9 10 11
Power OFF OFF OFF 10µAOFF OFF OFF OFF OFF OFF OFF OFF 20µA30µA
Light load 10µA5µA 10µAOFF OFF 5µAOFF OFF OFF OFF OFF 20µA50µA
Mid-load 60µA 55µA60µAOFF OFF 55µAOFF OFF OFF 50µAOFF 20µA 300µA
Stand-
by
mode Active load 60µA 55µA60µAOFF OFF 55µA50µA50µA50µA50µAOFF 20µA 450µA
Talk 60µA 55µA60µA50µAOFF 55µA50µA50µA50µA50µA50µA20µA 550µA
Ring 60µA 55µA60µA50µA 50µA 55µA50µA50µA50µA50µA50µA20µA 600µA
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 13 -
Table 2. LDO operation overview
Regulator Names Current
Rating (mA) Voltage (Typ)
Or Range Program steps Step size
(mV) Default Cout
LDO1a Baseband VDD 150 2.90V N/A N/A - 2.2µF
LDO1b Baseband VDD sub 1 2.87V N/A N/A - 2.2µF
LDO2a Baseband AVDD 50 2.36V~2.66V 16 20 2.52V 1µF
LDO2b Baseband AVDD sub 0.3 2.33V~2.63V 16 20 2.49V 1µF
LDO3a RTC/Coin Cell 50 3.0V N/A N/A - 1µF
LDO3b RTC/Coin Cell sub 1 2.97V N/A N/A - 1µF
LDO4 Audio 180 2.9V N/A N/A - 2.2µF
LDO5 Vibrator 150 2.9V N/A N/A - 2.2µF
LDO6a Baseband Core 50 2.6V N/A N/A - 1µF
LDO6b Baseband Core sub 0.3 2.57V N/A N/A - 1µF
LDO7 RF Rx1 100 2.9V N/A N/A - 2.2µF
LDO8 RF Tx 150 2.9V N/A N/A - 2.2µF
LDO9 RF Rx2 50 2.9V N/A N/A - 1µF
LDO10 RF Option 50 2.9V N/A N/A - 1µF
LDO11 Option 100 1.5V N/A N/A - 2.2µF
1.2 BATTERY CHARGER
1.2.1. Block Diagram
LOGIC Block
ISENSE
ADAPTER BASE
gm
EN
BVS
BATID
Charger_
Detect
BATID
gm
REF
Pre-charge
5m A
CHV
0/1
BVS
MVEN MV4:0
RSENSE
AC Adapter
Cvbat
CHI CHEN
EN
DDLO
LDO_
EN
+
V(ISENSE)
-
EN
EN
MVBAT
MVBAT
VBAT
100KΩ
Battery
CADAPTER
Figure 5. Battery charger block diagram
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 14 -
1.2.2. Flow Chart
N
Y
Battery charger start
VADAPTER>VBAT
?
Set Charger Detect flag
Pre-charge 5mA
VBAT>DDLO
?
BATID=0
?
BATID=0: Battery connected
BATID=1: Battery disconnected
Determined by external
sense resistor
Set Low Current Charge
IADAPTER=250mA
(50mV on Rsense)
Pre-charge: OFF
Current Loop Disabled
Voltage Loop Regulates
VBAT to 4.0V
Pre-charge: OFF
Voltage Detector
VLDO6>2.5V
AND
VLDO1>2.7V
?
LDO1,1b,2,2b,3,6,6b
Voltage Detector
all enabled
LDO3b: ON
DDLO comparator will
operate if VBAT>2V.
Even if VBAT<2V, pre-
charge is continuously
applying 5mA.
RESETIN- should be
asserted until baseband
chip active.
Then, CHEN=1 as default.
Figure 6. Charger flow chart A
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 15 -
Reset sequence runs
A
Baseband sets Charge Voltage
Baseband sets MVBAT gain
Baseband Enables
Full charge current?
(CHI=1?)
N
Y
Low Current Charge: OFF
SetFullcurrentcharge
IADAPTER=750mA
(150mV on Rsense)
Baseband
CHEN=0?
N
Y
Charging Terminated
CHI=0: Full current charge OFF
CHI=1: Full current charge ON
Figure 7. Charger flow chart B
1.2.3. Charger Detect function
The ADP3500 will detect that a charging adapter has been applied when the voltage at the ADAPTER pin exceeds the voltage at
BATSNS. The ADAPTER pin voltage must exceed the BVS voltage by a small positive offset. This offset has hysteresis to prevent
jitter at the detection threshold. The charger detection comparator will set the Charger_Detect flag in the 20h register and generate an
interrupt to the system. If the ADAPTER input voltage drops below the detection threshold, charging will stop automatically and the
Charger_Detect flag will be cleared and generate an interrupt also.
1.2.4. DDLO function and operation
The ADP3500 contains a comparator that will lock out system operation if the battery voltage drops to the point of deep discharge.
When the battery voltage exceeds 2.675 V, the reference will start as will the sub-LDO 3b. If the battery voltage drops below the
hysteresis level, the reference and LDO's will be shut down, if for some reason they are still active. Since LDO1 will be in deep
dropout and well below the voltage detector threshold at this point, the reset generator will have already shut down the rest of the
system via RESET+, RESETOUT-, and RSTDELAY-.
If a charging adapter has been applied to the system, the DDLO comparator will force the charging current to trickle charge if the
battery is below the DDLO threshold. During this time, the charging current is limited to 5 mA. When the battery voltage exceeds
the upper threshold, the low current charging is enabled, which allows 55 mV (typical) across the external charge current sense
resistor. See also Figure 6, the Battery Charger Flowchart.
1.3 MVBAT
The ADP3500 provides a scaled buffered output voltage for use in reading the battery voltage with an A/D converter. The battery
voltage is divided down to be nominally 2.600 V at full scale battery of 4.35 V. To assist with calibrating out system errors in the
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 16 -
ADP3500 and the external A/D converter, this full scale voltage may be trimmed digitally with 5 bits stored in register 12h. At full
scale input voltage, the output voltage of MVBAT can be scaled in 6 mV steps, allowing a very fine calibration of the battery voltage
measurement. The MVBAT buffer is enabled by the MVEN bit of register 11h, and will consume less than 1 uA of leakage current
when disabled.
1.4 REFERENCE
The ADP3500 has an internal, temperature compensated and trimmed band-gap reference. The battery charger and LDO's all use
this system reference. This reference is not available for use externally. However, to reduce thermal noise in the LDOs, the
reference voltage is brought out to the NRCAP pin through a 50kohm internal resistor. A cap on the NRCAP pin will complete a low
pass filter that will reduce the noise on the reference voltage. All the LDO's, with the exception of LDO3, use the filtered reference.
Since the reference voltage appears at NRCAP through a 50kohm series internal impedance, it is very important to never place any
load current on this pin. Even a volt meter with 10 megohm input impedance will affect the resulting reference voltage by about 6 or
7 mV, affecting the accuracy of the LDO's and charger. If for some reason the reference must be measured, be certain to use a high
impedance range on the volt meter or a discrete high impedance buffer prior to the measurement system.
2. LOGIC BLOCKS
ADP3500 has following logic functions.
• Three wire Serial Interface (CS, CLK, DATA)
• RTC counter section has Year, Month, Day, Week,
Hour, Minute, and Second, and controls Leap year,
and days in month automatically.
• Detect Alarms based on RTC counter.
• Periodically constant interrupt feature. (2Hz, 1Hz,
1/60Hz, 1/3600Hz, Once a months)
• GPIO and INT ports control
• Key-pad interface
• LED light control
• LDO functions
• Clock and Reset output control
• Stay-Alive timer
Following is a block diagram based on Logic circuit.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 17 -
CS
CLKIN
DATA
KEYPADROW
KEYPADCOL
GPIO[3:0]
RESETIN_N
32K OSC
OSCIN
OSCOUT
RSTDELAY_N
RESETOUT_N
RESET
PWRONKEY_N
OPT2_N
OPT3
chager_detect
voltage_detect
rtc_clk32k
INT_N
DELAY
10mS
keypad_int
TEST
4
4
6
ct
f
g_int
clk32k
voltage detect_delay
power_on
TCXO_ON
test_mode
[VBAT]
write_data[7:0]
write_enable
sp_addr[4:0]
clk512
SLEEP_N
test_ldoenable
BLIGHT
DGND
batid
Analog
Blocks
LDO control register
pwronkey_n_sync,
opt1_n_sync,
opt3_sync
Interrupt
register
block
LED control
Analog block
KEY PAD
I/F
BL
GPIO
OPT1_N
alarm_int
Serial
I/F
Data
select
resetin_n
(reset for registers)
rtc_resetin_n
analog block
rt
c_writ
e_enable
rt
c_writ
e_dat
a[
7:
0]
rt
c_sp_addr[
5:
0]
rt
c_read_dat
a[
7:
0]
LDO
Control
32K CLK
output
control
32K OUT
Testmodecont
rolsignal
Timingsignals
RTC register block
clk1k
rtc_voltage_detect rtc_voltage_detect
[RTCV]
reset output
control
SYNC.
t
est
_vdet
_signal
RTC_CS
RTC
Output data
select
Address
decode
Test mode
register
block
Stay-Alive
Timer
DATA
IN
POWER
OFF
INT
control
register
(reset & mask)
KEY PAD
I/F control
GPIO
control
Analog
control
registers
rtc_test
SYNC.
SYNC.
Figure 8. LOGIC block diagram
2.1 RESET
2.1.1 RESETIN- signal
The internal reset function is activated by external reset input, RESETIN-, and this is an asynchronous signal. The internal
reset signal is used in the following blocks.
• Serial I/F
• Interrupt control
• Stay-Alive timer
• Registers (refer to the Register section for detail).
LDOs, controlled by Serial I/F, are applied “RESET” by RESETIN-. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, LDO11
and REF0 are set to “0”. In case RESETIN- has noise, the internal circuit may be in reset and cause the system unexpected
result. Please take enough treatment. RESETIN- is level translated from LDO1 to both VBAT and RTCV supplies.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 18 -
2.1.2 RESET output control and 32KHz output control
Using Voltage Detect signal, device generates 32K OUT, RSTDELAY-, RESETOUT-, and RESET signals. About 32mS after
rtc_voltage_detect (Voltage Detect signal in RTCV supply) signal goes from “0” to “1”, 32K OUT signal is generated from
internal RTC_CLK32K signal. RSTDELAY_N (RSTDELAY-) goes to “0” when rtc_voltage_detect is “0”, and it goes to “1”
at 50mS after the “0” to “1” transition of rtc_voltage_detect. RESETOUT_N (RESETOUT-) and RESET toggle their states.
Signal clk512 is a 512Hz, which generated in USEC counter block.
2.2 SERIAL INTERFACE
Serial I/F WRITE Timing
CLKIN
CS
tCKS tCSS
tCKH tCKL
Serial
DATA
tCSR
tCSH
ADDR5 ADDR4 0 CTRL1 (W) CTRL2 (W) DATA7 1 DATA0
Serial I/F READ Timing Single Mode
CLKIN
CS
tCKS tCSS
tCKH tCKL
Serial
DATA
tCSR
ADDR5 ADDR4 0 CTRL1 (R) CTRL2 (R) DATA7 1DATA0
tRD tCSZ
Serial I/F READ Timing Continuous Mode
CLKIN
CS
tCKS tCSS
tCKH tCKL
Serial
DATA ADDR5 ADDR4 0 CTRL1 (R) CTRL2 (R) DATA7 1
tRD
DATA0 ADDR5
tRZ
ADDR4
Figure 9. Serial Interface signal
Table 3. Set up and Hold Specifications
Parameter Min. Typ. Max Units Test Condition/Comments
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 19 -
tCKS 200 nS CLK set-up time
tCSS 400 nS CS set-up time
tCKH 400 nS CLK “High” Duration
tCKL 400 nS CLK “Low” Duration
tCSH 500 nS CS hold time
tCSR 62 µSCS recovery time
tDS 200 nS Input data set-up time
tDH 200 nS Input data hold time
tRD 300 nS Data output delay time
tRZ 300 nS Data output floating time
tCSZ 300 nS Data output floating time after CS goes low.
2.2.1. Function block
ADP3500 integrates the serial bus interface for easy communication with the system. The data bus consists of three wires,
CLK, CS, and DATA, and is capable of Serial to Parallel / Parallel to Serial conversion of data, as well as clock transfer.
Serial To Parallel
Conversion
Parallel to Serial
Conversion
Creation of
write Data
sp_data [7:0]
write_enable
sp_addr [5:0]
ps_data [7:0] Synchlonization
and Data Selection
DATA
RW_SEL
resetin_n
CS
CLKIN
DATAIN
Figure 10. Serial Interface block diagram
Serial interface block works during the time period at CS signal enable. After the falling edge of CLKIN signal right after the
rising edge of CS signal, Address, transfer control signal and write data are held in sequentially. In case DATA READ, each of
data will be prepared by rising edge of CLKIN and baseband chip may want to read or latch the data at falling edge of CLKIN.
While CS is not asserted, CLKIN is ignored. If CS goes “L” while CLKIN is continuously applied or input DATA, all data is
canceled and DATA line would be High impedance. In this case, user needs to input the data again. Please note that CLKIN
should be stayed “L” when CS goes H. RTC counter registers should be accessed at a certain time (>62µS) later after CS
assertion. Asserting RESETIN_N (RESETIN-) signal resets the block..
Notes:
• CLKIN=10KHz to 1MHz, 20/80% duty cycle.
• CLKIN should be “L” when CS goes “H”.
• In case of RTC counter access, the access should be approximately 62µS, (2 clock cycles of CLK32K) after the CS signal
is asserted, to hold the RTC value.
• The CS should not be asserted for 62µS, (2 clock cycles of CLK32K) after the CS is released.
• CS signal should never be asserted for 1 sec or longer, otherwise RTC counter makes error.
2.2.2 Data input/output timing
Address(6bit) R/W(2bit) Read DATA(8bit)
4 3 2 1 05 1 0 7 6 5 4 3 2 1 0
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 20 -
Figure 11. Serial I/F Data read/write timing
SP_ADDR[5:0] : 6bit address
SP_CTRL[1:0] : 2bit Read/Write control (01: Write, 10: Read)
SP_DATA[7:0] : 8bit Input/Output Data
* All transfer will be done MSB first.
2.3 GPIO+INT
GPIO block has 4 channel I/O function and interrupt. With GPIO CONTROL register (1Ah), it is possible to control Input or
Output setting of each channel individually. The output data is set in GPIO register (1Ch). When the port is set as input mode,
the input signal transition from “1” to “0” and from “0” to “1”, then generate interrupt signal with Edge detection. The held
interrupt signals are reset by GPIO INT RESET register (1Dh). Setting GPIO MASK register (1Bh) to “1” enables the
interrupt of GPIO. (Not MASKED, “1” at default in reset.)
2.4 INT REGISTER
In case the interrupt event has occurred, “1”, the signal is held in this register. INT detect and Reset are synchronized at the
rising edge of CLK32K. In case the interrupt event and reset signal are occurred at same time, interrupt event has priority.
RESETIN_N signal resets INT register (1Eh) to “0” (No INT detected), except alarm_int and ctfg_int. INT MASK register
(1Fh) to “1” (not masked). This block masks alarm_int and ctfg_int, which generated in RTCV block, but these signals are
reset with ALARM CONTROL register (0Dh) and CTFG CONTROL register (0Eh). The interrupt signal, INT_N, is an
“inverted OR” signal of value in INT register and GPIO register.
DATA-IN register is a port to read an interrupt status. The input data are through SYNC block except Alarm signal. Since this
is for just read back purpose, user cannot write any data.
BATID
RTC Alarm
Charger_Detect
OPT3
OPT1-
PWRONKEY-
SYNC block
DATA_IN registor (Addr: 20h)
Register
Figure 12. DATA-IN block
2.5 KEYPAD CONTROL & LED DRIVE
KEYPADCOL[3:0] are Open Drain output. The KEYPADROW[5:0] are Falling edge trigger input (input state transition from
“1” to “0”) and generate Interrupt signal, and are pulled up to LDO1. By providing 4 keypad-column outputs and 6 keypad-
row inputs the ADP3500 can monitor up to 24 keys with baseband chip. Writing Column outputs and Reading Row inputs are
controlled through serial interface. The address of the KEYPADROW is 19h, and KEYPADCOL is 18h. Initial register value
is “0” that means an output of KEYPADCOL is “High Impedance”.
Back-light drive is an open drain output. Maximum current of internal FET is 100mA. Initial register value is “0” that means
the output of BLIGHT is “High impedance”.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 21 -
2.6 POWER ON INPUT
PWRONKEY and OPT1 have pull-up resistors, and others are not. In addition to these inputs, other internal input signals such
as charger_detect and Alarm signal (alarm_int) from RTC enable Main and Sub LDOs of LDO1, 2, 3 and LDO6. Power ON
status is hold by a latch data in Delay circuit, called voltage_detect_delay (please see 4.8 for more detail). OPT3 has a lower
voltage threshold. OPT2 is different structure to the other inputs, and is pulled down to zero by internal signal when phone is
Power ON status, in order to make sure to have Power ON status even if short-term disconnection is happened. Following is a
block diagram and Power on sequence.
VBAT
voltage_detect_delay
charger_detect
alarm_int power_on
PWRONKEY-
OPT1-
OPT2-
OPT3
140KΩ140KΩ
INT
Block
Figure 13. Power ON input block diagram
• Voltage_detect_delay : Voltage Detect Signal (10mS delay) (1: Assert)
• charger_detect : Charger Detect Signal (1: Assert)
• alarm_int : Alarm Detect Signal (Alarm 1 or 2) (1: Assert)
• PWRONKEY- : Power On key input (0: Assert)
• OPT1- : Power On signal (0: Assert)
• OPT2- : Power On signal (0: Assert)
• OPT3 : Power On signal (1: Assert)
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 22 -
PowerOnKey
POWERON
LDO1,2,3,6
LDO1b, 2b, 6b
Voltage Detector
voltage_detect_delay
RSTDELAY-
OPT2
INT-
Serial I/F
10mS
50mS
POWER ON POWER OFF
Clear INT- and set PWROFF(21h)=1
Clear INT-
Figure 14. Power ON sequence
2.7 10 MILISECOND DELAY
This block generates a 10mS delayed signal after the reset of the voltage_detect signal is released. After 10mS (11 clocks of
1024Hz) since the voltage_detect signal is asserted, the voltage_detect_delay signal is asserted. If the duration of the
voltage_detect signal is less than 10mS, voltage_detect_delay signal will not be asserted. When the voltage_detect signal is
released, the voltage_detect_delay signal is also released simultaneously. The voltage_detect_delay signal can be reset with
writing “1” in POWER OFF register (21h).
* User just need to write “1” in the POWER OFF register to reset voltage_detect _delay, and not need to over-write it with “0”.
2.8 LDO CONTROL
The LDO control block controls Power ON/OFF of LDO block. The function in this block has:
• Hardware control using external signals
• Software control using serial interface
• Mixture of hardware and software above
LDO1, LDO2, LDO3, and LDO6 are structured with Main and Sub LDOs. LDO4, LDO5, LDO7, LDO8, LDO9, LDO10, and
LDO11 are set through serial interface but LDO7 and LDO9 are gated (AND gate) with SLEEP- signal, in order to get into
Sleep mode. If the SLEEP- signal is enabled (goes “Low”), the outputs of LDO7 and LDO9 are turned OFF. Remainder of
LDOs as LDO1, LDO2, and LDO6 is controlled by “Power On Logic”. A Sub LDO called “LDO3b” is independent control
and this LDO control block doesn’t control LDO3b. And Main LDO3 called “LDO3a” is turned on by power_on signal, but
Sub LDO3 called “LDO3b” is always ON while Battery supplies and LDO3b is only controlled by DDLO. A DDLO is control
signal from Battery charger block and is monitoring Battery voltage. When VBAT is under 2.5V (200mV hysteresis from
VBAT=2.7V), DDLO minimizes (DDLO enable) current flow from Li-Ion battery.
Main LDOs : LDO1a, LDO2a, LDO3a, LDO6a
Sub LDOs : LDO1b, LDO2b, LDO3b, LDO6b
Table 4a. DDLO status table
Status LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11
Baseband VDD Baseband
AVDD Coin cell Audio REFO Vibrator Baseband Core Rx1 Tx Rx2 RF
Option Option
DDLO Enable OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
DDLO Disable XXXXXONXX X XXXXXXX
Note
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 23 -
1. “X” means a status of LDO depends on other conditions.
Table 4b. LDO Control Event Table
Event LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11
Baseband VDD Baseband
AVDD Coin cell Audio REFO Vibrator Baseband Core Rx1 Tx Rx2 RF
Option Option
POWER ON
(Note 2) ON ON ON ON ON ON ON
TCXO_ON
(Note 3) ON/
OFF ON/
OFF ON/
OFF ON/
OFF
SLEEP-
(Note 4) ON/
OFF ON/
OFF
RESETIN- OFF OFF OFF OFF OFF OFF OFF OFF
“ALLOFF” bit
goes “H” OFF OFF OFF OFF OFF OFF OFF OFF
“PWROFF” bit
goes “H” OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF
Notes
1. This table only indicate the change of status caused by an event. Blank cells means “no change” and keep previous status
2. Power ON Event: Indicating a status just after the power ON event. After the event, a status of LDO1a, 2a, 3a, and
LDO6a are changed by TCXO_ON signal.
3. TCXO_ON: Hardware control, change all Main-LDO’ ON/OFF status.
4. SLEEP-: The LDO7 and LDO9 are able to be controlled by software if SLEEP=”H” level. If SLEEP- goes “L”, these
LDOs are turned OFF immediately.
Table 4c. Software Controllability of LDOs
LDO1a LDO1b LDO2a LDO2b LDO3a LDO3b LDO4 REFO LDO5 LDO6a LDO6b LDO7 LDO8 LDO9 LDO10 LDO11
LDO description Baseband VDD Baseband
AVDD Coin cell Audio REFO Vibrator Baseband Core Rx1 Tx Rx2 RF
Option Option
Software Turn
ON √√ √ √
(Note1) √√
(Note1) √√
Software Turn
OFF √√√√√ √√ √ √√√√√√√
Note
1. LDO7 and LDO9 have a gate with SLEEP-. If SLEEP- is in “L” (active) status, user cannot control and both LDOs are kept
to “OFF” status. User may want to use this function as immediate control to get OFF status by using SLEEP- hardware control
while set register “1” to the LDO control register.
2.9 RTC BLOCK
The Calendar registers are set through serial interface.
2.9.1 Function
• RTC counter using binary
• Reading out and writing setting s of Year, Month, Day, Week, Hour, Minute, and second data.
• Leap year controls, Number of days in a month control
• Alarm function (Weak, Hour, Minute)
• Periodic Interrupt function - 2Hz, 1Hz, 1/60Hz, 1/3600Hz, Each month (First day of each month)
• Protection of wrong data readout during RTC data update.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 24 -
USEC
Counter
RTC
Counter
Loading Alarm times
RTC_WRITE_ENABLE
RTC_CLK32K
rtc_data[7:0]
rtc_alarm_int
RTC_CS
rtc_ctfg_int
RTC_WRITE_DATA[7:0]
(from serial I/F)
RTC
Register
block
RTC_SP_ADDR[5:0]
Alarm
Comparator
Periodic
Interrupt
Data
Select
leap year
and Date
Control
Reset will be asserted when
RTC counter is writed.
Registers for
Test mode
- Reset to RTC & USEC counters
- Write initial data of USEC counter
Sec counter
Increment
control
Figure 15. RTC counter block
2.9.2 Operation
Synchronizing with RTC_CLK32K clock, USEC counter generates 1sec timing clock and the clock hits RTC counter.
Through the serial interface, CPU can write setting value and read RTC counter value. In case the RTC counter toggles during
the serial interface access to RTC counter, the wrong data can be read/write between RTC counter and interface. CS signal
stops the clocking to RTC counter until CS signal is released. In case CPU writes data into SEC counter, USEC counter is
reset to zero.
Note
• In case of RTC counter access, the access should be waited approximately 62µS, (2 clock cycles of CLK32K) after the
CS signal is asserted, to hold the RTC value.
• CS signal should never be asserted 1sec or longer, this affects counter operation.
2.9.3 Operation of USEC counter
USEC counter counts up synchronizing with RTC_CLK32K clock. It generates 1sec timing signal and it is used as an
increment clocking of RTC counter. In case the 1sec signal is generated during CS signal asserted, the increment clock is
delayed until CS signal is released.
2.9.4 Operation of RTC counter
RTC counter uses the increment signal from USEC counter to control counting operation including the leap year control and
numbers of days in a month control.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 25 -
addr06h_write
USEC
counter
addr00h_write
7 scale
31 scale
12 scale
100 scale
00h
01h
02h
03h
04h
05h
06h
month_count
year_count
day_count
hour_count
week_count
min_count
sec_count
Enabled signals created
by decoding of
RTC_SP_ADDR[5:0]
Initial data
12 scale
60 scale
60 scale
Leap year
&
days in month
control
inc_enb
inc_clk
To following
counters
Year
Month
Date
Week
Hour
Minute
Second
Figure 16. RTC counter block diagram
Definition of Leap year
The definition of a leap year is, “a year which can be divided by 4 and can not be divided by 100” and “a year which can be
divided by 400.” For this device, the following definition is used instead.
“A year which can be divided by 4”
Note - Year counter = “00” means year 2000, and is a leap year because it can be divided by 400.
- Actual covered year period is from 1901 to 2099.
Number of days of month control
Months 1, 3, 5, 7, 8, 10, 12 have 31days.
Months 4, 6, 9, 11 have 30days.
Month 2 has 28days, but has 29 in leap year.
2.9.5 Alarm Function
Comparing the RTC counter value with the seting value in alarm_setting register (07h-09h), alarm condition is detected.
Setting of week uses 7bits for each day in a week, and works with multiple days setting. There is a delay of 62µSfromAlarm
detection to setting up to AOUT/BOUT registers.
ALA_EN flag in ALARM CONTROL register (0Dh) sets Enable/Disable of alarm detection. INT register (1Eh) indicates the
interrupt signals, alarm_int of ALA or/and ALB. INT MASK register (1Fh) do mask of alarm interrupt signal. Alarm
detection state is indicated as AOUT of ALARM CONTROL register (0Dh), and the alarm can be released by writing “1” at
the bit. Alarm B is also controlled as same as Alarm A is.
Note: User just need to write “1” to release the alarm, and not need to write “0” after “1”. User doesn’t need to wait 62µS
from CS assertion.
2.9.6 Periodic Interrupt function
This is a function, which generates interrupt periodically. The timing of cycle can be selected from 2Hz (0.5sec clock pulse),
1Hz (1sec clock pulse), 1/60Hz (minutes), 1/3600Hz (hour), and month (first day of each month).
The cycle is set using CT2-CT0 value in CTFG CONTROL register (0Eh). The state when interrupt is generated is indicated at
INTRA bit of CTFG CONTROL register (0Eh). INT MASK register (1Fh) only does mask of periodic interrupt signal. There
are two kinds of pattern of CTFG Interrupt signal output.
• Hold the value when the interrupt is occurred (level).
• After the interrupt event is happened, assert interrupt signal in certain time period then release it (pulse).
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 26 -
In level case, interrupt is occurred at each 0 min (1/60Hz), 0 o’clock (1/3600Hz) or at first day of month. Because they are
happened in long cycle, the value is held at register. After the CPU checks the state, it is released by writing “1” at CTFG bit
of CTFG CONTROL register. In case of 2Hz and 1Hz, the interrupt is not held because the event happens in short cycle.
These event signal output pulse signal of 2Hz or 1Hz in RTC counter directly. Interrupt release operation doesn’t affect on the
interrupt signal in the case.
2.10 STAY-ALIVE TIMER
This is a counter, which increments each 250mS after RTC_RESETIN_N is asserted. It holds its value when the counter
counts full up. Signal clk4 is a 4Hz (250mS) clock which generated in USEC counter. The counter can be reset by writing “1”
at CLR of Stay-Alive TIMER CONTROL register (0Fh). The RTC_RESETIN_N signal is transferred from a logic input
circuit, that is supplied by VBAT, of RESETIN_N.
Note : User just need to write “1” to release the interrupt, and not need to write “0” after “1”.
5bit counter
test_reset
clk4
CLRB
DSA[4:0]
RTC_RESETIN_N
Register
Stay-Alive Timer
Stay-alive Timer Control register (0Fh): CLR
Stay-alive Timer Control register (0Fh): SAx
Figure 17. Stay-Alive Timer block diagram
clk4
sa_count[4:0]
sa_clear
3210 431530 0
rtc_voltage_detect
Figure 18. Stay-Alive Timer operation timing
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 27 -
2.11 REGISTERS
ADDR Description D7 D6 D5 D4 D3 D2 D1 D0 Comment
00h Sec. Counter S5 S4 S3 S2 S1 S0 Note 1,5
01h Min. Counter M5 M4 M3 M2 M1 M0 Note 1,5
02h Hour Counter H4 H3 H2 H1 H0 Note 1,5
03h Week Counter W2 W1 W0 Note 1,5
04h Day Counter D4 D3 D2 D1 D0 Note 1,5
05h Month Counter MO3 MO2 MO1 MO0 Note 1,5
06h Year Counter Y6 Y5 Y4 Y3 Y2 Y1 Y0 Note 1,5
07h Alarm_A Min Register AM5 AM4 AM3 AM2 AM1 AM0 Note 5
08h Alarm_A Hour Register AH4 AH3 AH2 AH1 AH0 Note 5
09h Alarm_A Week Register AW6 AW5 AW4 AW3 AW2 AW1 AW0 Note 5
0Ah Alarm_B Min Register BM5 BM4 BM3 BM2 BM1 BM0 Note 5
0Bh Alarm_B Hour Register BH4 BH3 BH2 BH1 BH0 Note 5
0Ch Alarm_B Week Register (Option) BW6 BW5 BW4 BW3 BW2 BW1 BW0 Note 5
0Dh Alarm Control ALA_EN Aout ALB_EN Bout Note 5
0Eh Periodic Interrupt Control CTFG CT2 CT1 CT0 Note 5
0Fh Stay-Alive Timer Control CLR SA4 SA3 SA2 SA1 SA0 Note 5
10h Charger Control CHI CHEN Note 4
11h Charger MVBAT Control REF0 MVEN Note 4
12h Charger MVBAT CHV1 CHV0 MV4 MV3 MV2 MV1 MV0 Note 4
13h LDO Control 1 LDO11 LDO5 LDO4 Note 4
14h Not available Note 7
15h LDO Control 2 LDO10 LDO9 LDO8 LDO7 Note 4
16h LDO Control 3 ALLOF
FNote 4
17h LDO2 Gain G23 G22 G21 G20 Note 4
18h Keypad Column/B-light Register BL KO3 KO2 KO1 KO0 Note 6
19h Keypad Row KI5 KI4 KI3 KI2 KI1 KI0 Note 6
1Ah GPIO Control Register GPC3 GPC2 GPC1 GPC0 Note 6
1Bh GPIO MASK GPMSK3 GPMSK2 GPMSK1 GPMSK
0Note 6
1Ch GPIO Register GPI3
GPO3 GPI2
GPO2 GPI1
GPO1 GPI0
GPO0 Note 6
1Dh GPIO INT GPINT3
GPRST3 GPINT2
GPRST2 GPINT1
GPRST1 GPINT0
GPRST0 Note 2,6
1Eh INT Register
IN
T7
IR
ST
7
INT6
IRST6 INT5 INT4 INT3
IRST3 INT2
IRST2 INT1
IRST1 INT0
IRST0 Note 2,6
1Fh INT MASK MS
K7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 Note 6
20h DATA IN DI6 DI5 DI4 DI3 DI2 DI1 DI0 Note 6
21h Power OFF PWROF
FNote 6
3Fh TEST register (option) LDOENB USENB TEST Note 3,5
Notes:
1.For the RTC counter data protection, the access should be waited for certain time (62µS) period after CS signal assertion.
(Refer to RTC counter section for the wait time).
2.The INT reset operation will be valid at 62µS or later after its setting.
3.This is a set register for internal test, and should not be accessed at normal operation.
4.Analog block control registers. They control LDO etc. They are powered by VBAT.
5.Registers regarding RTC counter. They are powered by RTCV.
6.Registers for INT, GPIO, KEYPAD I/F etc. They are powered by VBAT.
7.Not available.
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 28 -
Typical Performance Characteristics
(Vin=4.2V,TA=25C)
2.900
2.905
2.910
2.915
2.920
2.925
0 50 100 150
Output Current, mA
Output Voltage, V
2.876
2.877
2.877
2.878
2.878
2.879
2.879
0 0.2 0.4 0.6 0.8 1
Output Current, mA
Output Voltage, V
TPC1, LDO1a load regulation TPC2, LDO1b load regulation
2.860
2.862
2.864
2.866
2.868
2.870
2.872
0 1020304050
Output Current, mA
Output Voltage, V
2.811
2.812
2.812
2.812
2.812
2.812
2.813
2.813
2.813
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35
Output Current, mA
Output Voltage, V
TPC3, LDO6a load regulation TPC4, LDO6b load regulation
2.885
2.890
2.895
2.900
2.905
2.910
2.915
2.920
0 50 100 150 200
Output Current, mA
Output Voltage, V
2.885
2.890
2.895
2.900
2.905
2.910
2.915
2.920
0 50 100 150 200
Output Current, mA
Output Voltage, V
TPC5, LDO4 load regulation TPC6, LDO7 load regulation
PRELIMINARY TECHNICAL DATA
ADP3500
REV.PrP 2/6/02 - 29 -
PACKAGE DIMENSION
0.063 (1.60)
MAX
SEATING
PLANE
0.003 (0.008)
MAX LEAD
COPLANARITY
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
7
8
0
8
0.057
(1.45)
0.055
(1.40)
0.053
(1.35)
0.006 (0.15)
0.002 (0.05)
TOP VIEW
(PINS DOWN)
1
16
17
33
32
48
49
64
0.016 (0.4)
BSC
0.354 (9.00) BSC
SQ
0.276
(7.00)
BSC
SQ
0.009 (0.23)
0.007 (0.18)
0.005 (0.13)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
ST-64A
64-Lead Thin Plastic Quad Flatpack [LQFP]
7 X 7mm Body, 1.4mm Thick
PRELIMINARY TECHNICAL DATA
