To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. R8C/2K Group, R8C/2L Group RENESAS MCU 1. REJ03B0219-0110 Rev.1.10 Dec 21, 2007 Overview 1.1 Features The R8C/2K Group and R8C/2L Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing. Power consumption is low, and the supported operating modes allow additional power control. These MCUs also use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI. Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of system components. Furthermore, the R8C/2L Group has on-chip data flash (1 KB x 2 blocks). The difference between the R8C/2K Group and R8C/2L Group is only the presence or absence of data flash. Their peripheral functions are the same. 1.1.1 Applications Electronic household appliances, office equipment, audio equipment, consumer equipment, etc. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 1 of 45 R8C/2K Group, R8C/2L Group 1.1.2 1. Overview Specifications Tables 1.1 and 1.2 outlines the Specifications for R8C/2K Group and Tables 1.3 and 1.4 outlines the Specifications for R8C/2L Group. Table 1.1 Item CPU Specifications for R8C/2K Group (1) Function Central processing unit Memory Power Supply Voltage Detection I/O Ports ROM, RAM Voltage detection circuit Clock Clock generation circuits Programmable I/O ports Interrupts Watchdog Timer Timer Timer RA Timer RB Timer RC Timer RD Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Specification R8C/Tiny series core * Number of fundamental instructions: 89 * Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) * Multiplier: 16 bits x 16 bits 32 bits * Multiply-accumulate instruction: 16 bits x 16 bits + 32 bits 32 bits * Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.5 Product List for R8C/2K Group. * Power-on reset * Voltage detection 3 * Input-only: 3 pins * CMOS I/O ports: 25, selectable pull-up resistor * High current drive ports: 8 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function) * Oscillation stop detection: XIN clock oscillation stop detection function * Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 * Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode * External: 4 sources, Internal: 15 sources, Software: 4 sources * Priority levels: 7 levels 15 bits x 1 (with prescaler), reset start selectable 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits x 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits x 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) Page 2 of 45 R8C/2K Group, R8C/2L Group Table 1.2 1. Overview Specifications for R8C/2K Group (2) Item Function Serial UART0, UART2 Interface LIN Module A/D Converter Flash Memory Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature Package Specification Clock synchronous serial I/O/UART x 2 Hardware LIN: 1 (timer RA, UART0) 10-bit resolution x 9 channels, includes sample and hold function * Programming and erasure voltage: VCC = 2.7 to 5.5 V * Programming and erasure endurance: 100 times * Program security: ROM code protect, ID code check * Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V) f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only) Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 23 A (VCC = 3.0 V, wait mode, low-speed on-chip oscillator used) Typ. 0.7 A (VCC = 3.0 V, stop mode) -20 to 85C (N version) -40 to 85C (D version)(1) -20 to 105C (Y version)(2) 32-pin LQFP * Package code: PLQP0032GB-A (previous code: 32P6U-A) NOTES: 1. Specify the D version if D version functions are to be used. 2. Please contact Renesas Technology sales offices for the Y version. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 3 of 45 R8C/2K Group, R8C/2L Group Table 1.3 Item CPU 1. Overview Specifications for R8C/2L Group (1) Function Central processing unit Memory Power Supply Voltage Detection I/O Ports ROM, RAM Voltage detection circuit Clock Clock generation circuits Programmable I/O ports Interrupts Watchdog Timer Timer Timer RA Timer RB Timer RC Timer RD Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Specification R8C/Tiny series core * Number of fundamental instructions: 89 * Minimum instruction execution time: 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) 200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) * Multiplier: 16 bits x 16 bits 32 bits * Multiply-accumulate instruction: 16 bits x 16 bits + 32 bits 32 bits * Operation mode: Single-chip mode (address space: 1 Mbyte) Refer to Table 1.6 Product List for R8C/2L Group. * Power-on reset * Voltage detection 3 * Input-only: 3 pins * CMOS I/O ports: 25, selectable pull-up resistor * High current drive ports: 8 2 circuits: XIN clock oscillation circuit (with on-chip feedback resistor), On-chip oscillator (high-speed, low-speed) (high-speed on-chip oscillator has a frequency adjustment function) * Oscillation stop detection: XIN clock oscillation stop detection function * Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16 * Low power consumption modes: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode * External: 4 sources, Internal: 15 sources, Software: 4 sources * Priority levels: 7 levels 15 bits x 1 (with prescaler), reset start selectable 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), pulse output mode (output level inverted every period), event counter mode, pulse width measurement mode, pulse period measurement mode 8 bits x 1 (with 8-bit prescaler) Timer mode (period timer), programmable waveform generation mode (PWM output), programmable one-shot generation mode, programmable wait oneshot generation mode 16 bits x 1 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 3 pins), PWM2 mode (PWM output pin) 16 bits x 2 (with 4 capture/compare registers) Timer mode (input capture function, output compare function), PWM mode (output 6 pins), reset synchronous PWM mode (output three-phase waveforms (6 pins), sawtooth wave modulation), complementary PWM mode (output three-phase waveforms (6 pins), triangular wave modulation), PWM3 mode (PWM output 2 pins with fixed period) Page 4 of 45 R8C/2K Group, R8C/2L Group Table 1.4 1. Overview Specifications for R8C/2L Group (2) Item Function Serial UART0, UART2 Interface LIN Module A/D Converter Flash Memory Operating Frequency/Supply Voltage Current consumption Operating Ambient Temperature Package Specification Clock synchronous serial I/O/UART x 2 Hardware LIN: 1 (timer RA, UART0) 10-bit resolution x 9 channels, includes sample and hold function * Programming and erasure voltage: VCC = 2.7 to 5.5 V * Programming and erasure endurance: 10,000 times (data flash) 1,000 times (program ROM) * Program security: ROM code protect, ID code check * Debug functions: On-chip debug, on-board flash rewrite function f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V) f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V) f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V) (VCC = 2.7 to 5.5 V for A/D converter only) Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz) Typ. 23 A (VCC = 3.0 V, wait mode, low-speed on-chip oscillator used) Typ. 0.7 A (VCC = 3.0 V, stop mode) -20 to 85C (N version) -40 to 85C (D version)(1) -20 to 105C (Y version)(2) 32-pin LQFP * Package code: PLQP0032GB-A (previous code: 32P6U-A) NOTES: 1. Specify the D version if D version functions are to be used. 2. Please contact Renesas Technology sales offices for the Y version. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 5 of 45 R8C/2K Group, R8C/2L Group 1.2 1. Overview Product List Table 1.5 lists the Product List for R8C/2K Group, Figure 1.1 shows a Part Number, Memory Size, and Package of R8C/2K Group, Table 1.6 lists the Product List for R8C/2L Group, and Figure 1.2 shows a Part Number, Memory Size, and Package of R8C/2L Group. Table 1.5 Product List for R8C/2K Group Part No. R5F212K2SNFP R5F212K4SNFP R5F212K2SDFP R5F212K4SDFP R5F212K2SNXXXFP (D) ROM Capacity 8 Kbytes 16 Kbytes 8 Kbytes 16 Kbytes 8 Kbytes Current of Dec. 2007 RAM Capacity 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte Package Type PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A PLQP0032GB-A R5F212K4SNXXXFP (D) 16 Kbytes 1.5 Kbytes PLQP0032GB-A R5F212K2SDXXXFP (D) 8 Kbytes 1 Kbyte PLQP0032GB-A R5F212K4SDXXXFP (D) 16 Kbytes 1.5 Kbytes PLQP0032GB-A Remarks N version D version N version Factory programming product(1) D version Factory programming product(1) (D): Under development NOTE: 1. The user ROM is programmed before shipment. Part No. R 5 F 21 2K 2 S N XXX FP Package type: FP: PLQP0032GB-A ROM number Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C Y: Operating ambient temperature -20C to 105C (1) S: Low-voltage version ROM capacity 2: 8 KB 4: 16 KB R8C/2K Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor NOTE: 1: Please contact Renesas Technology sales offices for the Y version. Figure 1.1 Part Number, Memory Size, and Package of R8C/2K Group Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 6 of 45 R8C/2K Group, R8C/2L Group Table 1.6 1. Overview Product List for R8C/2L Group Current of Dec. 2007 ROM Capacity Program ROM Data flash R5F212L2SNFP 8 Kbytes 1 Kbyte x 2 R5F212L4SNFP 16 Kbytes 1 Kbyte x 2 R5F212L2SDFP 8 Kbytes 1 Kbyte x 2 R5F212L4SDFP 16 Kbytes 1 Kbyte x 2 R5F212L2SNXXXFP (D) 8 Kbytes 1 Kbyte x 2 RAM Capacity 1 Kbyte 1.5 Kbytes 1 Kbyte 1.5 Kbytes 1 Kbyte R5F212L4SNXXXFP (D) 16 Kbytes 1 Kbyte x 2 1.5 Kbytes R5F212L2SDXXXFP (D) 8 Kbytes 1 Kbyte x 2 1 Kbyte R5F212L4SDXXXFP (D) 16 Kbytes 1 Kbyte x 2 1.5 Kbytes Part No. Package Type Remarks PLQP0032GB-A N version PLQP0032GB-A PLQP0032GB-A D version PLQP0032GB-A PLQP0032GB-A N version Factory PLQP0032GB-A programming product(1) PLQP0032GB-A D version Factory PLQP0032GB-A programming product(1) (D): Under development NOTE: 1. The user ROM is programmed before shipment. Part No. R 5 F 21 2L 2 S N XXX FP Package type: FP: PLQP0032GB-A ROM number Classification N: Operating ambient temperature -20C to 85C D: Operating ambient temperature -40C to 85C Y: Operating ambient temperature -20C to 105C (1) S: Low-voltage version ROM capacity 2: 8 KB 4: 16 KB R8C/2L Group R8C/Tiny Series Memory type F: Flash memory Renesas MCU Renesas semiconductor NOTE: 1: Please contact Renesas Technology sales offices for the Y version. Figure 1.2 Part Number, Memory Size, and Package of R8C/2L Group Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 7 of 45 R8C/2K Group, R8C/2L Group 1.3 1. Overview Block Diagram Figure 1.3 shows a Block Diagram. I/O ports 5 8 8 3 Port P0 Port P1 Port P2 Port P3 1 3 Port P4 Peripheral functions Timers Timer RA (8 bits x 1) Timer RB (8 bits x 1) Timer RC (16 bits x 1) Timer RD (16 bits x 2) UART or clock synchronous serial I/O (8 bits x 2) System clock generation circuit XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator LIN module Watchdog timer (15 bits) A/D converter (10 bits x 9 channels) R8C/Tiny Series CPU core R0H R1H R0L R1L R2 R3 SB ROM(1) USP ISP INTB A0 A1 FB Memory RAM(2) PC FLG Multiplier NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.3 Block Diagram Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 8 of 45 R8C/2K Group, R8C/2L Group 1.4 1. Overview Pin Assignment P4_5/INT0 P1_5/RXD0/(TRAIO)/(INT1)(2) P1_6/CLK0 P1_7/TRAIO/INT1 P1_2/KI2/AN10/TRCIOB P1_3/KI3/AN11/TRBO P1_4/TXD0 P1_1/KI1/AN9/TRCIOA/TRCTRG Figure 1.4 shows the Pin Assignment (Top View). Table 1.7 outlines the Pin Name Information by Pin Number. 24 23 22 21 20 19 18 17 16 26 15 14 27 R8C/2K Group R8C/2L Group 28 29 30 13 12 11 PLQP0032GB-A (32P6U-A) (top view) 2 3 4 5 6 10 9 7 8 P3_3/INT3/TRCCLK 1 RESET XOUT/P4_7 (1) VSS/AVSS XIN/P4_6 32 VCC/AVCC 31 MODE P3_5/TRCIOD P0_5/AN2 P0_3/AN4/CLK2 P0_2/AN5/RXD2 P0_1/AN6/TXD2 P0_0/AN7 25 VREF/P4_2 P1_0/KI0/AN8 P3_4/TRCIOC P2_0/TRDIOA0/TRDCLK P2_2/TRDIOC0 P2_1/TRDIOB0 P2_3/TRDIOD0 P2_4/TRDIOA1 P2_5/TRDIOB1 P2_6/TRDIOC1 P2_7/TRDIOD1 NOTES: 1. P4_7 are an input-only port. 2. Can be assigned to the pin in parentheses by a program. 3. Confirm the pin 1 position on the package by referring to the package dimensions. Figure 1.4 Pin Assignment (Top View) Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 9 of 45 R8C/2K Group, R8C/2L Group Table 1.7 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1. Overview Pin Name Information by Pin Number Control Pin Port VREF MODE RESET XOUT VSS/AVSS XIN VCC/AVCC P4_2 I/O Pin Functions for of Peripheral Modules Interrupt Timer INT3 TRCCLK TRDIOD1 TRDIOC1 TRDIOB1 TRDIOA1 TRDIOD0 TRDIOB0 TRDIOC0 TRDIOA0/TRDCLK A/D Converter P4_7 P4_6 P3_3 P2_7 P2_6 P2_5 P2_4 P2_3 P2_1 P2_2 P2_0 P4_5 P1_7 P1_6 P1_5 21 22 23 24 P1_4 P1_3 P1_2 P1_1 25 26 P1_0 P3_4 INT0 INT1 TRAIO (INT1)(1) (TRAIO)(1) KI3 KI2 KI1 TRBO TRCIOB TRCIOA/TRCTRG Page 10 of 45 CLK0 RXD0 TXD0 AN11 AN10 AN9 AN8 KI0 TRCIOC 27 P3_5 TRCIOD 28 P0_5 29 P0_3 30 P0_2 31 P0_1 32 P0_0 NOTE: 1. Can be assigned to the pin in parentheses by a program. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Serial Interface CLK2 RXD2 TXD2 AN2 AN4 AN5 AN6 AN7 R8C/2K Group, R8C/2L Group 1.5 1. Overview Pin Functions Table 1.8 lists Pin Functions. Table 1.8 Pin Functions Item Pin Name I/O Type Description Power supply input VCC, VSS - Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Analog power supply input AVCC, AVSS - Power supply for the A/D converter. Connect a capacitor between AVCC and AVSS. Reset input RESET I Input "L" on this pin resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. XIN clock input XIN I XIN clock output XOUT O These pins are provided for XIN clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins(1). To use an external clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input INT0, INT1, INT3 I INT interrupt input pins. INT0 is timer RB, timer RC and timer RD input pins. Key input interrupt KI0 to KI3 I Key input interrupt input pins Timer RA TRAIO I/O Timer RB TRBO O Timer RB output pin Timer RC TRCCLK I External clock input pin TRCTRG Timer RD External trigger input pin TRCIOA, TRCIOB, TRCIOC, TRCIOD I/O Timer RC I/O pins TRDIOA0, TRDIOA1, TRDIOB0, TRDIOB1, TRDIOC0, TRDIOC1, TRDIOD0, TRDIOD1 I/O Timer RD I/O pins TRDCLK Serial interface I Timer RA I/O pin I External clock input pin CLK0, CLK2 I/O RXD0, RXD2 I Serial data input pins Transfer clock I/O pins TXD0, TXD2 O Serial data output pins Reference voltage input VREF I Reference voltage input pin to A/D converter A/D converter AN2, AN4 to AN11 I Analog input pins to A/D converter I/O port P0_0 to P0_3, P0_5, P1_0 to P1_7, P2_0 to P2_7, P3_3 to P3_5, P4_5, Input port P4_2, P4_6, P4_7 I/O I CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P2_0 to P2_7 also function as LED drive ports. Input-only ports I: Input O: Output I/O: Input and output NOTE: 1. Refer to the oscillator manufacturer for oscillation characteristics. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 11 of 45 R8C/2K Group, R8C/2L Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 R2 R3 b8b7 b0 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers(1) R2 R3 A0 A1 FB b19 b15 Address registers(1) Frame base register(1) b0 Interrupt table register INTBL INTBH The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL. b19 b0 Program counter PC b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 b8 IPL b7 Flag register b0 U I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Registers Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 12 of 45 R8C/2K Group, R8C/2L Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide and indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when an operation results in an overflow; otherwise to 0. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 13 of 45 R8C/2K Group, R8C/2L Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 14 of 45 R8C/2K Group, R8C/2L Group 3. 3. Memory Memory 3.1 R8C/2K Group Figure 3.1 is a Memory Map of R8C/2K Group. The R8C/2K Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1.5-Kbyte internal RAM area is allocated addresses 00400h to 009FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h 002FFh SFR (Refer to 4. Special Function Registers (SFRs)) 00400h Internal RAM 0XXXh 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer/oscillation stop detection/voltage monitor 0YYYYh (Reserved) (Reserved) Reset Internal ROM (program ROM) 0FFFFh 0FFFFh FFFFFh NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Part Number R5F212K2SNFP, R5F212K2SDFP, R5F212K2SNXXXFP, R5F212K2SDXXXFP R5F212K4SNFP, R5F212K4SDFP, R5F212K4SNXXXFP, R5F212K4SDXXXFP Figure 3.1 Internal ROM Size Address 0YYYYh Size Address 0XXXXh 8 Kbytes 0E000h 1 Kbyte 007FFh 16 Kbytes 0C000h 1.5 Kbytes 009FFh Memory Map of R8C/2K Group Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 15 of 45 Internal RAM R8C/2K Group, R8C/2L Group 3.2 3. Memory R8C/2L Group Figure 3.2 is a Memory Map of R8C/2L Group. The R8C/2L Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1.5-Kbyte internal RAM is allocated addresses 00400h to 009FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h 002FFh SFR (Refer to 4. Special Function Registers (SFRs)) 00400h Internal RAM 0XXXXh 02400h 0FFDCh Internal ROM (data flash)(1) 02BFFh Undefined instruction Overflow BRK instruction Address match Single step 0YYYYh Watchdog timer/oscillation stop detection/voltage monitor (Reserved) (Reserved) Reset Internal ROM (program ROM) 0FFFFh 0FFFFh FFFFFh NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. R5F212L2SNFP, R5F212L2SDFP, R5F212L2SNXXXFP, R5F212L2SDXXXFP R5F212L4SNFP, R5F212L4SDFP, R5F212L4SNXXXFP, R5F212L4SDXXXFP Figure 3.2 Size Address 0YYYYh Size Address 0XXXXh 8 Kbytes 0E000h 1 Kbyte 007FFh 16 Kbytes 0C000h 1.5 Kbytes 009FFh Memory Map of R8C/2L Group Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 16 of 45 Internal RAM Internal ROM Part Number R8C/2K Group, R8C/2L Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers. Table 4.1 Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch SFR Information (1)(1) Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01101000b 00100000b Protect Register PRCR 00h Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 OCD WDTR WDTS WDC RMAD0 Address Match Interrupt Enable Register Address Match Interrupt Register 1 AIER RMAD1 00000100b XXh XXh 00X11111b 00h 00h 00h 00h 00h 00h 00h Count Source Protection Mode Register CSPR 00h 10000000b(6) High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 FRA0 FRA1 FRA2 00h When shipping 00h High-Speed On-Chip Oscillator Control Register 6 High-Speed On-Chip Oscillator Control Register 7 FRA6 FRA7 When Shipping When Shipping 0030h 0031h 0032h Voltage Detection Register 1(2) Voltage Detection Register 2(2) VCA1 VCA2 00001000b 00h(3) 00100000b(4) 0033h 0034h 0035h 0036h 0037h 0038h Voltage Monitor 1 Circuit Control Register(5) Voltage Monitor 2 Circuit Control Register(5) Voltage Monitor 0 Circuit Control Register(2) VW1C VW2C VW0C 00001000b 00h 0000X000b(3) 0100X001b(4) 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 0039h 003Ah 003Eh 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register. 3. The LVD0ON bit in the OFS register is set to 1 and hardware reset. 4. Power-on reset, voltage monitor 0 reset, or the LVD0ON bit in the OFS register is set to 0 and hardware reset. 5. Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3. 6. The CSPROINI bit in the OFS register is set to 0. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 17 of 45 R8C/2K Group, R8C/2L Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 4. Special Function Registers (SFRs) SFR Information (2)(1) Register Symbol After reset Timer RC Interrupt Control Register Timer RD0 Interrupt Control Register Timer RD1 Interrupt Control Register TRCIC TRD0IC TRD1IC XXXXX000b XXXXX000b XXXXX000b UART2 Transmit Interrupt Control Register UART2 Receive Interrupt Control Register Key Input Interrupt Control Register A/D Conversion Interrupt Control Register S2TIC S2RIC KUPIC ADIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register S0TIC S0RIC XXXXX000b XXXXX000b Timer RA Interrupt Control Register TRAIC XXXXX000b Timer RB Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register TRBIC INT1IC INT3IC XXXXX000b XX00X000b XX00X000b INT0 Interrupt Control Register INT0IC XX00X000b X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 18 of 45 R8C/2K Group, R8C/2L Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4. Special Function Registers (SFRs) SFR Information (3)(1) Register Symbol UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register U0MR U0BRG U0TB UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0C0 U0C1 U0RB X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 19 of 45 After reset 00h XXh XXh XXh 00001000b 00000010b XXh XXh R8C/2K Group, R8C/2L Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 4. Special Function Registers (SFRs) SFR Information (4)(1) Register Symbol After reset A/D Register AD XXh XXh A/D Control Register 2 ADCON2 00h A/D Control Register 0 A/D Control Register 1 ADCON0 ADCON1 00h 00h Port P0 Register Port P1 Register Port P0 Direction Register Port P1 Direction Register Port P2 Register Port P3 Register Port P2 Direction Register Port P3 Direction Register Port P4 Register P0 P1 PD0 PD1 P2 P3 PD2 PD3 P4 XXh XXh 00h 00h XXh XXh 00h 00h XXh Port P4 Direction Register PD4 00h Port P2 Drive Capacity Control Register Pin Select Register 1 Pin Select Register 2 Pin Select Register 3 Port Mode Register External Input Enable Register INT Input Filter Select Register Key Input Enable Register Pull-Up Control Register 0 Pull-Up Control Register 1 P2DRR PINSR1 PINSR2 PINSR3 PMR INTEN INTF KIEN PUR0 PUR1 00h XXh XXh XXh 00h 00h 00h 00h 00h XX000000b X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 20 of 45 R8C/2K Group, R8C/2L Group Table 4.5 Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh NOTE: 1. 4. Special Function Registers (SFRs) SFR Information (5)(1) Timer RA Control Register Timer RA I/O Control Register Timer RA Mode Register Timer RA Prescaler Register Timer RA Register LIN Control Register 2 LIN Control Register LIN Status Register Timer RB Control Register Timer RB One-Shot Control Register Timer RB I/O Control Register Timer RB Mode Register Timer RB Prescaler Register Timer RB Secondary Register Timer RB Primary Register Register Symbol TRACR TRAIOC TRAMR TRAPRE TRA LINCR2 LINCR LINST TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR Timer RC Mode Register Timer RC Control Register 1 Timer RC Interrupt Enable Register Timer RC Status Register Timer RC I/O Control Register 0 Timer RC I/O Control Register 1 Timer RC Counter TRCMR TRCCR1 TRCIER TRCSR TRCIOR0 TRCIOR1 TRC Timer RC General Register A TRCGRA Timer RC General Register B TRCGRB Timer RC General Register C TRCGRC Timer RC General Register D TRCGRD Timer RC Control Register 2 Timer RC Digital Filter Function Select Register Timer RC Output Master Enable Register TRCCR2 TRCDF TRCOER 01001000b 00h 01110000b 01110000b 10001000b 10001000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00011111b 00h 01111111b Timer RD Start Register Timer RD Mode Register Timer RD PWM Mode Register Timer RD Function Control Register Timer RD Output Master Enable Register 1 Timer RD Output Master Enable Register 2 Timer RD Output Control Register Timer RD Digital Filter Function Select Register 0 Timer RD Digital Filter Function Select Register 1 TRDSTR TRDMR TRDPMR TRDFCR TRDOER1 TRDOER2 TRDOCR TRDDF0 TRDDF1 11111100b 00001110b 10001000b 10000000b FFh 01111111b 00h 00h 00h The blank regions are reserved. Do not access locations in these regions Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 21 of 45 After reset 00h 00h 00h FFh FFh 00h 00h 00h 00h 00h 00h 00h FFh FFh FFh R8C/2K Group, R8C/2L Group Table 4.6 Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014Fh 0150h 0151h 0152h 0153h 0154h 0155h 0156h 0157h 0158h 0159h 015Ah 015Bh 015Ch 015Dh 015Eh 015Fh 0160h 0161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh 4. Special Function Registers (SFRs) SFR Information (6)(1) Register Timer RD Control Register 0 Timer RD I/O Control Register A0 Timer RD I/O Control Register C0 Timer RD Status Register 0 Timer RD Interrupt Enable Register 0 Timer RD PWM Mode Output Level Control Register 0 Timer RD Counter 0 Symbol TRDCR0 TRDIORA0 TRDIORC0 TRDSR0 TRDIER0 TRDPOCR0 TRD0 Timer RD General Register A0 TRDGRA0 Timer RD General Register B0 TRDGRB0 Timer RD General Register C0 TRDGRC0 Timer RD General Register D0 TRDGRD0 Timer RD Control Register 1 Timer RD I/O Control Register A1 Timer RD I/O Control Register C1 Timer RD Status Register 1 Timer RD Interrupt Enable Register 1 Timer RD PWM Mode Output Level Control Register 1 Timer RD Counter 1 TRDCR1 TRDIORA1 TRDIORC1 TRDSR1 TRDIER1 TRDPOCR1 TRD1 Timer RD General Register A1 TRDGRA1 Timer RD General Register B1 TRDGRB1 Timer RD General Register C1 TRDGRC1 Timer RD General Register D1 TRDGRD1 UART2 Transmit/Receive Mode Register UART2 Bit Rate Register UART2 Transmit Buffer Register U2MR U2BRG U2TB UART2 Transmit/Receive Control Register 0 UART2 Transmit/Receive Control Register 1 UART2 Receive Buffer Register U2C0 U2C1 U2RB X: Undefined NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 22 of 45 After reset 00h 10001000b 10001000b 11100000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h 10001000b 10001000b 11000000b 11100000b 11111000b 00h 00h FFh FFh FFh FFh FFh FFh FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh R8C/2K Group, R8C/2L Group Table 4.7 Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh FFFFh 4. Special Function Registers (SFRs) SFR Information (7)(1) Register Symbol After reset Flash Memory Control Register 4 FMR4 01000000b Flash Memory Control Register 1 FMR1 1000000Xb Flash Memory Control Register 0 FMR0 00000001b Option Function Select Register OFS (Note 2) X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a program. Use a flash programmer to write to it. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 23 of 45 R8C/2K Group, R8C/2L Group 5. 5. Electrical Characteristics Electrical Characteristics The electrical characteristics of N version (Topr = -20C to 85C) and D version (Topr = -40C to 85C) are listed below. Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20C to 105C). Table 5.1 Absolute Maximum Ratings Symbol Parameter Rated Value Unit -0.3 to 6.5 V Input voltage -0.3 to VCC + 0.3 V VO Output voltage -0.3 to VCC + 0.3 V Pd Power dissipation 500 mW Topr Operating ambient temperature -20 to 85 (N version) / -40 to 85 (D version) C Tstg Storage temperature -65 to 150 C VCC/AVCC Supply voltage VI Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 24 of 45 Condition Topr = 25C R8C/2K Group, R8C/2L Group Table 5.2 Recommended Operating Conditions Symbol VCC AVCC VSS/AVSS VIH VIL IOH(sum) IOH(sum) IOH(peak) Supply voltage Supply voltage Supply voltage Input "H" voltage Input "L" voltage Peak sum output "H" current Average sum output "H" current Peak output "H" current Average output "H" current IOL(sum) Peak sum output "L" currents Average sum output "L" currents Peak output "L" currents IOL(peak) Sum of all pins IOH(peak) Min. 2.2 2.7 - 0.8 VCC 0 - Standard Typ. - - 0 - - - Max. 5.5 5.5 - VCC 0.2 VCC -160 Sum of all pins IOH(avg) - - -80 mA Except P2_0 to P2_7 P2_0 to P2_7 Except P2_0 to P2_7 P2_0 to P2_7 Sum of all pins IOL(peak) - - - - - - - - - - -10 -40 -5 -20 160 mA mA mA mA mA Sum of all pins IOL(avg) - - 80 mA - - - - 0 0 0 0 0 0 - - - - - - - - - - - 125 10 40 5 20 20 10 5 20 10 5 - mA mA mA mA MHz MHz MHz MHz MHz MHz kHz - - 20 MHz - - 10 MHz - - 5 MHz Parameter IOH(avg) IOL(sum) 5. Electrical Characteristics f(XIN) Except P2_0 to P2_7 P2_0 to P2_7 Average output Except P2_0 to P2_7 "L" current P2_0 to P2_7 XIN clock input oscillation frequency - System clock IOL(avg) OCD2 = 0 XlN clock selected OCD2 = 1 On-chip oscillator clock selected Conditions 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V 3.0 V VCC 5.5 V 2.7 V VCC < 3.0 V 2.2 V VCC < 2.7 V FRA01 = 0 Low-speed on-chip oscillator clock selected FRA01 = 1 High-speed on-chip oscillator clock selected 3.0 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.7 V VCC 5.5 V FRA01 = 1 High-speed on-chip oscillator clock selected 2.2 V VCC 5.5 V NOTES: 1. VCC = 2.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. The average output current indicates the average value of current measured during 100 ms. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 25 of 45 Unit V V V V mA R8C/2K Group, R8C/2L Group Table 5.3 5. Electrical Characteristics A/D Converter Characteristics Symbol Parameter - Resolution - Absolute accuracy Conditions Standard Min. Typ. Max. Unit Vref = AVCC - - 10 Bits 10-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V - - 3 LSB 8-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V - - 2 LSB 10-bit mode AD = 10 MHz, Vref = AVCC = 3.3 V - - 5 LSB 8-bit mode AD = 10 MHz, Vref = AVCC = 3.3 V - - 2 LSB Rladder Resistor ladder Vref = AVCC 10 - 40 k tconv Conversion time 10-bit mode AD = 10 MHz, Vref = AVCC = 5.0 V 3.3 - - s AD = 10 MHz, Vref = AVCC = 5.0 V 2.8 - - s 2.2 - AVCC V 0 - AVCC V 8-bit mode Vref Reference voltage VIA Analog input voltage(2) - A/D operating clock frequency Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 - 10 MHz With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 - 10 MHz NOTES: 1. AVCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. P0 P1 P2 P3 P4 Figure 5.1 Ports P0 to P4 Timing Measurement Circuit Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 26 of 45 30pF R8C/2K Group, R8C/2L Group Table 5.4 Flash Memory (Program ROM) Electrical Characteristics Symbol - 5. Electrical Characteristics Parameter Program/erase endurance(2) Conditions Standard Unit Min. Typ. Max. R8C/2K Group 100(3) - - times R8C/2L Group 1,000(3) - - times s - Byte program time - 50 400 - Block erase time - 0.4 9 s td(SR-SUS) Time delay from suspend request until suspend - - 97+CPU clock x 6 cycles s - Interval from erase start/restart until following suspend request 650 - - s - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3+CPU clock x 4 cycles s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.2 - 5.5 V - Program, erase temperature 0 - 60 C - Data hold time(7) 20 - - year Ambient temperature = 55C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 7. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 27 of 45 R8C/2K Group, R8C/2L Group Table 5.5 5. Electrical Characteristics Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4) Symbol Parameter Conditions Standard Min. Typ. Max. Unit 10,000(3) - - times Byte program time (program/erase endurance 1,000 times) - 50 400 s - Byte program time (program/erase endurance > 1,000 times) - 65 - s - Block erase time (program/erase endurance 1,000 times) - 0.2 9 s - Block erase time (program/erase endurance > 1,000 times) - 0.3 - s td(SR-SUS) Time delay from suspend request until suspend - - 97+CPU clock x 6 cycles s - Interval from erase start/restart until following suspend request 650 - - s - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3+CPU clock x 4 cycles s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.2 - 5.5 V - Program, erase temperature -20(8) - 85 C - Data hold time(9) 20 - - year - Program/erase endurance(2) - Ambient temperature = 55 C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times is the same as that in program ROM. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative. 8. -40C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 28 of 45 R8C/2K Group, R8C/2L Group 5. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Clock-dependent time Fixed time Access restart td(SR-SUS) Figure 5.2 Table 5.6 Time delay until Suspend Voltage Detection 0 Circuit Electrical Characteristics Symbol Parameter Vdet0 Voltage detection level - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(2) Vccmin MCU operating voltage minimum value Condition VCA25 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 2.2 2.3 2.4 V - 0.9 - A - - 300 s 2.2 - - V NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2 register to 0. Table 5.7 Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Vdet1 Voltage detection level(4) - Voltage monitor 1 interrupt request generation time(2) - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(3) Condition VCA26 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 2.70 2.85 3.00 V - 40 - s - 0.6 - A - - 100 s NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 4. This parameter shows the voltage detection level when the power supply drops. The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply drops by approximately 0.1 V. Table 5.8 Voltage Detection 2 Circuit Electrical Characteristics Symbol Parameter Vdet2 Voltage detection level - Voltage monitor 2 interrupt request generation time(2) - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(3) Condition VCA27 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 3.3 3.6 3.9 V - 40 - s - 0.6 - A - - 100 s NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85C (N version) / -40 to 85C (D version). 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 29 of 45 R8C/2K Group, R8C/2L Group Table 5.9 5. Electrical Characteristics Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3) Symbol Parameter Condition Standard Min. Typ. Unit Max. Vpor1 Power-on reset valid voltage(4) - - 0.1 V Vpor2 Power-on reset or voltage monitor 0 reset valid voltage 0 - Vdet0 V trth External power VCC rise gradient(2) 20 - - mV/msec NOTES: 1. The measurement condition is Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. This condition (external power VCC rise gradient) does not apply if VCC 1.0 V. 3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1. 4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20C Topr 85C, maintain tw(por1) for 3,000 s or more if -40C Topr < -20C. Vdet0(3) Vdet0(3) 2.2V trth trth External Power VCC Vpor2 Vpor1 Sampling time(1, 2) tw(por1) Internal reset signal ("L" valid) 1 x 32 fOCO-S 1 x 32 fOCO-S NOTES: 1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage range (2.2 V or above) during the sampling time. 2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit for details. 3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection Circuit for details. Figure 5.3 Reset Circuit Electrical Characteristics Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 30 of 45 R8C/2K Group, R8C/2L Group Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol fOCO40M 5. Electrical Characteristics Parameter High-speed on-chip oscillator frequency temperature * supply voltage dependence High-speed on-chip oscillator frequency when correction value in FRA7 register is written to FRA1 register(4) - Value in FRA1 register after reset - Oscillation frequency adjustment unit of highspeed on-chip oscillator - - Condition Standard Unit Min. Typ. Max. VCC = 2.7 V to 5.5 V -20C Topr 85C(2) 39.2 40 40.8 MHz VCC = 2.7 V to 5.5 V -40C Topr 85C(2) 39.0 40 41.0 MHz VCC = 2.2 V to 5.5 V -20C Topr 85C(3) 35.2 40 44.8 MHz VCC = 2.2 V to 5.5 V -40C Topr 85C(3) 34.0 40 46.0 MHz - 36.864 - MHz -3% - 3% % VCC = 5.0 V, Topr = 25C VCC = 2.7 V to 5.5 V -20C Topr 85C 08h - F7h - Adjust FRA1 register (value after reset) to -1 - +0.3 - MHz Oscillation stability time VCC = 5.0 V, Topr = 25C - 10 100 s Self power consumption at oscillation VCC = 5.0 V, Topr = 25C - 550 - A NOTES: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. 2. These standard values show when the FRA1 register value after reset is assumed. 3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register. 4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in UART mode. Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit fOCO-S Low-speed on-chip oscillator frequency 30 125 250 - Oscillation stability time - 10 100 s - Self power consumption at oscillation - 15 - A VCC = 5.0 V, Topr = 25C kHz NOTE: 1. VCC = 2.2 to 5.5 V, Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified. Table 5.12 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit td(P-R) Time for internal power supply stabilization during power-on(2) 1 - 2000 s td(R-S) STOP exit time(3) - - 150 s NOTES: 1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 31 of 45 R8C/2K Group, R8C/2L Group Table 5.13 Electrical Characteristics (1) [VCC = 5 V] Symbol VOH 5. Electrical Characteristics Parameter Output "H" voltage Condition Typ. Max. Unit Except P2_0 to P2_7, XOUT IOH = -5 mA VCC - 2.0 - VCC V IOH = -200 A VCC - 0.5 - VCC V P2_0 to P2_7 Drive capacity HIGH IOH = -20 mA VCC - 2.0 - VCC V IOH = -5 mA VCC - 2.0 - VCC V Drive capacity HIGH IOH = -1 mA VCC - 2.0 - VCC V VCC - 2.0 - VCC V - - 2.0 V Drive capacity LOW XOUT Drive capacity LOW VOL Standard Min. Output "L" voltage Except P2_0 to P2_7, XOUT P2_0 to P2_7 IOL = 5 mA IOL = 200 A - - 0.45 V Drive capacity HIGH IOL = 20 mA - - 2.0 V IOL = 5 mA - - 2.0 V Drive capacity HIGH IOL = 1 mA - - 2.0 V - - 2.0 V 0.1 0.5 - V 0.1 1.0 - V - - 5.0 A Drive capacity LOW XOUT IOH = -500 A Drive capacity LOW IOL = 500 A VT+-VT- Hysteresis IIH Input "H" current VI = 5 V, VCC = 5 V IIL Input "L" current VI = 0 V, VCC = 5 V - - -5.0 A VI = 0 V, VCC = 5 V 30 50 167 k - 1.0 - M 1.8 - - V INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD2, CLK0, CLK2 RESET RPULLUP Pull-up resistance RfXIN Feedback resistance VRAM RAM hold voltage XIN During stop mode NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 20 MHz, unless otherwise specified. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 32 of 45 R8C/2K Group, R8C/2L Group Table 5.14 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Power supply High-speed current clock mode (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 33 of 45 Standard Unit Min. Typ. Max. XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 10 17 mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 9 15 mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 6 - mA XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 5 - mA XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 4 - mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 2.5 - mA XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz No division - 10 15 mA XIN clock off High-speed on-chip oscillator on fOCO = 20 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 4 - mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division - 5.5 10 mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 2.5 - mA XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 - 130 300 A R8C/2K Group, R8C/2L Group Table 5.15 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (3) [Vcc = 5 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Power supply Wait mode current (VCC = 3.3 to 5.5 V) Single-chip mode, output pins are open, other pins are VSS Stop mode Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 34 of 45 Standard Unit Min. Typ. Max. XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 25 75 A XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 23 60 A XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 0.8 3.0 A XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 1.2 - A R8C/2K Group, R8C/2L Group 5. Electrical Characteristics Timing Requirements (Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25C) [VCC = 5 V] Table 5.16 XIN Input Symbol Standard Parameter Min. Max. Unit tc(XIN) XIN input cycle time 50 - ns tWH(XIN) XIN input "H" width 25 - ns tWL(XIN) XIN input "L" width 25 - ns VCC = 5 V tC(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.4 Table 5.17 XIN Input Timing Diagram when VCC = 5 V TRAIO Input Symbol Standard Parameter Min. Max. Unit tc(TRAIO) TRAIO input cycle time 100 - ns tWH(TRAIO) TRAIO input "H" width 40 - ns tWL(TRAIO) TRAIO input "L" width 40 - ns tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.5 TRAIO Input Timing Diagram when VCC = 5 V Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 35 of 45 VCC = 5 V R8C/2K Group, R8C/2L Group Table 5.18 5. Electrical Characteristics Serial Interface Symbol Standard Parameter Min. Max. Unit tc(CK) CLKi input cycle time 200 - ns tW(CKH) CLKi input "H" width 100 - ns tW(CKL) CLKi input "L" width 100 - ns td(C-Q) TXDi output delay time - 50 ns th(C-Q) TXDi hold time 0 - ns tsu(D-C) RXDi input setup time 50 - ns th(C-D) RXDi input hold time 90 - ns i = 0, 2 VCC = 5 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.6 Table 5.19 Serial Interface Timing Diagram when VCC = 5 V External Interrupt INTi (i = 0, 1, 3) Input Symbol Standard Parameter Min. Max. Unit tW(INH) INTi input "H" width 250(1) - ns tW(INL) INTi input "L" width 250(2) - ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.7 External Interrupt INTi Input Timing Diagram when VCC = 5 V Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 36 of 45 R8C/2K Group, R8C/2L Group Table 5.20 Electrical Characteristics (1) [VCC = 3 V] Symbol VOH 5. Electrical Characteristics Parameter Output "H" voltage Output "L" voltage Standard Unit Min. Typ. Max. VCC - 0.5 - VCC V Except P2_0 to P2_7, XOUT IOH = -1 mA P2_0 to P2_7 Drive capacity HIGH IOH = -5 mA VCC - 0.5 - VCC V Drive capacity LOW IOH = -1 mA VCC - 0.5 - VCC V Drive capacity HIGH IOH = -0.1 mA VCC - 0.5 - VCC V Drive capacity LOW IOH = -50 A VCC - 0.5 - VCC V - - 0.5 V XOUT VOL Condition Except P2_0 to P2_7, XOUT IOL = 1 mA P2_0 to P2_7 Drive capacity HIGH IOL = 5 mA - - 0.5 V Drive capacity LOW IOL = 1 mA - - 0.5 V Drive capacity HIGH IOL = 0.1 mA - - 0.5 V Drive capacity LOW IOL = 50 A - - 0.5 V 0.1 0.3 - V 0.1 0.4 - V - - 4.0 A XOUT VT+-VT- Hysteresis IIH Input "H" current VI = 3 V, VCC = 3 V IIL Input "L" current VI = 0 V, VCC = 3 V - - -4.0 A VI = 0 V, VCC = 3 V 66 160 500 k - 3.0 - M During stop mode 1.8 - - V INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD2, CLK0, CLK2 RESET RPULLUP Pull-up resistance RfXIN Feedback resistance VRAM RAM hold voltage XIN NOTE: 1. VCC =2.7 to 3.3 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 10 MHz, unless otherwise specified. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 37 of 45 R8C/2K Group, R8C/2L Group Table 5.21 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 3 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Unit Typ. Max. XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 6 - mA XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 2 - mA High-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz No division - 5 9 mA XIN clock off High-speed on-chip oscillator on fOCO = 10 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 2 - mA Low-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 - 130 300 A Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 25 70 A XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 23 55 A XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 0.7 3.0 A XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 1.1 - A Power supply current High-speed (VCC = 2.7 to 3.3 V) clock mode Single-chip mode, output pins are open, other pins are VSS Stop mode Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Standard Min. Page 38 of 45 R8C/2K Group, R8C/2L Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25C) [VCC = 3 V] Table 5.22 XIN Input Symbol Standard Parameter Min. Max. Unit tc(XIN) XIN input cycle time 100 - ns tWH(XIN) XIN input "H" width 40 - ns tWL(XIN) XIN input "L" width 40 - ns VCC = 3 V tC(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.8 XIN Input Timing Diagram when VCC = 3 V Table 5.23 TRAIO Input Symbol Standard Parameter Min. Max. Unit tc(TRAIO) TRAIO input cycle time 300 - ns tWH(TRAIO) TRAIO input "H" width 120 - ns tWL(TRAIO) TRAIO input "L" width 120 - ns tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.9 TRAIO Input Timing Diagram when VCC = 3 V Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 39 of 45 VCC = 3 V R8C/2K Group, R8C/2L Group Table 5.24 5. Electrical Characteristics Serial Interface Symbol Standard Parameter Min. Max. Unit tc(CK) CLKi input cycle time 300 - ns tW(CKH) CLKi input "H" width 150 - ns tW(CKL) CLKi Input "L" width 150 - ns td(C-Q) TXDi output delay time - 80 ns th(C-Q) TXDi hold time 0 - ns tsu(D-C) RXDi input setup time 70 - ns th(C-D) RXDi input hold time 90 - ns i = 0, 2 VCC = 3 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.10 Table 5.25 Serial Interface Timing Diagram when VCC = 3 V External Interrupt INTi (i = 0, 1, 3) Input Symbol Standard Parameter Min. Max. Unit tW(INH) INTi input "H" width 380(1) - ns tW(INL) INTi input "L" width 380(2) - ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 3 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.11 External Interrupt INTi Input Timing Diagram when VCC = 3 V Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 40 of 45 R8C/2K Group, R8C/2L Group Table 5.26 Electrical Characteristics (1) [VCC = 2.2 V] Symbol VOH 5. Electrical Characteristics Parameter Output "H" voltage Output "L" voltage Standard Unit Min. Typ. Max. VCC - 0.5 - VCC V Except P2_0 to P2_7, XOUT IOH = -1 mA P2_0 to P2_7 Drive capacity HIGH IOH = -2 mA VCC - 0.5 - VCC V Drive capacity LOW IOH = -1 mA VCC - 0.5 - VCC V Drive capacity HIGH IOH = -0.1 mA VCC - 0.5 - VCC V Drive capacity LOW IOH = -50 A VCC - 0.5 - VCC V - - 0.5 V XOUT VOL Condition Except P2_0 to P2_7, XOUT IOL = 1 mA P2_0 to P2_7 Drive capacity HIGH IOL = 2 mA - - 0.5 V Drive capacity LOW IOL = 1 mA - - 0.5 V Drive capacity HIGH IOL = 0.1 mA - - 0.5 V Drive capacity LOW IOL = 50 A - - 0.5 V 0.05 0.3 - V 0.05 0.15 - V - - 4.0 A XOUT VT+-VT- Hysteresis IIH Input "H" current VI = 2.2 V IIL Input "L" current VI = 0 V - - -4.0 A VI = 0 V 100 200 600 k - 5 - M During stop mode 1.8 - - V INT0, INT1, INT3, KI0, KI1, KI2, KI3, TRAIO, RXD0, RXD2, CLK0, CLK2 RESET RPULLUP Pull-up resistance RfXIN Feedback resistance VRAM RAM hold voltage XIN NOTE: 1. VCC = 2.2 V at Topr = -20 to 85C (N version) / -40 to 85C (D version), f(XIN) = 5 MHz, unless otherwise specified. Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 41 of 45 R8C/2K Group, R8C/2L Group Table 5.27 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 2.2 V] (Topr = -20 to 85C (N version) / -40 to 85C (D version), unless otherwise specified.) Parameter Condition Unit Typ. Max. XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division - 3.5 - mA XIN = 5 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 1.5 - mA XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz No division - 3.5 - mA XIN clock off High-speed on-chip oscillator on fOCO = 5 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 - 1.5 - mA Low-speed on-chip oscillator mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8, FMR47 = 1 - 100 230 A Wait mode XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 22 60 A XIN clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = VCA25 = 0 VCA20 = 1 - 20 55 A XIN clock off, Topr = 25C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 0.7 3.0 A XIN clock off, Topr = 85C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = VCA25 = 0 - 1.1 - A Power supply current High-speed (VCC = 2.2 to 2.7 V) clock mode Single-chip mode, output pins are open, other pins are VSS High-speed on-chip oscillator mode Stop mode Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Standard Min. Page 42 of 45 R8C/2K Group, R8C/2L Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25C) [VCC = 2.2 V] Table 5.28 XIN Input Symbol Standard Parameter Min. Max. Unit tc(XIN) XIN input cycle time 200 - ns tWH(XIN) XIN input "H" width 90 - ns tWL(XIN) XIN input "L" width 90 - ns VCC = 2.2 V tC(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.12 XIN Input Timing Diagram when VCC = 2.2 V Table 5.29 TRAIO Input Symbol Standard Parameter Min. Max. Unit tc(TRAIO) TRAIO input cycle time 500 - ns tWH(TRAIO) TRAIO input "H" width 200 - ns tWL(TRAIO) TRAIO input "L" width 200 - ns tC(TRAIO) tWH(TRAIO) TRAIO input tWL(TRAIO) Figure 5.13 TRAIO Input Timing Diagram when VCC = 2.2 V Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 43 of 45 VCC = 2.2 V R8C/2K Group, R8C/2L Group Table 5.30 5. Electrical Characteristics Serial Interface Symbol Standard Parameter Min. Max. Unit tc(CK) CLKi input cycle time 800 - ns tW(CKH) CLKi input "H" width 400 - ns tW(CKL) CLKi input "L" width 400 - ns td(C-Q) TXDi output delay time - 200 ns th(C-Q) TXDi hold time 0 - ns tsu(D-C) RXDi input setup time 150 - ns th(C-D) RXDi input hold time 90 - ns i = 0, 2 VCC = 2.2 V tC(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0, 2 Figure 5.14 Table 5.31 Serial Interface Timing Diagram when VCC = 2.2 V External Interrupt INTi (i = 0, 1, 3) Input Symbol tW(INH) tW(INL) Standard Parameter Unit Min. Max. INTi input "H" width 1000(1) - ns INTi input "L" width 1000(2) - ns NOTES: 1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 2.2 V tW(INL) INTi input tW(INH) i = 0, 1, 3 Figure 5.15 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V Rev.1.10 Dec 21, 2007 REJ03B0219-0110 Page 44 of 45 R8C/2K Group, R8C/2L Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website. JEITA Package Code P-LQFP32-7x7-0.80 RENESAS Code PLQP0032GB-A Previous Code 32P6U-A MASS[Typ.] 0.2g HD *1 D 24 17 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 16 25 bp c c1 HE *2 E b1 Reference Dimension in Millimeters Symbol 32 9 1 ZE Terminal cross section 8 ZD c A A1 F A2 Index mark L D E A2 HD HE A A1 bp b1 c c1 L1 y e Rev.1.10 Dec 21, 2007 REJ03B0219-0110 *3 Detail F bp Page 45 of 45 x e x y ZD ZE L L1 Min Nom Max 6.9 7.0 7.1 6.9 7.0 7.1 1.4 8.8 9.0 9.2 8.8 9.0 9.2 1.7 0.1 0.2 0 0.32 0.37 0.42 0.35 0.09 0.145 0.20 0.125 0 8 0.8 0.20 0.10 0.7 0.7 0.3 0.5 0.7 1.0 REVISION HISTORY REVISION HISTORY Rev. Date 0.10 Jul 20, 2007 1.00 Nov 07, 2007 1.10 Dec 21, 2007 R8C/2K Group, R8C/2L Group Datasheet R8C/2K Group, R8C/2L Group Datasheet Description Page - Summary First Edition issued All pages "Preliminary" deleted 3, 5 Table 1.2, Table 1.4; Current consumption: "TBD" "Typ. 10 mA" "Typ. 6 mA" "Typ. 2.0 A" "Typ. 0.7 A" revised 6, 7 Table 1.5, Table 1.6 revised Figure 1.1, Figure 1.2; ROM number "XXX" added, NOTE1 added 20 Table 4.4 "005Fh" "006Fh" "007Fh" "008Fh" added 24 Table 5.2 NOTE2 revised 32, 33 Table 5.14, Table 5.15 revised 37, 41 Table 5.21, Table 5.27 revised 3, 5 Table 1.2, Table 1.4; revised, NOTE2 added 6, 7 Figure 1.1, Figure 1.2; "Y: Operating ambient ....", NOTE1 added 15, 16 Figure 3.1, Figure 3.2; "Expanded area" deleted 17 Table 4.1 "002Ch" added, "003Bh" "003Ch" "003Dh" deleted 20 Table 4.4 "00D4h" "00D6h" revised 22 Table 4.6 "0143h" revised 24 5. "The electrical characteristics ...." added 31 Table 5.10 Symbol "fOCO40M": Parameter added, NOTE4 added All trademarks and registered trademarks are the property of their respective owners. C-1 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. 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