DATA SH EET
Product specification
File under Integrated Circuits, IC06 December 1990
INTEGRATED CIRCUITS
74HC/HCT03
Quad 2-input NAND gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
December 1990 2
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
FEATURES
•Level shift capability
•Output capability: standard (open drain)
•ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT03 provide the 2-input NAND function.
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to VCC. In
the OFF-state, i.e. when one input is LOW, the output
may be pulled to any voltage between GND and VOmax.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f= 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD × VCC2× fi+∑(CL×VCC2× fo) + ∑ (VO2/RL)× duty factor LOW, where:
fi= input frequency in MHz
fo= output frequency in MHz
VO= output voltage in V
CL= output load capacitance in pF
VCC = supply voltage in V
RL= pull-up resistor in MΩ
∑ (CL× VCC2× fo) = sum of outputs
∑ (VO2/RL) = sum of outputs
2. For HC the condition is VI= GND to VCC
For HCT the condition is VI= GND to VCC − 1.5 V
3. The given value of CPD is obtained with:
CL= 0 pF and RL=∞
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPZL/ tPLZ propagation delay CL= 15 pF; RL=1 kΩ; VCC = 5 V 8 10 ns
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per gate notes 1, 2 and 3 4.0 4.0 pF
December 1990 3
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 9, 12 1A to 4A data inputs
2, 5, 10, 13 1B to 4B data inputs
3, 6, 8, 11 1Y to 4Y data outputs
7 GND ground (0 V)
14 VCC positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
INPUTS OUTPUT
nA nB nY
L
L
H
H
L
H
L
H
Z
Z
Z
L
December 1990 4
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER MIN. MAX. UNIT CONDITIONS
VCC DC supply voltage −0.5 +7 V
VODC output voltage −0.5 +7 V
IIK DC input diode current 20 mA for VI<−0.5 V or VI> VCC + 0.5 V
−IOK DC output diode current 20 mA for VO<−0.5 V
−IODC output sink current 25 mA for − 0.5 V < VO
±ICC;
±IGND
DC VCC or GND current 50 mA
Tstg storage temperature range −65 +150 °C
Ptot power dissipation per package for temperature range; −40 to +125 °C
74HC/HCT
plastic DIL 750 mW above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO) 500 mW above +70 °C: derate linearly with 8 mW/K
December 1990 5
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
, except that the VOH values are
not valid for open drain. They are replaced by IOZ as given below.
Output capability: standard (open drain), excepting VOH
ICC category: SSI
Voltages are referenced to GND (ground = 0 V)
Note
1. The maximum operating output voltage (VO(max)) is 6.0 V.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC UNIT VCC
(V) VIOTHER
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
IOZ HIGH level output
leakage current 0.5 5.0 10.0 µA2.0
to
6.0 VIL
VO=V
O(max)(1)
or GND
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HC UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPZL/
tPLZ
propagation delay
nA, nB to nY 28
10
8
95
19
16
120
24
20
145
29
25 ns 2.0
4.5
6.0
Fig.6
tTHL output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0 Fig.6
December 1990 6
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
, except that the VOH values are
not valid for open drain. They are replaced by IOZ as given below.
Output capability: standard (open drain), excepting VOH
ICC category: SSI
Voltages are referenced to GND (ground = 0 V)
Note
1. The maximum operating output voltage (VO(max)) is 6.0 V.
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=t
f= 6 ns; CL= 50 pF
SYMBOL PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT VCC
(V) VIOTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
IOZ HIGH level output
leakage current 0.5 5.0 10.0 µA4.5
to
5.5 VIL VO=V
O(max)(1)
or GND
INPUT UNIT LOAD COEFFICIENT
nA, nB 1.0
SYMBOL PARAMETER
Tamb (°C) TEST CONDITIONS
74HCT UNIT VCC
(V) WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
tPZL/ tPLZ propagation delay
nA, nB, to nY 12 24 30 36 ns 4.5 Fig.6
tTHL output transition time 7 15 19 22 ns 4.5 Fig.6
December 1990 7
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
AC WAVEFORMS
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
HC: VM= 50%; VI= GND to VCC
HCT: VM= 1.3 V; VI= GND to 3 V.
TEST CIRCUIT AND WAVEFORMS
Fig.7 Test circuit (open drain) Fig.8 Input pulse definitions.
Definitions for Figs. 7, 8:
CL= load capacitance including jig and probe
capacitance
(see AC CHARACTERISTICS for values).
RT= termination resistance should be equal to the
output impedance ZO of the pulse generator.
tr=t
f
= 6 ns; when measuring fmax, there is no
constraint on tr, tf with 50% duty factor.
FAMILY AMPLITUDE VM
tr;t
f
f
max;
PULSE
WIDTH OTHER
74HC VCC 50% < 2 ns 6 ns
74HCT 3.0 V 1.3 V < 2 ns 6 ns
December 1990 8
Philips Semiconductors Product specification
Quad 2-input NAND gate 74HC/HCT03
APPLICATION INFORMATION
Notes to Figs 9 and 10
If VP− VCC (R) > 0.5 V a positive current will flow into the receiver (as described in the
“USER GUIDE
”; input/output
protection), this will not affect the receiver provided the current does not exceed 20 mA. At VCC < 4.5 V, RON (max) is not
guaranteed; RON(max) can be estimated using Figs 33 and 34 in the
“USER GUIDE”
.
Note to Application information
All values given are typical unless otherwise specified.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Pull-up configuration. (b)
(a)
(1) RON(max) = 0.26 V / 4 mA = 65 Ω (at 25 °C)
Fig.10 Minimum resistive load as a function of the pull-up voltage.
(1) VCC (R) = 2.0 V; VIL = 0.5 V.
(2) VCC (R) = 5.0 V; VIL = 0.8 V.
(3) VCC (R) = 4.5 V; VIL = 1.35 V.
(4) VCC (R) = 6.0 V; VIL = 1.8 V.
