AD7606TSTZ-EP-RL - ANALOG DEVICES

8-Channel DAS with 16-Bit, Bipolar Input,

Simultaneous Sampling ADC

Data Sheet

AD7606-EP

Rev. 0 Document Feedback

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FEATURES

8 simultaneously sampled inputs

True bipolar analog input ranges: ±10 V, ±5 V

Single 5 V analog supply and 2.3 V to 5.25 V VDRIVE

Fully integrated data acquisition solution

Analog input clamp protection

Input buffer with 1 MΩ analog input impedance

Second-order antialiasing analog filter

On-chip accurate reference and reference buffer

16-bit ADC with 150 kSPS on all channels

Oversampling capability with digital filter

Flexible parallel/serial interface

SPI/QSPI™/MICROWIRE™/DSP compatible

Performance

7 kV ESD rating on analog input channels

95.5 dB SNR, −107 dB THD

±0.5 LSB INL, ±0.5 LSB DNL

Low power: 100 mW

Standby mode: 25 mW

64-lead LQFP package

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC

standard)

Military temperature range −55°C to +125°C

Controlled manufacturing baseline

One assembly/test site

One fabrication site

Product change notification

Qualification data available on request

APPLICATIONS

Power-line monitoring and protection systems

Multiphase motor control

Instrumentation and control systems

Multiaxis positioning systems

Data acquisition systems (DAS)

FUNCTIONAL BLOCK DIAGRAM

V1GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V2GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V3GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V4GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V5GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V6GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V7GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

V8GND

1MΩ

1MΩ R

CLAMP

CLAMP T/H

8:1

MUX

AGND

BUSY

FRSTDATA

CONVS T A CONVS T B RESET RANGE

CONTROL

INPUTS

CLK O SC

REFIN/REFOUT

REF SELECT

AGND

OS 2

OS 1

OS 0

OUT

RD/SCLK

PAR/SER/ BYTE SEL

DRIVE

16-BIT

SAR DIGITAL

FILTER PARALLEL/

SERIAL

INTERFACE

2.5V

REF

REFCAPB REFCAPA

SERIAL

PARALLEL

REGCAP

2.5V

LDO

REGCAP

2.5V

LDO

DB[15:0]

AD7606-EP

16483-001

Figure 1.

AD7606-EP Data Sheet

Rev. 0 | Page 2 of 15

TABLE OF CONTENTS

Features .............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

Timing Specifications .................................................................. 6

Absolute Maximum Ratings ............................................................8

Thermal Resistance .......................................................................8

ESD Caution...................................................................................8

Pin Configuration and Function Descriptions ..............................9

Typical Performance Characteristics ........................................... 13

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

REVISION HISTORY

6/2018—Revision 0: Initial Ve rsion

Data Sheet AD7606-EP

Rev. 0 | Page 3 of 15

GENERAL DESCRIPTION

The AD7606-EP1 is a 16-bit, simultaneous sampling, analog-to-

digital, data acquisition system (DAS) with eight channels. The

device contains analog input clamp protection, a second-order

antialiasing filter, a track-and-hold amplifier, a 16-bit charge

redistribution successive approximation analog-to-digital

converter (ADC), a flexible digital filter, a 2.5 V reference and

reference buffer, and high speed serial and parallel interfaces.

The AD7606-EP operates from a single +5 V supply and can

accommodate ±10 V and ±5 V true bipolar input signals while

sampling at throughput rates up to 150 kSPS for all channels.

The input clamp protection circuitry can tolerate voltages up to

±16.5 V. The AD7606-EP has 1 MΩ analog input impedance

regardless of sampling frequency. The single-supply operation,

on-chip filtering, and high input impedance eliminate the need

for driver op amps and external bipolar supplies. The AD7606-EP

antialiasing filter has a 3 dB cutoff frequency of 23 kHz. The

flexible digital filter is pin driven, yields improvements in SNR,

and reduces the 3 dB bandwidth.

Additional application and technical information can be found

in the AD7606 data sheet.

1 Protected by US Patent Number 8,072,360.

AD7606-EP Data Sheet

Rev. 0 | Page 4 of 15

SPECIFICATIONS

Reference voltage (VREF) = 2.5 V external/internal, AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, sampling frequency (fSAMPLE) =

150 kSPS, TA = −55°C to +125°C, unless otherwise noted.

Table 1.

Parameter Test Conditions/Comments Min Typ Max Unit

DYNAMIC PERFORMANCE Input frequency (fIN) = 1 kHz sine wave,

unless otherwise noted

Signal-to-Noise Ratio (SNR)1, 2 Oversampling by 16, ±10 V range, fIN = 130 Hz 93 95.5 dB

Oversampling by 16, ±5 V range, fIN = 130 Hz 92 94.5 dB

No oversampling, ±10 V range 87.5 90 dB

No oversampling, ±5 V range

86.5

Signal-to-(Noise + Distortion) (SINAD)1 No oversampling, ±10 V range 87 90 dB

No oversampling, ±5 V range 86 89 dB

Dynamic Range No oversampling, ±10 V range 90.5 dB

No oversampling, ±5 V range 90 dB

Total Harmonic Distortion (THD)1 −107 −93 dB

Peak Harmonic or Spurious Noise (SFDR)1 −108 dB

Intermodulation Distortion (IMD)1 Tone frequencies = 1 kHz and 1.1 kHz

Second-Order Terms −110 dB

Third-Order Terms −106 dB

Channel-to-Channel Isolation1 fIN on unselected channels up to 160 kHz −95 dB

ANALOG INPUT FILTER

Full Power Bandwidth −3 dB, ±10 V range 23 kHz

−3 dB, ±5 V range 15 kHz

−0.1 dB, ±10 V range

kHz

−0.1 dB, ±5 V range 5 kHz

Group Delay Time (tGROUP DELAY) ±10 V range 11 µs

±5 V range 15 µs

DC ACCURACY

Resolution No missing codes 16 Bits

Differential Nonlinearity1 ±0.5 ±0.99 LSB3

Integral Nonlinearity1 ±0.5 ±2 LSB3

Total Unadjusted Error (TUE) ±10 V range ±6 LSB3

±5 V range

±12

LSB

Positive Full-Scale Error1, 4 External reference ±8 ±34 LSB3

Internal reference ±8 LSB3

Positive Full-Scale Error Drift External reference ±2 ppm/°C

Internal reference ±7 ppm/°C

Positive Full-Scale Error Matching

±10 V range

LSB

±5 V range 16 40 LSB3

Bipolar Zero Code Error1, 5 ±10 V range ±1 ±8 LSB3

± 5 V range ±3 ±14 LSB3

Bipolar Zero Code Error Drift ±10 V range 10 µV/°C

± 5 V range 5 µV/°C

Bipolar Zero Code Error Matching1 ±10 V range 1 8 LSB3

±5 V range 6 22 LSB3

Negative Full-Scale Error1, 4 External reference ±8 ±34 LSB3

Internal reference ±8 LSB3

Negative Full-Scale Error Drift External reference ±4 ppm/°C

Internal reference ±8 ppm/°C

Negative Full-Scale Error Matching1 ±10 V range 5 32 LSB3

±5 V range 16 40 LSB3

Data Sheet AD7606-EP

Rev. 0 | Page 5 of 15

Parameter Test Conditions/Comments Min Typ Max Unit

ANALOG INPUT

Input Voltage Ranges RANGE = 1 ±10 V

RANGE = 0 ±5 V

Analog Input Current 10 V, see Figure 11 5.4 µA

5 V, see Figure 11

2.5

µA

Input Capacitance6 5 pF

Input Impedance 1 MΩ

REFERENCE INPUT AND OUTPUT

Reference Input Voltage Range 2.475 2.5 2.525 V

DC Leakage Current ±1 µA

Input Capacitance6 REF SELECT = 1 7.5 pF

Reference Output Voltage REFIN/REFOUT 2.49/

2.505

Reference Temperature Coefficient ±15 ppm/°C

LOGIC INPUTS

Input High Voltage (VINH) 0.7 × VDRIVE V

Input Low Voltage (VINL) 0.3 × VDRIVE V

Input Current (IIN) ±2 µA

Input Capacitance (CIN)6 5 pF

LOGIC OUTPUTS

Output High Voltage (VOH) Source current (ISOURCE) = 100 µA VDRIVE − 0.2 V

Output Low Voltage (VOL) Sink current (ISINK) = 100 µA 0.2 V

Floating State Leakage Current ±1 ±20 µA

Floating State Output Capacitance6 5 pF

Output Coding Twos complement

CONVERSION RATE

Conversion Time All eight channels included, see Table 2 4.5 µs

Track-and-Hold Acquisition Time 1.5 µs

Throughput Rate Per channel, all eight channels included 150 kSPS

POWER REQUIREMENTS

AVCC 4.75 5.25 V

VDRIVE 2.3 5.25 V

Total Current (ITOTAL) Digital inputs = 0 V or VDRIVE

Normal Mode (Static) 16 22 mA

Normal Mode (Operational)7 fSAMPLE = 150 kSPS 20 27 mA

Standby Mode

Shutdown Mode 2 7 µA

Power Dissipation

Normal Mode (Static) 80 115.5 mW

Normal Mode (Operational)7 fSAMPLE = 150 kSPS 100 142 mW

Standby Mode 25 42 mW

Shutdown Mode 10 36.8 µW

1 See the Terminology section in the AD7606 datasheet.

2 This specification applies when reading during a conversion or after a conversion. If reading during a conversion in parallel mode with VDRIVE = 5 V, SNR typically reduces by 1.5 dB

and THD by 3 dB.

3 LSB means least significant bit. With ±5 V input range, 1 LSB = 152.58 µV. With ±10 V input range, 1 LSB = 305.175 µV.

4 These specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from

the external reference.

5 Bipolar zero code error is calculated with respect to the analog input voltage.

6 Sample tested during initial release to ensure compliance.

7 Operational power and current figure includes contribution when running in oversampling mode.

AD7606-EP Data Sheet

Rev. 0 | Page 6 of 15

TIMING SPECIFICATIONS

AVCC = 4.75 V to 5.25 V, VDRIVE = 2.3 V to 5.25 V, VREF = 2.5 V external reference and internal reference, TA = TMIN to TMAX, unless otherwise noted.

Sample tested during initial release to ensure compliance. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns (10% to

90% of VDRIVE) and timed from a voltage level of 1.6 V.

Table 2.

Limit at TMIN, TMAX

0.1 × VDRIVE and 0.9 × VDRIVE

Logic Input Levels

0.3 × VDRIVE and 0.7 × VDRIVE

Logic Input Levels

Parameter Min Typ Max Min Typ Max Unit Description

PARALLEL/SERIAL/BYTE MODE

tCYCLE 1/throughput rate

6.65 6.65 µs Parallel mode, reading during or after

conversion; or serial mode: VDRIVE =

3.3 V to 5.25 V, reading during a

conversion using DOUTA and DOUTB lines

11.1 µs Serial mode reading after a conversion;

VDRIVE = 2.7 V

11.4 12.4 µs Serial mode reading after a conversion;

VDRIVE = 2.3 V, DOUTA and DOUTB lines

tCONV Conversion time

4.1 4.5 5 4.1 4.5 5 µs Oversampling off

9.6 11.7 9.6 11.7 µs Oversampling by 2

20.5 25 20.5 25 µs Oversampling by 4

42 52 42 52 µs Oversampling by 8

105

µs

Oversampling by 16

173 212 173 212 µs Oversampling by 32

347 424 347 424 µs Oversampling by 64

tRESET 50 50 ns RESET high pulse width

t1 40 45 ns CONVST x high to BUSY high

t2 25 25 ns Minimum CONVST x low pulse

t3 25 25 ns Minimum CONVST x high pulse

t4 0 0 ns BUSY falling edge to CS falling edge

setup time

t51 0.5 0.5 ms Maximum delay allowed between

CONVST A, CONVST B rising edges

t6 25 25 ns Maximum time between last CS rising

edge and BUSY falling edge

t7 25 25 ns Minimum delay between RESET low to

CONVST x high

1 The delay between the CONVST x signals was measured as the maximum time allowed while ensuring a <10 LSB performance matching between channel sets.

Data Sheet AD7606-EP

Rev. 0 | Page 7 of 15

Timing Diagrams

CYCLE

RESET

CONV

CONVS T A,

CONVS T B

CONVS T A,

CONVS T B

BUSY

RESET

16483-002

Figure 2. CONVST x Timing—Reading After a Conversion

CYCLE

CONV

CONVS T A,

CONVS T B

CONVS T A,

CONVS T B

BUSY

RESET

16483-003

Figure 3. CONVST x Timing—Reading During a Conversion

AD7606-EP Data Sheet

Rev. 0 | Page 8 of 15

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVCC to AGND −0.3 V to +7 V

VDRIVE to AGND −0.3 V to AVCC + 0.3 V

Analog Input Voltage to AGND1 ±16.5 V

Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V

Digital Output Voltage to AGND −0.3 V to VDRIVE + 0.3 V

REFIN to AGND −0.3 V to AVCC + 0.3 V

Input Current to Any Pin Except Supplies

±10 mA

Operating Temperature Range −55°C to +125°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

Soldering Reflow Temperature 260 (0)°C

Electrostatic Discharge (ESD)

All Pins Except Analog Inputs 2 kV

Analog Input Pins Only 7 kV

1 Transient currents of up to 100 mA do not cause silicon controlled rectifier

(SCR) latch-up.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

THERMAL RESISTANCE

Thermal performance is directly linked to PCB design and

operating environment. Careful attention to PCB thermal

design is required.

θJA is the natural convection, junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure.

θJC is the junction to case thermal resistance.

Table 4. Thermal Resistance

Package Type θJA θJC Unit

ST-64-21 45 11 °C/W

1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test

board. See JEDEC JESD-51.

ESD CAUTION

Data Sheet AD7606-EP

Rev. 0 | Page 9 of 15

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD7606-EP

TOP VIEW

(No t t o Scale)

64 63 62 61 60 59 58 57

V1GND

56 55 54 53 52 51 50 49

PIN 1

V2GND

V3GND

V4GND

V5GND

V6GND

V7GND

V8GND

DB13

DB12

DB11

DB14/HBEN

VDRIVE

DB1

17 18 19 20 21 22 23 24 25

AGND

26 27 28 29 30 31 32

DB2

DB3

DB4

DB5

DB6

DB7/DOUTA

DB9

DB10

DB8/DOUTB

AGND

AVCC 1

FRSTDATA

OS 2

DB0

BUSY

CONVS T B

CONVS T A

RANGE

RESET

RD/SCLK

PAR/SER/BYTE SEL

OS 1

OS 0

STBY

DECOUP LI NG CAP P IN

DATA OUTP UT

POWER SUPPLY

ANALOG INPUT

GRO UND P IN

DIGITAL OUTPUT

DIGITAL INPUT

REF ERE NCE INPUT/ OUT P UT

DB15/BYTE S E L

REFIN/REFOUT

AGND

AVCC

REFGND

REFCAPA

AGND

REFCAPB

REFGND

REGCAP

AVCC

REF SELECT

16483-008

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Type 1 Mnemonic Description

1, 37, 38, 48 P AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-

end amplifiers and to the ADC core. Decouple these supply pins to AGND.

2, 26, 35, 40,

41, 47

P AGND Analog Ground. These pins are the ground reference points for all analog circuitry on the

AD7606-EP. Refer all analog input signals and external reference signals to these pins.

Connect the six AGND pins to the AGND plane of a system.

3, 4, 5 DI OS 0, OS 1, OS 2 Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling

ratio. OS 2 is the most significant bit (MSB) control bit, and OS 0 is the least significant bit

(LSB) control bit. See the Oversample Bit Decoding table and Digital Filter section in the

AD7606 data sheet for more details about the logic states and oversampling mode of

operation.

6 DI PAR/SER/

BYTE SEL

Parallel/Serial/Byte Interface Selection Input. Logic input. See the Interface Mode Selection

table in the AD7606 data sheet.

If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic

high, the serial interface is selected. Parallel byte interface mode is selected when this pin is

logic high and DB15/BYTE SEL is logic high.

In serial mode, the

/SCLK pin functions as the serial clock input. The DB7/D

OUT

A pin and

the DB8/DOUTB pin function as serial data outputs. When the serial interface is selected, tie the

DB[15:9] and DB[6:0] pins to ground.

In byte mode, DB15, in conjunction with PAR/SER/BYTE SEL, is used to select the parallel byte

mode of operation. DB14 is used as the HBEN pin. DB[7:0] transfer the 16-bit conversion

results in two RD operations, with DB0 as the LSB of the data transfers.

7 DI STBY Standby Mode Input. This pin is used to place the AD7606-EP into one of two power-down

modes: standby mode or shutdown mode. The power-down mode entered depends on the

state of the RANGE pin. When in standby mode, all circuitry, except the on-chip reference,

regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is

powered down. See the Power-Down Mode Selection table in the AD7606 data sheet.

AD7606-EP Data Sheet

Rev. 0 | Page 10 of 15

Pin No. Type 1 Mnemonic Description

8 DI RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input

range of the analog input channels. If this pin is tied to a logic high, the analog input range

is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all

channels. A logic change on this pin has an immediate effect on the analog input range.

Changing this pin during a conversion is not recommended for fast throughput rate

applications. See the Analog Input section in the AD7606 data sheet for more information.

9, 10 DI CONVST A,

CONVST B

Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are

used to initiate conversions on the analog input channels. For simultaneous sampling of

all input channels, CONVST A and CONVST B can be shorted together, and a single convert

start signal can be applied. Alternatively, CONVST A can be used to initiate simultaneous

sampling: V1, V2, V3, and V4 for the AD7606-EP. CONVST B can be used to initiate

simultaneous sampling on the other analog inputs: V5, V6, V7, and V8 for the AD7606-E P.

This is possible only when oversampling is not switched on. When the CONVST A or CONVST B

pin transitions from low to high, the front-end, track-and-hold circuitry for the respective

analog inputs is set to hold.

RESET

Reset Input. When set to logic high, the rising edge of RESET resets the AD7606-EP. The

device receives a RESET pulse directly after power-up. The RESET high pulse is typically 50 ns

wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a RESET

pulse is applied during a read, the contents of the output registers reset to all zeros.

12 DI RD/SCLK Parallel Data Read Control Input When Parallel Interface Selected (RD)/Serial Clock Input

When Serial Interface Selected (SCLK). When both CS and RD are logic low in parallel

mode, the output bus is enabled. In serial mode, this pin acts as the serial clock input for

data transfers. The CS falling edge takes the DOUTA and DOUTB data output lines out

of three-state and clocks out the MSB of the conversion result. The rising edge of SCLK

clocks all subsequent data bits onto the DOUTA and DOUTB serial data outputs. See the

Conversion Control section in the AD7606 data sheet for more information.

13 DI CS Chip Select. This active low logic input frames the data transfer. When both CS and RD are

logic low in parallel mode, the DB[15:0] output bus is enabled, and the conversion result is

output on the parallel data bus lines. In serial mode, CS is used to frame the serial read

transfer and clock out the MSB of the serial output data.

14 DO BUSY Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising

edges and indicates that the conversion process has started. The BUSY output remains

high until the conversion process for all channels is complete. The falling edge of BUSY

signals that the conversion data is being latched into the output data registers and is

available to read after t4. Any data read while BUSY is high must be completed before the

falling edge of BUSY occurs. Rising edges on CONVST A or CONVST B have no effect while

the BUSY signal is high.

15 DO FRSTDATA Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read

back on the parallel, byte, or serial interface. When the CS input is high, the FRSTDATA

output pin is in three-state. The falling edge of CS takes FRSTDATA out of three-state.

In parallel mode, the falling edge of RD corresponding to the result of V1 then sets the

FRSTDATA pin high, indicating that the result from V1 is available on the output data bus.

The FRSTDATA output returns to a logic low following the next falling edge of RD. In serial

mode, FRSTDATA goes high on the falling edge of CS because this pin clocks out the MSB of

V1 on DOUTA. FRSTDATA returns low on the 16th SCLK falling edge after the CS falling edge.

See the Conversion Control section in the AD7606 data sheet for more information.

22 to 16 DO DB[6:0] Parallel Output Data Bits, DB6 to DB0. When PAR/SER/BYTE SEL = 0, these pins act as three-

state parallel digital input and output pins. When CS and RD are low, these pins are used to

output DB6 to DB0 of the conversion result. When PAR/SER/BYTE SEL = 1, tie these pins to

AGND. When operating in parallel byte interface mode, DB[7:0] outputs the 16-bit

conversion result in two RD operations. DB7 (Pin 24) is the MSB and DB0 is the LSB. See Pin 24

description for additional information.

23 P VDRIVE Logic Power Supply Input. The voltage (2.3 V to 5.25 V) supplied at this pin determines the

operating voltage of the interface. This pin is nominally at the same supply as the supply of the

host interface (that is, digital signal processor and field programmable gate array).

Data Sheet AD7606-EP

Rev. 0 | Page 11 of 15

Pin No. Type 1 Mnemonic Description

24 DO DB7/DOUTA Parallel Output Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When PAR/SER/

BYTE SEL = 0, this pin acts as a three-state parallel digital input and output pin. When CS and

RD are low, this pin is used to output DB7 of the conversion result. When PAR/SER/BYTE

SEL = 1, this pin functions as DOUTA and outputs serial conversion data. When operating in

parallel byte mode, DB7 is the MSB of the byte. See the Conversion Control section in the

AD7606 data sheet for more information.

25 DO DB8/DOUTB Parallel Output Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When PAR/SER/

BYTE SEL = 0, this pin acts as a three-state parallel digital input and output pin. When CS

and RD are low, this pin is used to output DB8 of the conversion result. When PAR/SER/BYTE

SEL = 1, this pin functions as DOUTB and outputs serial conversion data. See the Conversion

Control section in the AD7606 data sheet for more information.

31 to 27 DO DB[13:9] Parallel Output Data Bits, DB13 to DB9. When PAR/SER/BYTE SEL = 0, these pins act as

three-state parallel digital input and output pins. When CS and RD are low, these pins are

used to output DB13 to DB9 of the conversion result. When PAR/SER/BYTE SEL = 1, tie these

pins to AGND.

32 DO/DI DB14/HBEN Parallel Output Data Bit 14 (DB14)/High Byte Enable (HBEN). When PAR/ SER/BYTE SEL = 0,

this pin acts as a three-state parallel digital output pin. When CS and RD are low, this pin is

used to output DB14 of the conversion result. When PAR/SER/BYTE SEL = 1 and DB15/BYTE

SEL = 1, the AD7606-EP operates in parallel byte interface mode. In parallel byte mode, the

HBEN pin is used to select whether the MSB or the LSB of the conversion result is output first.

When HBEN = 1, the MSB is output first, followed by the LSB. When HBEN = 0, the LSB is

output first, followed by the MSB. In serial mode, tie this pin to GND.

33 DO/DI DB15/BYTE SEL Parallel Output Data Bit 15 (DB15)/Parallel Byte Mode Select (BYTE SEL). See the Interface

Mode Selection table in the AD7606 data sheet. When PAR/SER/BYTE SEL = 0, this pin acts as

a three-state parallel digital output pin. When CS and RD are low, this pin is used to output

DB15 of the conversion result. When PAR/SER/BYTE SEL = 1, the BYTE SEL pin is used to

select between serial interface mode and parallel byte interface mode. When PAR/SER/

BYTE SEL = 1 and DB15/BYTE SEL = 0, the AD7606-EP operates in serial interface mode.

When PAR/SER/ BYTE SEL = 1 and DB15/BYTE SEL = 1, the AD7606-EP operates in parallel

byte interface mode.

34 DI REF SELECT Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the

internal reference is selected and enabled. If this pin is set to logic low, the internal reference

is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin.

36, 39 P REGCAP Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple these

output pins separately to AGND using a 1 μF capacitor. The voltage on these pins is in the

2.5 V to 2.7 V range.

42 REF REFIN/REFOUT Reference Input (REFIN)/Reference Output (REFOUT). See the Internal/External Reference

section in the AD7606 data sheet for more information. The on-chip reference of 2.5 V

is available on this pin for external use if the REF SELECT pin is set to logic high. Alternatively,

the internal reference can be disabled by setting the REF SELECT pin to logic low, and an

external reference of 2.5 V can be applied to this input. Decoupling is required on this pin

for both the internal and external reference options. Apply a 10 μF capacitor from this pin

to ground close to the REFGND pins.

43, 46 REF REFGND Reference Ground Pins. Connect these pins to AGND.

44, 45 REF REFCAPA,

REFCAPB

Reference Buffer Output Force and Sense Pins. Connect these pins together, and decouple

these pins to AGND using a low ESR, 10 μF ceramic capacitor. The voltage on these pins is

typically 4.5 V.

49 AI V1 Analog Input 1. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

AI GND

V1GND

Analog Input V1 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

51 AI V2 Analog Input 2. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

52 AI GND V2GND Analog Input V2 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

53 AI V3 Analog Input 3. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

54 AI GND V3GND Analog Input V3 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

AD7606-EP Data Sheet

Rev. 0 | Page 12 of 15

Pin No. Type 1 Mnemonic Description

55 AI V4 Analog Input 4. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

56 AI GND V4GND Analog Input V4 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

Analog Input 5. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

58 AI GND V5GND Analog Input V5 Ground Pins. Connect all analog input AGND pins to the AGND plane of a

system.

59 AI V6 Analog Input 6. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

60 AI GND V6GND Analog Input V6 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

61 AI V7 Analog Input 7 Pin. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

62 AI GND V7GND Analog Input V7 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

63 AI V8 Analog Input 8 Pin. This pin is a single-ended analog input. The RANGE pin determines the

analog input range of this channel.

64 AI GND V8GND Analog Input V8 Ground Pin. Connect all analog input AGND pins to the AGND plane of a

system.

1 P is power supply, DI is digital input, DO is digital output, REF is reference input and output, AI is analog input, and GND is ground.

Data Sheet AD7606-EP

Rev. 0 | Page 13 of 15

TYPICAL PERFORMANCE CHARACTERISTICS

–5

–10

–15

–20

–25

–30

NFS ERROR (LSB)

TEMPERATURE (°C)

16483-016

–55 –35 –15 525 45 65 85 105 125

±10V RANG E

±5V RANG E

fSAMPLE

= 150kSPS

, V

DRIVE

= 5V

EXT E RNAL REFERE NCE

Figure 5. NFS Error vs. Temperature

PFS ERROR (LSB)

TEMPERATURE (°C)

16483-017

–55 –35 –15 525 45 65 85 105 125

–20

–15

–10

–5

±10V RANG E

±5V RANG E

fSAMPLE

= 150kSPS

, V

DRIVE

= 5V

EXT E RNAL REFERE NCE

Figure 6. PFS Error vs. Temperature

–55 –35 –15 525 45 65 85 105 125

NFS / P FS CHANNE L MATCHI NG (LSB)

TEMPERATURE (°C)

16483-018

–10

–5

10V RANGE

, V

DRIVE

= 5V

EXT E RNAL REFERE NCE

PFS ERROR

NFS ERROR

Figure 7. NFS and PFS Channel Matching vs. Temperature

BIPOL AR ZERO CO DE E RROR (LSB)

TEMPERATURE (°C)

16483-020

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

–55 –35 –15 525 45 65 85 105 125

±10V RANG E

±5V RANG E

fSAMPLE

= 150kSPS

, V

DRIVE

= 5V

EXT E RNAL REFERE NCE

Figure 8. Bipolar Zero Code Error vs. Temperature

BIPOL AR ZERO CO DE E RROR MATCHI NG (LSB)

TEMPERATURE (°C)

16483-021

–55 –35 –15 525 45 65 85 105 125

SAMPLE

= 150kSPS

, V

DRIVE

= 5V

EXT E RNAL REFERE NCE

–4

–3

–2

–1

±10V RANG E

±5V RANG E

Figure 9. Channel to Channel Bipolar Zero Code Error Matching vs.

Temperature

AD7606-EP Data Sheet

Rev. 0 | Page 14 of 15

REFOUT VOLTAGE (V)

TEMPERATURE (°C)

16483-028

2.4950

2.4955

2.4960

2.4965

2.4970

2.4975

2.4980

2.4985

2.4990

2.4995

2.5000

2.5005

2.5010

–55 –35 –15 525 45 65 85 105 125

= 4.75V

= 5.00V

= 5.25V

Figure 10. REFOUT Voltage vs. Temperature for Different Supply Voltages

–10

–8

–6

–4

–2

ANALOG INPUT CURRENT (µA)

INPUT VOLTAGE (V)

16483-029

–10 –8 –6 –4 –2 0 2 4 6 8

–55°C

+25°C

+125°C

, V

DRIVE

= 5V

SAMPLE

= 150kSPS

Figure 11. Analog Input Current vs. Input Voltage for Various Temperatures

Data Sheet AD7606-EP

Rev. 0 | Page 15 of 15

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC S TANDARDS MS-026-BCD

051706-A

TOP VIEW

(PINS DO WN)

17 33

4964

0.27

0.22

0.17

0.50

BSC

LEAD P ITCH

12.20

12.00 SQ

11.80

PIN 1

1.60

MAX

0.75

0.60

0.45

10.20

10.00 SQ

9.80

VIEW A

0.20

0.09

1.45

1.40

1.35

0.08

COPLANARITY

VIEW A

ROTAT E D 90° CCW

SEATING

PLANE

0.15

0.05

7°

3.5°

0°

Figure 12. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

AD7606TSTZ-EP −55°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

AD7606TSTZ-EP-RL −55°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2

1 Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D16483-0-6/18(0)