CY7C131-55JC T&R - Cirrus Logic, Inc.

1K x 8 Dual-Port Static Ram

fax id: 5200

CY7C130/CY7C131

CY7C140/CY7C141

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 9 5 1 3 4 • 408-943-260 0

May 1989 – Revised March 27, 1997

1CY7C140

Features

• Tru e Dual-Ported memory cel ls whic h allow simulta-

neous reads of the same memory location

• 1K x 8 organization

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 1 5 ns

• Low operating power: ICC = 90 mA (max.)

• Fully asynchronous op eration

• Automatic power-down

• Master CY7C130/CY7C131 easily expands data bus

width to 16 or more bits us ing slave CY7C140/CY7C141

• BUSY output flag on CY7C130/CY7C131; BUSY input

on CY7C140/CY7C141

• INT flag for port-to-port communication

• Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and

52-pin TQFP

• Pin-compatible and functionally equivalent to

IDT7130/IDT7140

Functional Description

The CY7C130/CY7C131/CY7C140 and CY7C141 are

high-speed CMOS 1K by 8 dual-port static R AMs. Two ports

are provided permitting independent access to any location in

memory. The CY7C130/ CY7C131 can be utilized as either a

standalone 8-bit d ual-port static RAM or as a master dua l-port

RAM in conjunction with the CY7C140/CY7C141 slave du-

al-port device in systems requiring 16-bit or greater word

widths. It is the solution to applications requiring shared or

buffered data, such as cache memory for DSP, bit-slice, or

multiprocessor designs.

Each port has independent control pins; chip enable (CE),

write enable (R/W), and output enable (OE). Two flags are

provided on each port, BUSY and INT. BUSY signals that the

port is t rying to access the same location currently being ac-

cess ed by the other port. INT is an interrupt flag ind icating that

data has been placed in a u nique loca tion (3FF for the left port

and 3FE for the right port). An automatic power-down feature

is controlled independently on each port by the chip enable

(CE) pins.

The CY7C130 and CY7C140 are available in 48-pin DIP. The

CY7C131 and CY7C141 are available in 52-pin PLCC and

PQFP.

Notes:

1. CY7C130/CY7C131 (Master): BUSY is open drain output and requires pull-up resistor

CY7C140/CY7C141 (Slave): BUSY is input.

2. Open drain outputs: pull-up resistor required

Logic Block Diagram Pin Configurations

C130-1 C130-2

23 26

24 25

GND

11 38

12 37

R/WL

CEL

BUSYL

INTL

OEL

A0L

A1L

A2L

A3L

A4L

A5L

A6L

A7L

A8L

A9L

I/O0L

I/O1L

I/O2L

I/O3L

I/O4L

I/O5L

I/O6L

I/O7L

CER

R/WR

BUSY

INTR

OER

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

A9R

I/O7R

I/O6R

I/O5R

I/O4R

I/O3R

I/O2R

I/O1R

I/O0R

VCC

DIP

Top View

7C130

7C140

R/WL

BUSYL

CEL

OEL

A9L

A0L A0R

A9R

R/WR

CER

OER

CER

OER

CEL

OEL

R/WLR/WR

I/O7L

I/O0L

I/O7R

I/O0R

BUSYR

INTLINTR

ARBITRATION

LOGIC

(7C130/7C131 ONLY)

AND

INTERRUPT LOGIC

CONTROL

I/O CONTROL

I/O

MEMORY

ARRAY ADDRESS

DECODER

ADDRESS

DECODER

[1]

[2] [2]

CY7C130/CY7C131

CY7C140/CY7C141

Maximum Ratings

(Above which the useful life may be impaired. For user guide-

lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temper ature with

Power Applied.............................................–55°C to +125°C

Supply Volta ge to Gro und Potential

(Pin 48 to Pin 24)........................................... –0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State............................................... –0.5V to +7.0V

DC Input Vol tage............................................ –3.5V to +7.0V

Output Current into Outputs (LOW)................... ..........20 mA

Static Discharge Voltage.......................................... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up C urrent.................................................... >200 mA

Notes:

3. 15 and 25-ns version available only in PLCC/PQ FP packages.

4. Shaded area contains preliminary information.

5. TA is the “instant on” case temperature

Pin Configuration (continued)

Top View

PLCC

OER

A0R

2122 2324252627282930313233

7 6 5 4 3 2 52 51 50 49 48 47

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

A9R

I/O7R

A1L

A2L

A3L

A4L

A5L

A6L

A7L

A8L

A9L

I/O0L

I/O1L

I/O2L

I/O3L

C130-3

7C131

7C141

1415 16 17 18 19 20 21 22 23 24 25 26

525150 494847 454443424140

Top View

PQFP

OER

A0R

A1R

A2R

A3R

A4R

A5R

A6R

A7R

A8R

A9R

I/O7R

A1L

A2L

A3L

A4L

A5L

A6L

A7L

A8L

A9L

I/O0L

I/O1L

I/O2L

I/O3L

C130-4

7C131

7C141

Selectio n G uide

7C131-15[3,4]

7C141-15 7C131-25[3]

7C141-25

7C130-30

7C131-30

7C140-30

7C141-30

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55

Maximum Access Time (ns) 15 25 30 35 45 55

M aximum Operating

Cur rent (mA) Com’l/Ind 190 170 170 120 90 90

Military 170 120 120

Maximum Standby

Cur rent (mA) Com’l/Ind 75 65 65 45 35 35

Military 65 45 45

Operating Range

Range Ambient

Temperature VCC

Commercial 0°C to +70°C 5V ± 10%

Industrial –40°C to +85°C 5V ± 10%

Military[5] –55°C to +125°C 5V ± 10%

CY7C130/CY7C131

CY7C140/CY7C141

]

Electrical Characteristics Over the Operating Range[6]

7C131-15[3,4]

7C141-15

7C130-30[3]

7C131-25,30

7C140-30

7C141-25,30

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45,55

7C131-45,55

7C140-45,55

7C141-45,55

Parameter Description Test Conditions Min. Max. Min. Max. Min. Max. Min. Max. Unit

VOH Output HIGH

Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 2.4 V

VOL Output LOW

Voltage IOL = 4.0 mA 0.4 0.4 0.4 0.4 V

IOL = 16.0 mA[7] 0.5 0.5 0.5 0.5

VIH Input HIGH Voltage 2.2 2.2 2.2 2.2 V

VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V

IIX Input Leakage

Current GND < VI < VCC –5 +5 –5 +5 –5 +5 –5 +5 µA

IOZ Outp ut Leakage

Current GND < VO < VCC,

Output Disabled –5 +5 –5 +5 –5 +5 –5 +5 µA

IOS Output Short

Circuit Curr ent [8, 9] VCC = Max.,

VOUT = GND –350 –350 –350 –350 mA

ICC VCC Operating

Supply Current CE = VIL,

Outputs Open,

f = fMAX[10]

Com’l 190 170 120 90 mA

Mil 170 120

ISB1 Standby Current

Both Ports,

TTL Inputs

CEL and CER >

VIH, f = fMAX[10] Com’l 75 65 45 35 mA

Mil 65 45

ISB2 Standby Current

One Port,

TTL Inputs

CEL or CER > VIH,

Active P ort Out-

puts Open,

f = fMAX[10]

Com’l 135 115 90 75 mA

Mil 115 90

ISB3 Standby Current

Both Ports,

CM OS Inputs

Both Ports CEL

and CER > VCC –

0.2V,

VIN > VCC – 0.2V

or VIN < 0.2V, f = 0

Com’l 15 15 15 15 mA

Mil 15 15

ISB4 Standby Current

One Port,

CM OS Inputs

One Port CEL or

CER > VCC – 0.2V,

VIN > VCC – 0.2V

or VIN < 0. 2 V,

Active Port Outputs

Open,

f = f MAX[10]

Com’l 125 105 85 70 mA

Mil 105 85

Notes:

6. See the last page of this specification for Group A subgroup testing information.

7. BUSY and INT pins only.

8. Duration of the short circuit should not exceed 30 seconds.

9. This parameter is guaranteed but not tested.

10. At f=fMAX, add ress and data inp uts are cycli ng at the maximum fr equency of r ead cycle of 1/tRC and using AC Test W av eforms input lev els of GN D to 3V.

Capacitance[9]

Parameter Description Test Conditions Max. Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz,

VCC = 5.0V 15 pF

COUT Output Capacitance 10 pF

CY7C130/CY7C131

CY7C140/CY7C141

AC Test Loads and Waveforms

Switching Characteristics Over the Operating Range[6,11]

7C131-15[3,4]

7C141-15

7C130-25[3]

7C131-25

7C140-25

7C141-25

7C130-30

7C131-30

7C140-30

7C141-30

Parameter Description Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

tRC Read Cycle Time 15 25 30 ns

tAA Address to Data Valid[12] 15 25 30 ns

tOHA Data Hold from Address Change 0 00ns

ACE CE LOW to Data Valid[12] 15 25 30 ns

tDOE OE LOW t o Data Valid[12] 10 15 20 ns

tLZOE OE LOW to L ow Z[9,13, 14] 333ns

HZOE OE HIGH to High Z[9,13, 14] 10 15 15 ns

tLZCE CE LOW to Low Z[9,13, 14] 355ns

HZCE CE HIGH to High Z[9,13, 14] 10 15 15 ns

tPU CE LOW to Power-Up[9] 000ns

PD CE HIGH to Power-Down[9] 15 25 25 ns

WRITE CYCLE[15]

tWC Write Cycle Time 15 25 30 ns

tSCE CE LOW to Write End 12 20 25 ns

tAW Address Set-Up to Write End 12 20 25 ns

tHA Address Hold from Write End 2 22ns

SA Address Set-Up to Write Start 0 00ns

PWE R/W Pulse Width 12 15 25 ns

tSD Data Set-Up to Write End 10 15 15 ns

tHD Data Hold fr om Write End 0 00ns

HZWE R/W LOW to High Z[14] 10 15 15 ns

tLZWE R/W HIG H to Low Z[14] 000ns

Notes:

1 1. Test conditions assume s ignal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified

IOL/IOH, and 30- pF load capac itance.

12. AC Test Conditions use VOH = 1.6V and VOL = 1. 4V.

13. At any given temperature and voltage condition for any given device, tHZCE is les s than tLZCE and t HZOE is l ess than tLZOE.

14. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tes ted wi th C L = 5pF a s in part ( b) of A C Test Load s

T ransiti on is mea sured ±500 m V from s teady state v oltage.

15. The internal write time of the memory is defined by the overlap of CS LO W and R/ W LOW . Bo th signal s must be l ow to i nitiate a wr ite and either signal can termi nate

a write by goi ng h igh. T he data i nput set-up and hold timing s hould b e r eferenced to the r is ing edge of the sign al that termi nates the wri te

3.0V

OUTPUT

R1 893Ω

347Ω

30 pF

INCLUDING

JIGAND

SCOPE

GND

90% 90%

10%

≤ 5ns ≤5ns

OUTPUT

R1 893Ω

347Ω

5pF

INCLUDING

JIGAND

SCOPE

(a) (b)

OUTPUT 1.40V

Equivalent to: THÉVENIN EQUIVALENT

281Ω

BUSY

INT

BUSY Output Load

(CY7C130/CY7C131 ONLY)

10%

C130-5

C130-6

ALL INPUT PULSES

250Ω

CY7C130/CY7C131

CY7C140/CY7C141

BUSY/INTERRUPT TIMING

tBLA BUSY LOW from Address Mat ch 15 20 20 ns

tBHA BUSY HIGH from Address Mismatch[16] 15 20 20 ns

tBLC BUSY LOW from CE LOW 15 20 20 ns

tBHC BUSY HIGH from CE HIGH[16] 15 20 20 ns

tPS Port Set Up for Priority 5 55ns

WB[17] R/W LOW after BUSY LOW 0 00ns

WH R/W H IGH a fter BUS Y HIGH 13 20 30 ns

tBDD BUSY HIGH to Valid Data 15 25 30 ns

tDDD Wr ite Data Valid to Read Data Valid Note

18 Note

18 ns

tWDD Write Pulse to Data Delay Note

18 Note

18 ns

INTERRUPT TIMING

tWINS R/W t o INTERRUPT Set T i me 15 25 25 ns

tEINS CE to INTERRUPT Set Time 15 25 25 ns

tINS Address to INTERRUPT Se t T ime 15 25 25 ns

tOINR OE to INT ERRUPT Reset Time[16] 15 25 25 ns

tEINR CE to INTERRUPT Reset Time[16] 15 25 25 ns

tINR Address to INTERRUPT Re set T im e[16] 15 25 25 ns

Notes:

16. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state.

17. CY7C140/CY7C141 only.

18. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following:

BUSY on Port B goes H IGH.

Port B’s addr ess is to ggled.

CE for P ort B i s toggled.

R/W for Po rt B is tog gled dur ing v alid read .

Switching Characteristics Over the Operatin g Range[6,11]

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55

Parameter Description Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

tRC Read Cycle Time 35 45 55 ns

tAA Address to Data Valid[12] 35 45 55 ns

tOHA Data Hold from Address Change 0 0 0 ns

tACE CE LOW to Data Val id[12] 35 45 55 ns

tDOE OE LOW to Data Valid[12] 20 25 25 ns

tLZOE OE LOW to Low Z[9,13, 14] 333ns

HZOE OE HIGH to High Z[9,13, 14] 20 20 25 ns

tLZCE CE LOW to Low Z[9,13, 14] 555ns

HZCE CE HIGH to High Z[9,13, 14] 20 20 25 ns

tPU CE LOW to Power-Up[9] 000ns

PD CE HIGH to Power-Down[9] 35 35 35 ns

Switching Characteristics Over the Operating Range[6,11] (con tinued)

7C131-15[3,4]

7C141-15

7C130-25[3]

7C131-25

7C140-25

7C141-25

7C130-30

7C131-30

7C140-30

7C141-30

Parameter Description Min. Max. Min. Max. Min. Max. Unit

CY7C130/CY7C131

CY7C140/CY7C141

WRITE CYCLE[15]

tWC Write Cycle Time 35 45 55 ns

tSCE CE LOW to Write End 30 35 4 0 ns

tAW Address Set-Up to Write End 30 35 4 0 ns

tHA Address Hold from Write End 2 2 2 ns

tSA Address Set-Up to Write Start 0 0 0 ns

tPWE R/W Pu lse Wi dt h 25 30 30 ns

tSD Dat a Set-U p to Write End 15 2 0 2 0 n s

tHD Data Hold from Write End 0 0 0 ns

tHZWE R/W LOW to High Z[14] 20 20 25 ns

tLZWE R/W HIGH to Low Z[14] 000ns

BUSY/INTERRUPT TIMING

tBLA BUSY LOW from Address Match 20 25 30 ns

tBHA BUSY HIGH from Address Mismatch[16] 20 25 30 ns

tBLC BUSY LOW from CE LOW 20 25 30 ns

tBHC BUSY HIGH from CE HIGH[16] 20 25 30 ns

tPS Port Set Up for Priority 5 5 5 ns

tWB[17] R/W LOW after BUSY LOW 0 0 0 ns

tWH R/W HIGH after BUSY H IG H 30 35 35 ns

tBDD BUSY HIGH to Valid Data 35 45 45 n s

tDDD Write Dat a Valid to Read Data Valid Note

18 Note

18 ns

tWDD Write Pulse t o Data Delay Note

18 Note

18 ns

INTERRUPT TIMING

tWINS R/W to IN TERRUP T S e t Ti m e 25 35 45 ns

tEINS CE to INTERRUPT Set Time 25 35 45 n s

tINS Address to INTERRUPT S et Ti m e 25 35 45 ns

tOINR OE to INTERRUPT Reset Time[16] 25 35 45 ns

tEINR CE to INTERRUPT Reset Time[16] 25 35 45 ns

tINR Address to INTERRUPT Reset Ti me[16] 25 35 45 ns

Switching Characteristics Over the Operatin g Range[6,11] ( contin ued)

7C130-35

7C131-35

7C140-35

7C141-35

7C130-45

7C131-45

7C140-45

7C141-45

7C130-55

7C131-55

7C140-55

7C141-55

Parameter Description Min. Max. Min. Max. Min. Max. Unit

Switching Waveforms

Notes:

19. R/W is HIG H for rea d cycle.

20. Device is continuously selected, CE = V IL and OE = VIL.

Read Cycle No.1 tRC

tAA

tOHA

DATA VALIDPREVIOUS DATA VALID

DATA OUT

ADDRESS

C130-7

Either Port Ad dress Access

[19, 20]

CY7C130/CY7C131

CY7C140/CY7C141

Notes:

21. Address valid prior to or coincident with CE trans ition LO W.

22. If OE i s L OW duri ng a R/W controlled wr it e cycl e, the wr ite pulse width must be the l arg er of t PWE or tHZWE + tSD to allow the data I/O pins to enter high impedanc e and for data

to be pl aced o n the bus for the required tSD.

Switching Waveforms (cont inued)

tACE

tLZOE tDOE tHZOE

tHZCE

DATA VALID

DATA OUT

tLZCE

tPU

ICC

ISB

tPD

Read Cycle No. 2

tBHA

tBDD

VALID

tDDD

tWDD

ADDRESS MATCH

R/WR

ADDRESSR

DINR

ADDRESSL

BUSYL

DOUTL

Read Cycle No.3

Write CycleNo.1 (OE Thr e e-States Data I/O s - Either Port )

tAW

tWC

DATA VALID

HIGH IMPEDANCE

tSCE

tSA tPWE

tHD

tSD

tHA

R/W

ADDRESS

tHZOE

DOUT

DATAIN

Either Port CE/OE Access

Either Port

C130-8

C130-9

C130-10

tPS

tBLA

Read with BUSY, Master: CY7C130 and CY7C13 1

tRC

tPWE

VALID

tHD

[19, 21]

[20]

[15, 22]

CY7C130/CY7C131

CY7C140/CY7C141

Note:

23. If the CE LOW tran sition occurs s imultaneous ly wi th or after th e R/W L OW transiti on, the ou tputs remai n in the high- impedan ce st ate

Switching Waveforms (cont inued)

Write Cycle No. 2 (R/W Three-States Data I/Os - Either Port)

tAW

tWC

tSCE

tSA tPWE

tHD

tSD

tHZWE

Either Port

tHA

HIGH IMPE DANCE

ADDRESS MATCH

tPS

Busy Timing Diagram No. 1 (CE Arbitration)

CELValid First:

tBLC tBHC

ADDRESS MATCH

tPS

tBLC tBHC

CERValid First:

DATAVALID

tLZWE

C130-11

C130-12

C130-13

ADDRESS

R/W

DATAOUT

DATAIN

ADDRESSL,R

BUSYR

CEL

CER

BUSYL

CER

CEL

ADDRESS

L,R

[16, 23]

CY7C130/CY7C131

CY7C140/CY7C141

Switching Waveforms (cont inued)

Busy Ti ming Diagram No. 2 (Addre ss Arbitration)

Left Address Valid First:

ADDRESS MATCH

tPS

ADDRESSL

BUSYR

ADDRESS MI SMATCH

tRC or tWC

tBLA tBHA

ADDRESSR

ADDRESS MATCH AD DRESS MI SMATCH

tPS

ADDRESSL

BUSYL

tRC or tWC

tBLA tBHA

ADDRESSR

Right Address Valid First:

tPWE

tWB tWH

Busy Ti ming Diagram No. 3

Write with BUSY (Slave:CY7C140 /CY7C14 1 )

C130-14

C130-15

C130-16

BUSY

R/W

CY7C130/CY7C131

CY7C140/CY7C141

Switching Waveforms (cont inued)

Interrupt Timing Diagrams

WRITE 3FF

tINS

tWC

tEINS

Right Side Clears INTR

tHA

tSA tWINS

READ 3FF

tRC

tEINR

tHA tINT

tOINR

WRITE 3FE

tINS

tWC

tEINS

tHA

tSA tWINS

Right Side Sets INTL

Left Side Sets INTR

Left Side Clears INTL

READ 3FE

tEINR

tHA tINR

tOINR

tRC

C130-17

C130-18

C130-19

C130-20

ADDRR

CEL

R/WL

INTL

OEL

ADDRR

R/WR

CER

INTL

ADDRR

CER

R/WR

INTR

OER

ADDRL

R/WL

CEL

INTR

CY7C130/CY7C131

CY7C140/CY7C141

Ty pical DC and AC Characteristics

1.4

1.0

0.4

4.0 4.5 5.0 5.5 6.0 -55 25 125

1.2

1.0

120

100

0 1.0 2.0 3.0 4.0

SU PPLY VOLTAGE ( V)

NORMAL IZED SUPP LY CURRENT

vs.SUPPLYVOLTAGE NORMALIZED SUPPLY CURRENT

vs. AMBIENT TEMPERATURE

AMBI ENT TEMPERATURE ( °C) OUTPUT VOLTAGE (V)

OUTPUT SOURCE CURRENT

vs. OUTPUT V OLTAGE

0.0

0.8 0.8

0.6

VCC =5.0V

VIN =5.0V VCC =5.0V

TA=25°C

ICC

1.6

1.4

1.2

1.0

0.8

-55 125

NORMALIZED ACCESS TIME

vs. AMBIENT TEMPERATURE

AMBI ENT TEMPERATURE ( °C)

1.4

1.3

1.2

1.0

0.9

4.0 4.5 5.0 5.5 6.0

SUPPLYVOLTAGE (V)

NORMALIZED ACCESS TIME

vs. SUPPLY VO LTAGE

120

140

100

0.0 1.0 2.0 3.0 4.0

OUTPUT VOLTAGE (V)

OUTPUT SINK CURRENT

vs.OUTPUT VOLTAGE

VCC =5.0V

TA=25°C

0.6

0.8

VCC =5.0V

TA=25°C

1.25

1.0

0.75

10 40

0.50

NORMALIZED ICC vs.CYCLETIME

CYCLE FREQUENC Y (M Hz)

3.0

2.5

2.0

1.5

0.5

0 1.0 2.0 3.0 5.0

25.0

30.0

20.0

10.0

5.0

0 200 400 600 800

15.0

0.0

SUPPLYVOLTAGE (V)

TYPICAL POW ER -ON CURRENT

vs. SUPPLY VOLTAGE

CAPACITANCE (pF)

TYPICAL ACCESS TIME CHANGE

vs. OUTPUT LOADING

4.0 1000

1.0

20 30

0.2

0.6

1.2

ISB3 0.2

0.4

ISB3

1.1

VCC =4.5V

TA=25°C

VCC =4.5V

TA=25°C

VIN =0.5V

CY7C130/CY7C131

CY7C140/CY7C141

Orde rin g Inf orm a tio n

Shaded area contains preliminary information.

Speed

(ns) Ordering Code Package

Name Package Type Operating

Range

30 CY7C130-30PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C130-30PI P25 48-Lead (600-Mil) Molded DIP Industrial

35 CY7C130-35PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C130-35PI P25 48-Lead (600-Mil) Molded DIP Industrial

CY7C130-35DMB D26 48-Lead (600-Mil) Sidebraze DIP Military

45 CY7C130-45PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C130-45PI P25 48-Lead (600-Mil) Molded DIP Industrial

CY7C130-45DMB D26 48-Lead (600-Mil) Sidebraze DIP Military

55 CY7C130-55PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C130-55PI P25 48-Lead (600-Mil) Molded DIP Industrial

CY7C130-55DMB D26 48-Lead (600-Mil) Sidebraze DIP Military

Speed

(ns ) Orderi ng Co de Package

Name Package Type Operating

Range

15 CY7C131-15JC J69 52-Lead Plastic L e aded Chip Carrier Commercial

CY7C131-15NC N52 52-Pin Plastic Quad Flatpack

25 CY7C131-25JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C131-25NC N52 52- Pin Plastic Quad Flatpack

CY7C131-25JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C131-25NI N5 2 52- Pin Plastic Quad Flatpack

30 CY7C131-30JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C131-30NC N52 52- Pin Plastic Quad Flatpack

CY7C131-30JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

35 CY7C131-35JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C131-35NC N52 52- Pin Plastic Quad Flatpack

CY7C131-35JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C131-35NI N5 2 52- Pin Plastic Quad Flatpack

45 CY7C131-45JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C131-45NC N52 52- Pin Plastic Quad Flatpack

CY7C131-45JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C131-45NI N5 2 52- Pin Plastic Quad Flatpack

55 CY7C131-55JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C131-55NC N52 52- Pin Plastic Quad Flatpack

CY7C131-55JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C131-55NI N5 2 52- Pin Plastic Quad Flatpack

CY7C130/CY7C131

CY7C140/CY7C141

Orde rin g Inf orm a tio n (continued)

Shaded area contains preliminary information.

Speed

(ns) Or dering Code Package

Name Package Type Operating

Range

30 CY7C140-30PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C140-30PI P25 48-Lead (600-Mil) Molded DIP Industrial

35 CY7C140-35PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C140-35PI P25 48-Lead (600-Mil) Molded DIP Industrial

CY7C140-35DMB D26 48-Lead (600-Mil) Sidebraze DIP Military

45 CY7C140-45PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C140-45PI P25 48-Lead (600-Mil) Molded DIP Industrial

CY7C140-45DMB D26 48-Lead (600-Mil) Sidebraze DIP Military

55 CY7C140-55PC P25 48-Lead (600-Mil) Mol ded DIP Commercial

CY7C140-55PI P25 48-Lead (600-Mil) Molded DIP Industrial

CY7C140-55DMB D26 48-Lead (600-Mil) Sidebraze DIP Military

Speed

(ns ) Orderi ng Co de Package

Name Package Type Operating

Range

15 CY7C141-15JC J69 52-Lead Plastic L e aded Chip Carrier Commercial

CY7C141-15NC N52 52-Pin Plastic Quad Flatpack

25 CY7C141-25JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C141-25NC N52 52- Pin Plastic Quad Flatpack

CY7C141-25JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C141-25NI N5 2 52- Pin Plastic Quad Flatpack

30 CY7C141-30JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C141-30NC N52 52- Pin Plastic Quad Flatpack

CY7C141-30JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

35 CY7C141-35JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C141-35NC N52 52- Pin Plastic Quad Flatpack

CY7C141-35JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C141-35NI N5 2 52- Pin Plastic Quad Flatpack

45 CY7C141-45JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C141-45NC N52 52- Pin Plastic Quad Flatpack

CY7C141-45JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C141-45NI N5 2 52- Pin Plastic Quad Flatpack

55 CY7C141-55JC J69 52-Lead Plastic Leaded Chip Carrier Commercial

CY7C141-55NC N52 52- Pin Plastic Quad Flatpack

CY7C141-55JI J69 52-Lead Plastic Leaded Chip Carrier In dustrial

CY7C141-55NI N5 2 52- Pin Plastic Quad Flatpack

CY7C130/CY7C131

CY7C140/CY7C141

MIL ITARY SPECIFICAT IONS

Group A Subgroup Testing

DC Characteristics

Switching Characteristics

Note:

24. CY7C140/CY7C141 only.

Document #: 38-00027-L

Parameter Subgroups

VOH 1, 2, 3

VOL 1, 2, 3

VIH 1, 2, 3

VIL Max. 1, 2, 3

IIX 1, 2, 3

IOZ 1, 2, 3

ICC 1, 2, 3

ISB1 1, 2, 3

ISB2 1, 2, 3

ISB3 1, 2, 3

ISB4 1, 2, 3

Parameter Subgroups

READ CYCLE

tRC 7, 8, 9, 10, 11

tAA 7, 8, 9, 10, 11

tACE 7, 8, 9, 10, 11

tDOE 7, 8, 9, 10, 11

WRITE CYCLE

tWC 7, 8, 9, 10, 11

tSCE 7, 8, 9, 10, 11

tAW 7, 8, 9, 10, 11

tHA 7, 8, 9, 10, 11

tSA 7, 8, 9, 10, 11

tPWE 7, 8, 9, 10, 11

tSD 7, 8, 9, 10, 11

tHD 7, 8, 9, 10, 11

Parameter Subgroups

BUSY/INTERRUPT TIMING

tBLA 7, 8, 9, 10, 11

tBHA 7, 8, 9, 10, 11

tBLC 7, 8, 9, 10, 11

tBHC 7, 8, 9, 10, 11

tPS 7, 8, 9, 10, 11

tWINS 7, 8, 9, 10, 11

tEINS 7, 8, 9, 10, 11

tINS 7, 8, 9, 10, 11

tOINR 7, 8, 9, 10, 11

tEINR 7, 8, 9, 10, 11

tINR 7, 8, 9, 10, 11

BUSY TIMING

tWB[24] 7, 8, 9, 10, 11

tWH 7, 8, 9, 10, 11

tBDD 7, 8, 9, 10, 11

CY7C130/CY7C131

CY7C140/CY7C141

Package Diagrams

48-Lead (600-Mil) Sidebraze DIP D26

52-Lead Plastic LeadedChip Carrier J69

CY7C130/CY7C131

CY7C140/CY7C141

of any circui try other than c ircui try embodied in a Cypre ss Semic onducto r produc t. Nor does it con vey or impl y any lice nse under patent o r other ri ghts. Cypress Semi conductor does not authoriz e

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams (c ontinu ed)

48-Lead (600-Mil) Molded DIP P25