March 2008
©1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2
FST3245 — 8-Bit Bus Switch
FST3245 — 8-Bit Bus Switch
Features
4Ω Switch Connection between Two Ports
Minimal Propagation Delay through the Switch
Low ICC
Zero Bounce in Flow-through Mode
Control Inputs Compatible with TTL Level
Description
The FST3245 switch provides eight-bits of high-speed
CMOS TTL-compatible bus switching in a standard ’245
pin-out. The low on resistance allows inputs to be
connected to outputs without adding propagation delay
or generating additional ground bounce noise.
The device is organized as an eight-bit switch. When
/OE is LOW, the switch is ON and port A is connected
to port B. When /OE is HIGH, the switch is OPEN and a
high-impedance state exists between the two ports.
Ordering Information
Part Number Operating
Temperature
Range Package Packing
Method
FST3245WMX -40 to +85°C 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC
MS-013, 0.300-inch Wide Tape and Reel
FST3245QSC -40 to +85°C 20-Lead Quarter Size Outline Package (QSOP), JEDEC
MO-137, 0.150-inch Wide Tube
FST3245QSCX -40 to +85°C 20-Lead Quarter Size Outline Package (QSOP),
JEDEC MO-137, 0.150-inch Wide Tape and Reel
FST3245MTC -40 to +85°C 20-Lead Thin Shrink Small Outline Package (TSSOP),
JEDEC MO-153, 4.4mm Wide Tube
FST3245MTCX -40 to +85°C 20-Lead Thin Shrink Small Outline Package (TSSOP),
JEDEC MO-153, 4.4mm Wide Tape and Reel
All pac kages are lead free per J EDEC: J-S T D-020B standard.
The Fairchild switch family derives from and embodi es Fairchild’ s proven switch technology used for s everal years in its
74LVX3L384 (FST3384) bus switc h product.
Logic Diagram
18
11
B
0
B
7
19
2
9
/OE
A
7
A
0
Figure 1. Logic Diagram
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 2
FST3245 — 8-Bit Bus Switch
Pin Configuration
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
A
3
A
4
A
5
A
6
A
7
NC
A
0
A
1
A
2
GND B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
/OE
V
CC
Figure 2. Pin Configuration
Pin Descriptions
Pin # Pin Names Description
1 NC No Connnect
19 /OE Bus Switch Enable
2,3,4,5,6,7,8,9 A0,A1,A2,A3,A4,A5,A6,A7 Bus A
10 GND Ground
11,12,13,14,15,16,17,18 B7,B6,B5,B4,B3,B2,B1,B0 Bus B
20 VCC Supply Voltage
Truth Table
Input /OE Function
LOW Connect
HIGH Disconnect
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 3
FST3245 — 8-Bit Bus Switch
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage -0.5 7.0 V
VS DC Switch Voltage -0.5 7.0 V
VIN DC Input Voltage(1) -0.5 7.0 V
IIK DC Input Diode Current, VIN < 0V -50 mA
IOUT DC Output Sink Current 128 mA
ICC / IGND DC VCC / GND Current ±100 mA
TSTG Storage Temperature Range -65 +150 °C
Note:
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Max. Unit
VCC Power Supply Operating 4.0 5.5 V
VIN Input Voltage 0 5.5 V
VOUT Output Voltage 0 5.5 V
Switch Control Input(2) 0 5
tr, tf Input Rise and Fall Time Switch I/O 0 DC ns/V
TA Operating Temperature, Free Air -40 +85 °C
Note:
2. Unused control inputs must be held HIGH or LOW. They may not float.
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 4
FST3245 — 8-Bit Bus Switch
DC Electrical Characteristics
Typical values are at VCC = 5.0V and TA = 25°C.
TA=-40 to +85°C
Symbol Parameter Conditions VCC (V) Min. Typ. Max.
Units
VIK Clamp Diode Voltage IIN = -18mA 4.5 -1.2 V
VIH High-Level Input Voltage 4.0 to 5.5 2.0 V
VIL Low-Level Input Voltage 4.0 to 5.5 0.8 V
IIN Input Leakage Current 0 ≤ VIN ≤ 5.5V 5.5 ±1.0 µA
IOZ Off-state Leakage
Current 0 ≤ A, B ≤ VCC 5.5 ±1.0 µA
VIN = 0V, IIN = 64mA 4.5 4 7
VIN = 0V, IIN = 30mA 4.5 4 7
VIN = 2.4V, IIN = 15mA 4.5 8 15
RON Switch On Resistance(3)
VIN = 2.4V, IIN = 15mA 4.0 11 20
Ω
ICC Quiescent Supply Current VIN = VCC or GND,
IOUT = 0 5.5 3 µA
ΔICC Increase in ICC per Input One Input at 3.4V, Other
Inputs at VCC or GND 5.5 2.5 mA
Note:
3. Measured by the voltage drop between the A and B pins at the indicated current through the switch. On
resistance is determined by the lower of the voltages on the A or B pins.
AC Electrical Characteristics
TA = -40 to +85°C, CL = 50pF, and RU = RD = 500Ω.
VCC = 4.5 – 5.5V VCC = 4.0V
Symbol Parameter Conditions
Min. Max. Min. Max.
Units Figure
tPHL, tPLH Propagation Delay
Bus-to-Bus(4) VIN = Open 0.25 0.25 ns Figure 3
Figure 4
tPZH ,tPZL Output Enable Time VIN = 7V for tPZL
VIN = Open for
tPZH 1.5 5.9 6.4 ns
Figure 3
Figure 4
tPHZ, tPLZ Output Disable Time VIN = 7V for tPLZ
VIN = Open for
tPHZ 1.5 6.0 5.7 ns
Figure 3
Figure 4
Note:
4. This parameter is guaranteed by design, but is not tested. The bus switch contributes no propagation delay
other than the RC delay of the typical on resistance of the switch and the 50pF load capacitance when driven by
an ideal voltage source (zero output impedance).
Capacitance
TA = +25°C, f = 1MHz. Capacitance is characterized, but not tested.
Symbol Parameter Conditions Typ. Units
CIN Control Pin Input Capacitance VCC = 5.0V 3 pF
CI/O Input/Output Capacitance VCC, /OE = 5.0V 5 pF
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 5
FST3245 — 8-Bit Bus Switch
AC Loadings and Waveforms
Notes: Input driven by 50Ω source terminated in 50Ω.
CL includes load and stray capacitance.
Input PRR = 1.0MHz, tw = 500ns.
Figure 3. AC Test Circuit
Figure 4. AC Waveforms
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 6
FST3245 — 8-Bit Bus Switch
Physical Dimensions
0.10 C
C
A
SEE DETAIL A
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MS-013, VARIATION AC, ISSUE E
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
E) LANDPATTERN STANDARD: SOIC127P1030X265-20L
PIN ONE
INDICATOR 0.25
110
BCA
M
20 11
B
X 45°
8°
0°
SEATING PLANE
GAGE PLANE
DETAIL A
SCALE: 2:1
SEATING PLANE
LAND PATTERN RECOMMENDATION
F) DRAWING FILENAME: MKT-M20BREV3
0.65
1.27
2.25
9.50
13.00
12.60
11.43
7.60
7.40
10.65
10.00
0.51
0.35 1.27
2.65 MAX
0.30
0.10
0.33
0.20
0.75
0.25
(R0.10)
(R0.10)
1.27
0.40
(1.40)
0.25
D) CONFORMS TO ASME Y14.5M-1994
Figure 5. 20-Lead, Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300-inch Wide
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 7
FST3245 — 8-Bit Bus Switch
Physical Dimensions
SIDE VIEW
TOP VIEW
DETAIL A
END VIEW
LAND PATT ERN
RECOMMENDATION
Figure 6. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150-inch Wide
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor represent ative to v er ify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 8
FST3245 — 8-Bit Bus Switch
Physical Dimensions
Figure 7. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pack age drawings are provided as a service to customers consideri ng Fai rchild components . Drawings may c hange i n any manner
without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’ s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 1997 Fairchild Semiconductor Corporation www.fairchildsemi.com
FST3245 • Rev. 1.0.2 9
FST3245 — 8-Bit Bus Switch
