February 2016 DocID026980 Rev 4 1/44
VIPer35
Quasi-resonant high performance off line high voltage converter
Datasheet
-
production data
Figure 1. Basic application schematic
Features
•800 V avalanche-rugged power MOSFET
allowing ultra wide range input V
AC
to be
achieved
•Embedded HV start-up and senseFET
•Built- in so ft- sta rt
•Quasi-resonant current mode PWM controller
with drain current limit (I
Dlim
)
•Multifun cti on ZC D pin:
– Zero-current detection
– OCP threshold (I
Dlim
) setup
– Output OVP (auto-restart)
– Feed-forward compensation
•Support isolated flyback topology with opto-
coupler
•Freque nc y limit:
– 136 kHz (L type), 225 kHz (H type)
•Less than 30 mW @ 230 V
AC
in no-load
condition
•Brown-out set through resistor divider
•Short-circuit protection (auto-restart)
•Hysteretic thermal shutdown
Applications
•Auxiliary power supply
•Adapter/charger for PDA, camcorders,
shavers, tablet, video games, STB
•Supplies for industrial systems, metering,
appliances
Description
The device is a high voltage converter, which
smartly integrates an 800 V rugged power
MOSFET with a quasi-resonant current mode
PWM co ntrol. Th is IC meets severe energy
saving standards as it has very low consumption
and operates in burst mode under light load
conditions.
The device features the brown-out enabling the
IC to set the switch-off and switch-on threshold
independently one of each other. The quasi-
resonant operation reduces the level of EMI and
the quantity of components in the application.
The quasi-resonant operation reduces the
switching losses and improves power conversion
efficiency. The device features high level
protections such as: output overvoltage, short-
circuit and thermal shutdown with hysteresis.
After the removal of a fault condi tio n, the IC is
automatically restarted.
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Contents VIPer35
2/44 DocID026980 Rev 4
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Typical output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Typical circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Efficiency performance for a typical flyback converter . . . . . . . . . . . . 18
8 Operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.2 High voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.3 Power-up and soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8.4 Power-down description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.5 Auto- restart description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.6 Quasi- resonant operation (QR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.7 Frequency foldback function and val ley-skipping mode . . . . . . . . . . . . . . 25
8.8 Blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.9 Starter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8.10 Current limit set-point and feed-forward option . . . . . . . . . . . . . . . . . . . . 27
8.11 Overvoltage protection (O VP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.12 ZCD pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.13 Feedback and overload prote ction (OLP) . . . . . . . . . . . . . . . . . . . . . . . . 32
8.14 Burst mode operati on at no-load or very light load . . . . . . . . . . . . . . . . . . 35
8.15 Brown-o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DocID026980 Rev 4 3/44
VIPer35 Contents
44
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.1 SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.2 SDIP10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
List of tables VIPer35
4/44 DocID026980 Rev 4
List of tables
Table 1. Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Controller section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Power supply efficiency, V
OUT
= 12 V, V
IN
= 115 V
AC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Power supply efficiency, V
OUT
= 12 V, V
IN
= 230 V
AC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. ZCD pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 11. SO16N mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 12. SDIP10 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 13. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DocID026980 Rev 4 5/44
VIPer35 List of figures
44
List of figures
Figure 1. Basic application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. V
DDon
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. V
DD(RESTART)
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. I
Dlim
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. V
DRAIN_START
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. H
FB
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. V
BRth
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. V
BRhyst
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. I
BRhys
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 12. I
DD0
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 13. I
DD1
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 14. V
ZCD
vs I
ZCD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 15. I
Dlim
vs I
ZCD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 16. R
DS(on)
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 17. V
BVDSS
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 18. I
DDch1
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 19. I
DDch2
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 20. F
OSClim_L
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 21. F
OSClim_H
vs T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. Thermal shutdown timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 23. Min-feature quasi-resonant flyback (isolated). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 24. Full-feature quasi-resonant flyback (isolated). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 25. Power supply consumption at light output loads, V
OUT
= 12 V. . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. Power supply consumption at no output load, V
OUT
= 12 V . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. I
DD
current during start-up and burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Timing diagram: normal power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. Timing diagram: start-up phase and soft-start (case 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 30. Timing diagram: start-up phase and soft-start (case 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 31. Timing diagram: behavior after short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 32. Switching frequency vs power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Zero-current detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 34. Drain ringing cycle skipping as the load progressively reduces . . . . . . . . . . . . . . . . . . . . . 25
Figure 35. Timing diagram: double blanking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 36. Typical power capability vs input voltage in quasi-resonant converter. . . . . . . . . . . . . . . . 28
Figure 37. ZCD pin typical external configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 38. Timing diagram: OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 39. FB pin configuration (minimal BOM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. FB pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 41. Timing diagram: overload protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 42. Burst mode timing: light load management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 43. Brown-out: external setting and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 44. SO16N package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 45. SDIP10 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Block diagram VIPer35
6/44 DocID026980 Rev 4
1 Block diagram
Figure 2. Block diagram
2 Typical output power
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Table 1. Typical power
Part number 230 V
AC
85-265 V
AC
Adapter
(1)
1. Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient.
Op en frame
(2)
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate
heatsinking.
Adapter
(1)
Open frame
(2)
VIPER35 20 W 22 W 15 W 16 W
DocID026980 Rev 4 7/44
VIPer35 Pin settings
44
3 Pin settings
Figure 3. Connection diagram
Note: The copper area for heat dissipation has to be designed under the DRAIN pins.
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Table 2. Pin description
SO16N SDIP10 Name Function
1, 2 1 GND Device ground and source of the power MOSFET.
3 - N.C. Not internally connected. It can be connected to GND.
4-N.A.
Not availab le for user. This pin is mechan ically conn ected to the c ontroller die pad of
the frame. In order to improve the noise immunity it should be connected to GND
(pin 1, 2).
5 2 VDD Supply voltage of the control section. This pin provides the charging current of the
external capacitor during the power-up.
63ZCD
Multif un cti on pin :
1. Zero-current detection for quasi-resonant operations.
2. Drain current limit (I
Dlim)
setup for overcurre nt protection (R
LIM
).
3. Feed-forward compensation (R
FF
) setup.
4. Output overvoltage protection (resistor divider R
OVP
/ R
LIM
) setup.
74FB
Control input for duty cycle control. Internal current generator provides bias current
for loop regulation. A voltage below the threshold V
FBbm
activates the burs t-mode
operation. A level close to the threshold V
FBlin
means that the cycle- by-cycle
overcurrent set-point is close.
85BR
Brown-out protection input with hysteresis. A voltage below the threshold V
BRth
shuts down (not latch) the device and lowers the power consumption. The device
operation restarts as the voltage exceeds the threshold V
BRth
+ V
BRhyst
. It must be
connected to ground when it is not used.
9 to 12 - N.C. Not internally connected. These pins must be left floating in order to get a safe
clearance distance.
13 to 16 6 to 10 DRAIN High voltage drain pin. The built-in high voltage switched start-up bias current is
drawn from this pin. Pins connected to the metal frame facilitate heat dissipation.
Electrical ratings VIPer35
8/44 DocID026980 Rev 4
4 Electrical ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
Min. Max.
V
DRAIN
Drain-to-source (ground) voltage 800 V
E
AV
Repetitive avalanche energy (limited by T
J
= 150 °C) 5 mJ
I
AR
Repetitive avalanche current (limited by T
J
= 150 °C) 1.5 A
I
DRAIN
Single pu lse drain current 3 A
V
ZCD
Input pin voltage (with I
ZCD
= 1 mA) -0.3 Self limited V
V
FB
Input pin voltage -0.3 5.5 V
V
BR
Input pin voltage (with I
BR
= 0.25 mA) -0.3 Self limited V
V
DD
Supply voltage -0.3 Self limited V
I
DD
Input current 25 mA
P
TOT
Power dissipation at T
A
< 60 °C 1.5 W
T
J
Operati ng jun cti on tem per ature range -40 150 °C
T
STG
St orage temper ature -55 150 °C
Table 4. Thermal data
Symbol Parameter Ma x. value Unit
SDIP10 SO16N
R
thJP
Thermal resistance junction pin
(dissipated po wer = 1 W) 35 35 °C/W
R
thJA
Thermal resistance junction ambient
(dissipated po wer = 1 W) 100 110 °C/W
R
thJA
Thermal resistance junction ambient
(1)
(dissipated po wer = 1 W) 85 80 °C/W
1. When mounted on a standard single side FR4 board with 100 mm
2
(0.155 sq inch) of Cu (35 µm thick).
DocID026980 Rev 4 9/44
VIPer35 Electrical ratings
44
T
J
= -40 to 125 °C, V
DD
= 14 V
(a)
(unless otherwise specified)
T
J
= -40 to 125 °C (unless otherwise specified)
a. Adjust V
DD
above V
DDon
start-up threshold before setting 14 V.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
BVDSS
Breakdown voltage I
DRAIN
= 1 mA, V
FB
= GN D
T
J
= 25 °C 800 V
I
OFF
Off-state drain
current V
DRAIN
= 800 V
V
FB
= GND, T
J
= 25 °C 60 uA
R
DS(on)
Drain-source on-
state resista nce
I
DRAIN
= 0.4 A, VFB = 3 V
V
BR
= GND, T
J
= 25 °C 4.5
I
DRAIN
= 0.4 A, VFB = 3 V
V
BR
= GND, T
J
= 125 °C 9
C
OSS
Effective (energy
related) output
capacitance V
DRAIN
= 0 to 640 V 17 pF
Table 6. Supply section
Symbol Parameter Test conditions Min. Typ. Max. Unit
Voltage
V
DRAIN_START
Drain-source start
voltage 60 80 100 V
I
DDch1
Sta rt-up charging
current (power-up)
V
DRAIN
= 120 V
V
BR
= GN D
V
FB
= GND
V
DD
= 4 V
-2 -3 -4 mA
I
DDch2
Sta rt-up charging
current (auto-restart)
V
DRAIN
= 120 V
V
BR
= GN D
V
FB
= GND
V
DD
= 5 V, after fault
-0.4 -0.6 -0.8 mA
V
DD
Operating voltage
range After turn-on 8.5 23.5 V
V
DDclamp
Clamp vol tage I
DD
= 20 mA 23.5 V
V
DDon
V
DD
sta rt-up
threshold V
DRAIN
= 120 V
V
BR
= GN D
V
FB
= GND
13 14 15 V
V
DDoff
V
DD
undervoltage
shut d ow n thre shold 7.5 8 8.5 V
V
DD(RESTART)
V
DD
restart vo ltage
threshold 44.55V
Electrical ratings VIPer35
10/44 DocID026980 Rev 4
T
J
= -40 to 125 °C (unless otherwise specified)
Current
I
DD0
Operating supply
current, not switching
V
FB
= GND
V
BR
= GN D
V
DD
= 10 V
(1)
0.6 0.7 mA
I
DD1
Operating supply
curr ent sw itching
V
DRAIN
= 120 V
V
DD
= 16 V
ZCD switching @100 kHz
Resistiv e load:100
V
FB
= 2.5 V
23mA
I
DD_FAULT
Operating supply
current with
protection tr ipping VDD = 10 V 400 uA
I
DDoff
Operating supply
current V
DD
< V
DDoff
270 uA
1. Adjust V
DD
above V
DDon
start-up threshold before setting 10 V.
Table 6. Supply section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Table 7. Controller section
Symbol Parameter Test conditions Min. Typ. Max. Unit
Feedback pin
V
FBolp
Overload shutdown
threshold 4.5 4.8 5.2 V
V
FBlin
Linear dynamics
upper limit 3.1 3.3 3.5 V
V
FBbm
Burst mode
threshold Voltage falling 0.56 0.6 0.64 V
V
FBbmhys
Burst mode
hysteresis V o lt age rising 100 mV
I
FB
Feedback sourced
current V
FB
= 0.3 V -150 -215 -280 µA
3.3 V < V
FB
< 4 V -2.5 -3 -3.5 µA
R
FB(DYN)
Dynamic resistance V
FB
> 2.5
V1225k
H
FB
ΔV
FB
/ ΔI
D
0.5 2 V/A
DocID026980 Rev 4 11/44
VIPer35 Electrical ratings
44
ZCD pin
V
ZCDCLh
Upper clamp voltage I
ZCD
= 1 mA 5 5.5 6 V
V
ZCDAth
Arming voltage
threshold Positive-going edg e 0.75 0.8 0 .85 V
V
ZCDTth
Triggering voltage
threshold Negative-going edge 0.55 0.6 0.65 V
I
ZCD
Internal pul l-up V
FB
< V
FBlin
-7.5 -10 -12.5 µA
t
DELAY
Turn-on delay after
ZCD trigger 300 ns
t
BLANK
Turn-on inhibit time
after MOSFET turn-
off
V
ZCD
< 1 V 6.3 µs
V
ZCD
>1 V 2.5 µs
Current limitation
I
Dlim
Drain current
limitation
V
FB
= 4 V
I
ZCD
= -10 µA
T
J
= 25 °C 0.9511.05A
V
FB
= 4 V
I
ZCD
= - 55 µA
T
J
= 25 °C 0.68 0.8 0.92 A
V
FB
= 4 V
I
ZCD
= - 105 µA
T
J
= 25 °C 0.55 0.65 0.75 A
t
SS
Soft-start time VIPER35L 3.5 ms
VIPER35H 4.2 ms
t
SU
Start-up time VIPER35L 7.5 15 ms
VIPER35H 9.5 18 ms
t
ON_MIN
Minimum turn-on
time 220 400 480 ns
t
d
Propagation delay (1) 100 ns
t
LEB
Leading edge
blanking (1) 300 ns
I
D_BM
Peak drain current
during burst mode V
FB
= 0.6 V 120 170 220 mA
Table 7. Controller section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Electrical ratings VIPer35
12/44 DocID026980 Rev 4
Overvoltage protection
V
OVP
Overvoltage
threshold 3.8 4.2 4.6 V
t
STROBE
Strobe time 2.2 µs
Oscillator section
F
OSClim
Internal frequency
limit VIPER35L 122 136 150 kHz
VIPER35H 200 225 250 kHz
F
STARTER
Starter frequency
V
FB
= 1 V
V
ZCD
< V
ZCDTth
t < t
SU
1/4
F
OSClim
kHz
V
FB
=1 V
V
ZCD
< V
ZCDTth
t > t
SU
1/8
F
OSClim
kHz
Brown-out protection
V
BRth
Brown-out threshold Voltage falling 0.41 0.45 0.49 A
V
BRHyst
Voltage hysteresis
above V
BRth
40 50 60 mV
I
BRHyst
Current hysteresis 7 12 µ A
V
BRclamp
Clamp voltage I
BR
= 250 µA 3 V
V
DIS
Brown-out disable
voltage 50 150 mV
Thermal shutdown
T
SD
Thermal shutdown
temperature
(1)
150 160 °C
T
HYST
Thermal shutdown
hysteresis
(1)
30 °C
1. Spec ification assured by design, characterization and statistical correlation.
Table 7. Controller section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
DocID026980 Rev 4 13/44
VIPer35 Typical electrical characteristics
44
5 Typical electrical characteristics
Figure 4. V
DDon
vs T
J
Figure 5. V
DD(RESTART)
vs T
J
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Dlim
vs T
J
Figure 7. V
DRAIN_START
vs T
J
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FB
vs T
J
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BRth
vs T
J
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14/44 DocID026980 Rev 4
Figure 10. V
BRhyst
vs T
J
Figure 11. I
BRhys
vs T
J
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DD0
vs T
J
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DD1
vs T
J
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ZCD
vs I
ZCD
Figure 15. I
Dlim
vs I
ZCD
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DocID026980 Rev 4 15/44
VIPer35 Typical electrical characteristics
44
Figure 16. R
DS(on)
vs T
J
Figure 17. V
BVDSS
vs T
J
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Figure 18. I
DDch1
vs T
J
Figure 19. I
DDch2
vs T
J
Figure 20. F
OSClim_L
vs T
J
Figure 21. F
OSClim_H
vs T
J
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16/44 DocID026980 Rev 4
Figure 22. Thermal shutdown timing diagram
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DocID026980 Rev 4 17/44
VIPer35 Typical circuits
44
6 Typical circuits
Figure 23. Min-feature quasi-resonant flyback (isolated)
Figure 24. Full-feature quasi-resonant flyback (isolated)
CVDD
RLIM
C2
GND
OPTO
VOUT
OPTO
C5
REF
BR
ZCD
DRAIN
GND
CONTROL
VDD
FB
VIPER35
BR
R2
D2
AC IN
AC IN
D3
DOVP
C3
ROVP
C4
R4
R5
C1
R3
D1
R1
GIPG2801151023LM
T3
CVDD
RLIM
C2
GND
VOUT
OPTO
OPTO
C5
REF
BR
ZCD
DRAIN
GND
CONTROL
VDD
FB
VIPER35
+
BR
R2
D2
AC IN
AC IN DOVP
R6
C6 C3
ROVP
C4
R4
R5
C1
R3
D1
R1
Rff
T3
R8
R7
D3
GIPG2801151020LM
Efficiency performance for a typical flyback converter VIPer35
18/44 DocID026980 Rev 4
7 Efficiency performance for a typical flyback
converter
The efficiency of the converter has been measured in different load and line voltage
conditions. In accordance with the Energy Star average active mode testing efficiency
method, the efficiency measurements have been performed at 25%, 50% and 75% and
100% of the rated output power, both at 115 V
AC
and 230 V
AC
.
Table 8. Power supply efficiency, V
OUT
= 12 V, V
IN
= 115 V
AC
%load I
OUT
[A] V
OUT
[V] P
OUT
[W] P
IN
[W] Effi cie ncy [%]
25% 0.31 12.1 3.78 4.53 83.47
50% 0.63 12.1 7.56 8.98 84.21
75% 0.94 12.1 11.34 13.4 84.65
100% 1.25 12.1 15.12 17.93 84.36
Average efficiency 84.17
Table 9. Power supply efficiency, V
OUT
= 12 V, V
IN
= 230 V
AC
%load I
OUT
[A] V
OUT
[V] P
OUT
[W] P
IN
[W] Effi cie ncy [%]
25% 0.31 12.1 3.78 4.71 80.28
50% 0.63 12.1 7.56 9.22 82.02
75% 0.94 12.1 11.34 13.53 83.84
100% 1.25 12.1 15.12 17.77 85.12
Average efficiency 82.82
Figure 25. Power supply consumption at light
output loads, V
OUT
= 12 V Figure 26. Power supply consumption at no
output load, V
OUT
= 12 V
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DocID026980 Rev 4 19/44
VIPer35 Operatio n descrip tio n
44
8 Operation description
The device is a high performance low voltage PWM controller chip with an 800 V,
avalanche-rugged power section.
The controller includes the PWM logic, ZCD logic for quasi-resonant operation, oscillator,
start-up circuit with soft-start, current limiting circuit with adjustable set-point, burst mode
management, brown-out circuit, UVLO circuit, auto-restart circuit and thermal protection
circuit.
The current limit set-point can be reduced by ZCD pin. Burst mode operation guarantees
high performance in standby mode and meets energy-saving standards.
All fault protections are built-in auto-restart mode with very low repetition rate to prevent the
IC overheating.
8.1 Power section and gate driver
The power section is given by an avalanche-rugged N-channel MOSFET, which guarantees
safe operation within the specified energy rating as well as high dv/dt capability. The power
MOSFET has a B
VDSS
of 800 V mi n. an d a ty pi ca l R
DS(on)
of 4.5 at 25 °C. The integrated
senseFET structure allows a virtual loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common-mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the power section cannot be turned on
accidentally.
8.2 High voltage start-up generator
The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than V
DRAIN_START
threshold, 80 V DC typically.
When HV current generator is on, I
DDch1
current (3 mA typical value) is delivered to the
capacitor on VDD pin. During auto-restart mode after a fault event, the current is reduced to
I
DDch2
(0.6 mA, typ.) in order to have a slow duty cycle during the restart phase.
8.3 Power-up and soft-start
When the input voltage reaches the device start threshold, V
DRAIN_START,
the VDD voltage
begins growing due to I
DDch1
current (see Table 7) coming from the internal high voltage
start-up circuit. If the VDD voltage reaches V
DDon
threshold, the power MOSFET starts
switching and the HV current generator turns off.
The IC is powered by the energy stored in the capacitor on V
DD
pin, C
VDD
, until the self-
supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage so high to sustain the operation.
C
VDD
capacitor must be correctly sized to avoid fast discharge and keep the required
voltage higher than V
DDoff
threshold. In fact, an insufficient capacitance value could
terminate the switching operation before the controller receives any energy from the
auxiliary winding.
Operation description VIPer35
20/44 DocID026980 Rev 4
The following formula can be used to calculate C
VDD
capacitor:
Equation 1
t
SSaux
is the time needed for the steady-state of the auxiliary voltage. It represents an
estimate of the user's application according to the output stage configurations (transformer,
output capacitances, etc.).
During the normal operation, the power MOSFET switches on after the transformer
demagnetization, detected through the voltage V
ZCD
sensed on ZCD pin.
At power-up, the initial output voltage is zero and the voltage V
ZCD
is not so high to correctly
arm the internal ZCD circuit. In this case, the power MOSFET turns on with the fixed
frequency F
STARTER
, reported in Table 7. After the start-up, as soon as the voltage on ZCD
logic is enabled to work, the turn-on of the power MOSFET is driven by this circuit and it is
not related to the internal oscillator (except for the frequency foldback function) any longer.
The start-up phase is managed by a dedicated internal logic and is activated by every
attempt of the start-up converter or after a fault.
An internal clock counter defines the start-up time, t
SU
, since during quasi-resonant
operation, the switching frequency and the duration of the start-up time depend on the load,
t
SU
range is indicated in Table 7. At the beginning of the start-up time, the drain current
limitation progressively rises to the maximum value. In this way a soft-start occurs and the
stress on the secondary diode is considerably reduced. It also prevents transformer
saturation.
The soft-start time lasts 3.5 ms (VIPER35L) or 4.2 ms (VIPER35H), (see t
SS
in Table 7).
At the start-up, until the output voltage reaches its regulated value, the feedback loop is
open and an improper activation of the overload protection could occur. In order to avoid
this, OLP logic is disabled and it is active at the end of the start-up phase, t > t
SU
. Figure 29
and Figure 30 show two possible start-up cases.
As soon as the output voltage reaches the regulated value, the regulation loop takes over
and the drain current is regulated below its limit, I
Dlim
, by the feedback voltage, which is at a
value lower than the V
FBlin
threshold.
C
VDD
I
DDch
t
SSaux
×
V
DDon
V
DDoff
–
----------------------------------------=
DocID026980 Rev 4 21/44
VIPer35 Operatio n descrip tio n
44
Figure 27. I
DD
current during start-up and burst mode
Figure 28. Timing diagram: normal power-up and power-down sequenc e
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Operation description VIPer35
22/44 DocID026980 Rev 4
Figure 29. Timing diagram: start-up phase and soft-start (case 1)
Figure 30. Timing diagram: start-up phase and soft-start (case 2)
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DocID026980 Rev 4 23/44
VIPer35 Operatio n descrip tio n
44
8.4 Power-down description
At converter power-down, the system loses its ability to regulate as soon as the decreasing
input voltage is so low to reach the peak current limitation. V
DD
voltage drops and when it
falls bel ow V
DDoff
threshold (see Table 7) the power MOSFET switches off, the energy is
interrupted, V
DD
voltage decreases, the start-up sequence is inhibited and the power-down
is completed. This feature prevents any restart attempt and ensures a monotonic output
voltage decay during the system power-down.
8.5 Auto-restart description
Every time a protection is tripped, the IC automatically restarts after a duration depending
on the discharge and recharge of C
VDD
capacitor . As shown in Figure 31, af ter a fault, the IC
stops and V
DD
voltage decreases because of IC consumption. As soon as V
DD
voltage falls
below V
DD(RESTART)
threshold and if the DC input voltage is higher than V
DRAIN_START
threshold, the internal HV current source turns on and it starts to charge C
VDD
capa citor with
the current I
DDch2
(0.6 mA, typ.). As soon as V
DD
voltage reaches V
DD(ON)
threshold, the IC
restarts.
Figure 31. Timing diagram: behavior after short-circuit
8.6 Quasi-resonant operation (QR)
The control core of the VIPER35 is a current mode PWM controller with a zero-current
detect circuit designed for quasi-resonant (QR) operation, a technique whose benefits are:
minimum turn-on losses, low EMI emission and safe behavior in case of short-circuit. At
heavy load the converter operates in quasi-resonant mode; operation synchronizes
MOSFET turn-on to the transformer demagnetization by detecting the resulting negative-
going edge of the voltage across any winding of the transformer. The system works close to
the boundary between discontinuous (DCM) and continuous conduction (CCM) of the
transformer and as a result, the switching frequency is different according to different
line/load conditions. See the hyperbolic-like portion reported in Figure 32.
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Operation description VIPer35
24/44 DocID026980 Rev 4
At medium/ light load, depending on the converter input voltage as well, the device enters
valley-skipping mode. An internal oscillator, synchronized to MOSFET turn-on, defines the
maximum operating frequency of the converter, F
OSClim
.
The VIPER35 is available as type 'L' or type 'H', depending on F
OSClim
value, see Table 7.
During the normal operation the converter works with a frequency below F
OSClim
, so the 'L'
type is suitable for applications where the priority is on the EMI filter minimization. The 'H'
type is suitable when an extended QR operation range or the transformer size reduction are
priorities.
As the load is reduced, and the switching frequency tends to exceed the oscillator’s one,
MOSFET turn-on doesn’t occur on the first valley but on the second one, the third one and
so on. In this way a “frequency clamp” effect is achieved, piecewise linear portion is showed
in Figure 32.
When the load is extremely light or disconnected, the converter enters burst mode
operation. By decreasing the load, the frequency is reduced even few hundred hertz, so to
comply with energy saving regulations or recommendations. As the peak current is low, no
audible noise occurs.
The above mentioned operation is based on ZCD pin. This pin is the input of the integrated
ZCD circuit which allows the power section turn-on at the end of the transformer
demagnetization. The input signal for the ZCD is obtained as a partition of the auxiliary
voltage used to supply the device, see Figure 33.
When the triggering circuit senses a negative-going edge below V
ZCDTth
threshold
(seeTable 7), after an internal delay that helps to achieve minimum drain-source voltage
switch-on (“valley switching”), the power MOSFET turns on. However, to enable power
MOSFET turn-on, the triggering circuit has to be previously armed by a positive-going edge
exceeding V
ZCDAth
threshold (see Table 7) on the same ZCD pin.
After the MOSFET turn-off, the blanking time, t
BLANK
, is generated to avoid an erroneous
arming and triggering due to the noise, generated by the leakage inductance resonance of
the transformer which rings and couples with ZCD pin.
Figure 32. Switching frequency vs power
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DocID026980 Rev 4 25/44
VIPer35 Operatio n descrip tio n
44
Figure 33. Zero-current detection circuit
8.7 Frequency foldback function and valley-skipping mode
The switching frequency, in quasi-resonant mode, is not fixed and it depends on both the
load and the converter input voltage. The switching frequency increases when the load
decreases, or when the mains voltage increases, and vice versa. To avoid that, the
VIPER35 tap s the maximum switching frequency of the application thanks to its control
logic.
The frequency limit is given by an internal oscillator switching at 136 kHz for the VIPER35L
or at 225 kHz for the VIPER35H, (see parameter F
OSClim
in Table 7). This oscillator is
synchronized with the power MOSFET turn-on. When the power MOSFET is off, if the first
negative-going edge voltage of the ZCD pin, resulting from transformer demagnetization,
appears after at least one oscillator cycle has been completed, the MOSFET turns on and
the oscillator is synchronized again.
Otherwise, if the first negative-going edge voltage appears before completing one oscillator
cycle, the signal is ignored. Due to the ringing of the drain voltage, the ZCD pin experiences
another positive-going edge voltage that arms the circuit and a negative-going edge voltage.
Again, if this appears before the oscillator cycle is completed, it is ignored, otherwise the
MOSFET turns on and the oscillator is synchronized. In this manner, one or more drain
ringing cycles are skipped (Figure 34 shows the so called “valley-skipping mode”) and the
switching frequency doesn’t exceed F
OSClim
limit.
Figure 34. Drain ringing cycle skipping as the load progressively reduces
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Operation description VIPer35
26/44 DocID026980 Rev 4
When the system operates in valley-skipping mode, uneven switching cycles may be
observed under some line/load conditions, due to the fact that the off-time of the power
MOSFET changes its discrete steps one ringing cycle, while the off-time needed for cycle-
by-cycle energy balance could fall in between. Therefore one or even longer switching
cycles are compensated by one or more shorter cycles and vice versa. This mechanism is
natural and any effect on the converter performance and on its output voltage appears.
This operation does not consider the blanking time t
BLANK
after power MOSFET turn-off.
Actually t
BLANK
is not taken into account as long as the following condition is met:
Equation 2
where D is the MOSFET duty cycle. If this condition is not met, the time during which
MOSFET turn-on is inhibited is extended beyond t
OSClim
by a fraction of t
BLANK
. As a
consequence, the maximum switching frequency is a little bit lower than the internal limit set
by the oscillator and valley-skipping mode takes place slightly earlier than expected.
8.8 Blanking time
The blanking time, t
BLANK
, can have two different values: the lower one is 2.5 seconds
(typical value) and the higher one is 6.3 seconds (typical value). The value is linked to the
voltage V
ZCD
, sampled during the time t
STROBE
. The time t
BLANK
has the l ower v alue i f V
ZCD
> 1 V or it has the higher value if V
ZCD
< 1 V, refer to Table 7 and Figure 35.
The higher value of the blanking time is active during the start-up phase or in case of output
short-circuit, when the output voltage of the converter is quite lower than the regulated
value. In this condition, during the demagnetization of the transformer, V
ZCD
can be very
close to the arming and triggering thresholds (V
ZCDAth
and V
ZCDTth
) and ZCD circuit can be
erroneously trigged, leading the system to work with higher frequency and in continuous
mode. This false trigger is inhibited by the selection of t
BLANK
higher value when V
ZCD
is
lower than 1 V.
During the normal operation, in steady-state condition, the voltage V
ZCD
during the
demagnetization is higher than 1 V and the selected t
BLANK
value is the lower one.
Figure 35 shows the typical waveforms during the power-up and the linked t
BLANK
selection.
D1t
BLANK
t
osclim
------------------ 1t
BLANK
F
osclim
⋅–=–≤
DocID026980 Rev 4 27/44
VIPer35 Operatio n descrip tio n
44
Figure 35. Timing diagram: double blanking time
8.9 Starter
If the amplitude of the voltage on ZCD pin at the end of one oscillator cycle is smaller than
V
ZCDAth
arming threshold, (in this case MOSFET turn-on could not be triggered), the system
stops.
This is what normally happens during the converter power-up or under overload/short-circuit
conditions.
During the converter start-up phase, the voltage on ZCD pin is not so high to arm the
triggering circuit. Thus, the converter operates at a fixed frequency, F
STARTER
, (see
Table 7). As the voltage developed across the auxiliary winding arms the ZCD circuit,
MOSFET turn-on is locked to transformer demagnetization, hence quasi-resonant operation
is set.
8.10 Current limit set-point and feed-forward option
The VIPER35 is a current mode converter and the drain current is limited cycle-by-cycle
according to FB pin voltage value, which is related to the feedback loop response and the
load. When the drain current, sensed by the integrated senseFET, reaches the current
limitation, after the internal propagation delay, the MOSFET switches off. The current
limitation cannot exceed a certain value, I
Dlim
, which can vary according to the current sunk
by ZCD pin during MOSFET on-time.
Usually a resistor, R
LIM
, connected from ZCD pin to ground fixes this sunk current and then
the peak drain current set-point: the lower the resistor, the lower I
Dlim
.
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Operation description VIPer35
28/44 DocID026980 Rev 4
For a quasi-resonant flyback converter, the power capability strongly depends on the input
voltage. In wide range applications, at maximum line, the power capability can be more than
twice the value at minimum line, as shown by the upper curve in the diagram, see Figure 36.
To reduce this dependence, the I
Dlim
has to be reduced according to the increment of the
input voltage, this is the line feed-forward. It's given by a resistor, R
FF
, connected between
the ZCD pin and the auxiliary winding, see Figure 37. Since the voltage across the auxiliary
winding during MOSFET on-time is proportional to the input voltage through the auxiliary-to-
primary turn ratio N
AUX
/N
P
, a current proportional to the input voltage is sunk by the ZCD
pin, thus the overcurrent set-point lowers.
Figure 36. Typical power capability vs input voltage in quasi-resonant converter
In order to select the R
FF
resist anc e value (se e Figure 37), when the proper overcurrent set-
points are known at minimum and at the maximum converter input voltage, in Figure 15 the
needed current to sink during MOSFET on-time is visible. With the following approximated
formula, the value of R
FF
resistor can be calculated:
Equation 3
where
•V
in
_
Max
and V
in
_
min
are the maximum and minim um con ve rt er rec tified input voltage
•N
AUX
is the primary-to-auxiliary winding turn ratio
•I
ZCD1
, and I
ZCD2
are the currents needed to sink from the ZCD pin, in order to obtain
the selected overcurrent set-points, at maximum and minimum flyback input voltage,
see Figure 15.
Given R
FF
value, R
LIM
value can be calculated by the following formula:
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V
in_Max
V
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–
N
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I
ZCD1
I
ZCD2
–()⋅
------------------------------------------------------------=
DocID026980 Rev 4 29/44
VIPer35 Operatio n descrip tio n
44
Equation 4
where:
V
ZCD1
and V
ZCD2
are ZCD pin voltages when the sunk current is I
ZCD1
and I
ZCD2
respectivel y, see Figure 14.
Figure 37. ZCD pin typical external configuration
8.11 Overvoltage protection (OVP)
The device has integrated the logic to monitor the output voltage using as input signal, the
voltage V
ZCD
during the off-time of the power MOSFET. This is the time when the voltage
from the auxiliary winding tracks the output voltage, through the turn ratio N
AUX
/ N
SEC
.
ZCD pin has to be connected to the auxiliary winding through the diode D
OVP
and the
resist ors R
OVP
and R
LIM
as shown in Figure 37. When, during the off-time, the voltage V
ZCD
exceeds, four consecutive times, the reference voltage V
OVP
(reported in Table 8), the
overvoltage protection stops the power MOSFET and the converter enters auto-restart
mode.
In order to bypass the noise after the turn-off of the power MOSFET, V
ZCD
voltage is
sampled inside a short window after the time t
STROBE
, see Table 7 and Figure 38. The
sampled signal, if higher than V
OVP,
triggers the internal OVP digital signal and increments
the internal counter. The same counter is reset every time the signal OVP is not triggered in
one oscillator cycle.
Referring to Figure 37, the resistor divider ratio k
OVP
is given by below equations:
R
LIM
Max V
ZCD1
I
ZCD1
V
in_min
N
AUX
------------------ V
ZCD1
+
R
FF
------------------------------------------–
----------------------------------------------------------------V
ZCD2
I
ZCD2
V
in_Max
N
AUX
--------------------V
ZCD2
+
R
FF
--------------------------------------------–
-----------------------------------------------------------------,
=
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Operation description VIPer35
30/44 DocID026980 Rev 4
Equation 5
Equation 6
where:
•V
OVP
is the OVP threshold (see Table 7)
•V
OUTOVP
is the converter output voltage value to activate the OVP (set by design)
•N
AUX
is the auxiliary winding turn
•N
SEC
is the secondary winding turn
•V
DSEC
is the secondary diode forward voltage
•V
DAUX
is the auxiliary diode forward voltage
•R
OVP
and R
LIM
make the output voltage divider
By fixing R
LIM,
according to the desired I
Dlim
, R
OVP
can be calculated as follows:
Equation 7
The resistor values let the current sourced and sunk by the ZCD pin be within the rated
capability of t he intern al clamp.
K
OVP
V
OVP
N
AUX
N
SEC
-------------- V
OUTOVP
V
DSEC
+()V
DAUX
–⋅
---------------------------------------------------------------------------------------------------=
K
OVP
R
LIM
R
LIM
R
OVP
+
----------------------------------=
R
OVP
R
LIM
1K
OVP
–
K
OVP
------------------------×=
DocID026980 Rev 4 31/44
VIPer35 Operatio n descrip tio n
44
Figure 38. Timing diagram: OVP
8.12 ZCD pin summary
With reference to Figure 37, the circuitry connected to the ZCD pin enables the following
functions:
1. Current limit set-point (I
DLIM
)
2. Line feed-forward compensation (FF)
3. Output overvoltage protection (OVP)
4. Zero-current detection for QR operation
Chosen R
LIM
, R
FF
and R
OVP
as described in the previous sections, these functions are
automatically defined.
Table 7 refers to Figure 37 and lists the external resistance combinations needed to activate
one or more functions associated to ZCD pin.
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Operation description VIPer35
32/44 DocID026980 Rev 4
8.13 Feedback an d overload protection (OLP)
The feedback pin (FB) controls the PWM operation, enters the burst mode and manages the
delayed overload protection.
V
FBbm
and V
FBlin
thresholds (Table 7) are respectively low and high limit of PWM
operations, where the drain current is sensed by the integrated resistor, R
SENSE,
and
applied to the comparator PWM. The PWM logic turns off the power MOSFET as soon as
the sensed voltage is equal to the voltage applied to FB pin and through the integrated
resistor network (see Figure 2 and Figure 23).
IC block diagram (Figure 2) shows in parallel with the PWM comparator how OCP
comparator limits the drain current to I
Dlim
value, as per Table 7.
In case of higher load, the voltage V
FB
increases, when it reaches V
FBlin
thr eshol d, the d rain
current is limited to I
Dlim
by OCP comparator and the internal current starts the charge of
C
FB
capacitor. As soon as the voltage V
FB
reaches the threshold V
FBolp,
see Figure 41, the
protection turns off the IC. The auto-restart mode is active using the low value of the current
I
DDch
, see Table 7.
The time, from the high load detection, V
FB
= V
FBlin
, to the overload turn-off, V
FB
= V
FBolp
,
depends on the value of C
FB
capacitor and on the internal charge current, I
FB
. OLP delay
time can be calculated as follows:
Equation 8
The c ur r en t , I
FB
, is 3 A as minimum value. Components, connected to FB pin, belong to the
compensation loop, so they have to be selected taking into account the proper delay and
loop stability. Figure 39 and Figure 40 show two different feedback networks.
Table 10. ZCD pin configurations
I
Dlim
OVP FF R
Lim
R
OVP
R
FF
D
OVP
Equation 4 Equation 7 with
V
OUTOVP
2 V
OUT
Yes
22 kEquation 7 Yes
22 kEquation 7 with
V
OUTOVP
2 V
OUT
Equation 3 Yes
Equation 4
with R
FF
=
Equation 7 Yes
22 kEquation 7 Equation 3 Yes
Equation 4 Equation 7 with
V
OUTOVP
2 V
OUT
Equation 3 Yes
Equation 4 Equation 7 Equation 3 Yes
T
OLP_delay
C
FB
V
FBolp
V
FBlin
–
I
FB
----------------------------------------×=
DocID026980 Rev 4 33/44
VIPer35 Operatio n descrip tio n
44
In Figure 39 C
FB
capacitor , connected to FB pin, is used as part of the circuit to compensate
the feedback loop but it is also an element to delay OLP shutdown owing to the time needed
to charge the ca pacitor (see Equati on 8 ).
After the start-up time, t
SU
, during which the feedback voltage is fixed at V
FBlin
, the output
capacitor could not be at its nominal value and the controller detects this situation as an
overload condition. In this case, OLP delay avoids the wrong device shutdown during the
start-up.
Owing to the above considerations, OLP delay time must last to bypass the initial output
voltage transient and check the overload condition only when the output voltage is in
steady-state. The output transient time depends on the value of the output capacitor and on
the load.
When C
FB
capacitor value is too low and cannot ensure the OLP delay, an alternative
compensation network can be used as showed in Figure 40. Two poles (f
PFB
, f
PFB1
) and
one zero (f
ZFB
) are introduced by C
FB
and C
FB1
capacitors and R
FB1
resistor.
The capaci tor C
FB
introduces a pole (f
PFB
) at higher frequency than f
ZB
and f
PFB1
. This pole
compensates zero frequency due to ESR (equivalent series resistor) of the output
capacitance of the flyback converter.
By taking into account the scheme in Figure 40, these poles and zero frequency are
repor ted as follows:
Equation 9
Equation 10
Equation 11
R
FB(DYN)
is the dynamic resistance seen by FB pin and reported in Table 7.
C
FB1
capacitor fixes the OLP delay and usually it is much higher than C
FB.
Equation 8
calculates the OLP delay time but C
FB1
has to be considered. Using the alternative
compensation network, the designer can satisfy the loop stability and OLP delay time.
f
ZFB
1
2πC
FB
R
FB
⋅⋅ ⋅
-----------------------------------------=
f
PFB
R
FB DYN()
R
FB1
+
2πC
FB
R
FB DYN()
R
FB1
⋅()⋅⋅ ⋅
-------------------------------------------------------------------------------=
f
PFB1
1
2πC
FB1
R
FB1
R
FB DYN()
+()⋅⋅ ⋅
------------------------------------------------------------------------------------=
Operation description VIPer35
34/44 DocID026980 Rev 4
Figure 39. FB pin configuration (minimal BOM)
Figure 40. FB pin configuration
From senseFET
4.8 V
BURST
PWM
Cfb
To PWM logic
Burst mode
references
+
-
PWM
+
-
OLP comparator
To disable logic
Burst mode
logic
control
GIPG2801150948LM
4.8 V
From senseFET
PWM
CONTROL
+
-
PWM
BURST
To disable logic
+
-
OLP comparator
To PWM logic
Burst mode
logic
Cfb1
Rfb1
Cfb
Burst mode
references
GIPG2801150952LM
DocID026980 Rev 4 35/44
VIPer35 Operatio n descrip tio n
44
Figure 41. Timing diagram: ove rload protection
8.14 Burst mode operation at no-load or very light load
When the load decreases, the feedback loop lowers the feedback pin voltage. If it falls down
the burst mode threshold, V
FBBm
, the power MOSFET doesn’t switch on. After the MOSFET
stops, the feedback pin voltage increases and by exceeding the level, V
FBbm
+ V
FBbmhys
,
the power MOSFET starts switching again. The burst mode thresholds are reported in
Table 7 and Figure 42 shows this behavior. System alternates period of time where power
MOSFET switches to period of time where power MOSFET doesn’t switch; this device
working mode is the burst mode. The power delivered to output during switching periods
exceeds the load power demands; the excess of power is balanced by the period where no
power is processed. The advantage of burst mode operation is an average switching
frequency much lower than the normal operation working frequency, up to some hundred of
hertz, minimizing all frequency-related losses. During the burst mode the drain current peak
is clamped to the level, I
D_BM
, (see Table 7).
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Operation description VIPer35
36/44 DocID026980 Rev 4
Figure 42. Burst mode timing: light load management
8.15 Brown-out
Brown-out protection is a not-latched shutdown function active when a condition of mains
undervoltage is detected. The brown-out comparator is internally referenced to V
BRth
threshold (see Figure 10) and disables the PWM if the voltage applied to BR pin is below
this internal reference. Under this condition the power MOSFET turns off.
Until the brown-out conditi on is present, the V
DD
voltage continuously oscillates between
the V
DDon
and the UVLO thresholds, as shown in the timing diagram of Figure 43. A voltage
hysteresis improves the noise immunity.
The switching operation restarts as the voltage on the pin is above the reference plus the
voltage hysteresis. The brown-out comparator is provided with a current hysteresis, I
BRhyst.
The designer has to set the rectified input voltage above which the power MOSFET starts
switching after brown-out event, V
INon
, and below which the power MOSFET switches off,
V
INoff.
Thanks to the I
BRhyst
, see Table 7, these two thresholds can be set separately.
When V
INon
and V
INoff
levels are fixed, with reference to Figure 43, the following
relationships can be established to calculate R
H
and R
L
resistors:
Equation 12
Equation 13
time
time
time
V
COMP
V
FBbm
V
FBbm
+V
FBbmhys
I
DD1
I
DD0
I
DD
I
DRAIN
I
D_BM
Burst mode
GIPG2801151121LM
R
L
V
BRhyst
I
BRhyst
---------------------– V
INon
V
INoff
V
BRhyst
––
V
INon
V
BRth
–
--------------------------------------------------------------- V
BRth
I
BRhyst
------------------⋅+=
R
H
V
INon
V
INoff
V
BRhyst
–– I
BRhyst
--------------------------------------------------------------- R
L
R
L
V
BRhyst
I
BRhyst
---------------------+
----------------------------------⋅=
DocID026980 Rev 4 37/44
VIPer35 Operatio n descrip tio n
44
Figure 43. Brown
-
out: external setting and timing diagra m
V
INon
must be less than the peak voltage at minimum mains and V
INoff
voltage has to be
less than the minimum voltage on the input bulk capacitor at minimum mains and maximum
load.
BR pin is a high impedance input connected to high value resistors, thus it is ready to pick
up noise, which might alter the V
INoff
threshold when the converter operates or causes the
undesired switch-off of the device during ESD tests.
The pin ca be bypassed to ground with a small film capacitor (1-10 nF) to prevent any
malfunctioning.
If the brown-out function is not used, BR pin has to be connected to GND, ensuring that the
voltage is lower than the minimum V
DIS
threshold (50 mV, see Table 7). In order to enable
the brown-out function, BR pin voltage has to be higher than the maximum V
DIS
threshold
(150 mV, see Table 7).
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Package information VIPer35
38/44 DocID026980 Rev 4
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
9.1 SO16N package information
Figure 44. SO16N package outline
0016020_F
DocID026980 Rev 4 39/44
VIPer35 Package information
44
Table 11. SO16N mechanical data
Dim. mm
Min. Typ. Max.
A1.75
A1 0.10 0.25
A2 1.25
b0.31 0.51
c0.17 0.25
D 9.80 9.90 10.00
E5.806.006.20
E1 3.80 3.90 4.00
e1.27
h0.25 0.50
L0.40 1.27
k0 8°
ccc 0.10
Package information VIPer35
40/44 DocID026980 Rev 4
9.2 SDIP10 package information
Figure 45. SDIP10 package outline
DocID026980 Rev 4 41/44
VIPer35 Package information
44
Table 12. SDIP10 mechanical data
Dim. mm
Min. Typ. Max.
A 5.33
A1 0.38
A2 2.92 4.95
b 0.36 0.56
b2 0.51 1.15
c 0.2 0.36
D 9.02 10.16
E 7.62 8.26
E1 6.1 7.11
E2 7.62
E3 10.92
e 1.77
L 2.92 3.81
Ordering information VIPer35
42/44 DocID026980 Rev 4
10 Ordering information
Table 13. Order codes
Order code F
Osclim
R
DS(on)
Peak drain
current Package
VIPER35LD
136 kHz
4.5 1 A
SO16N
(tube)
VIPE35LDTR SO16N
(tape and reel)
VIPER35LE SDIP10
(tube)
VIPER35HD
225 kH z
SO16N
(tube)
VIPER35HDTR SO16N
(tape and reel)
VIPER35HE SDIP10
(tube)
DocID026980 Rev 4 43/44
VIPer35 Revision history
44
11 Revision history
Table 14. Document revision history
Date Revision Changes
23-Feb-2015 1 First r elease.
19-Mar-2015 2 Updated title in cover page.
Minor text chan ges .
08-Jul-2015 3 Document status prom oted from preliminary data to production data.
Updated Section 4: Electrical ratings.
Minor text chan ges .
10-Feb-2016 4
Added SDIP10 package.
Updated Figure 1 title in cover page from “Internal schematic
diagram” to “Basic application schematic”.
Updated Section 3: Pin settings, Table 2: Pin description, Table 4:
Thermal data and Section 10: Ordering information.
Added Sectio n 9.2: SDIP10 package information.
Minor text chan ges .
VIPer35
44/44 DocID026980 Rev 4
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