LTM4608AEV#PBF - LINEAR TECHNOLOGY

LTM4608A

4608afd

Typical applicaTion

FeaTures

applicaTions

DescripTion

Low VIN, 8A DC/DC µModule

Regulator with Tracking, Margining,

and Frequency Synchronization

The LTM

4608A is a complete 8A switch mode DC/DC

power supply with ±1.75% total output voltage error. In-

cluded in the package are the switching controller, power

FETs, inductor and all support components. Operating

over an input voltage range of 2.7V to 5.5V, the LTM4608A

supports an output voltage range of 0.6V to 5V, set by a

single external resistor. This high efficiency design delivers

up to 8A continuous current (10A peak). Only bulk input

and output capacitors are needed to complete the design.

The low profile package (2.82mm) enables utilization

of unused space on the back side of PC boards for high

density point-of-load regulation. The 0.630mm LGA pads

with 1.27mm pitch simplify PCB layout by providing stan-

dard trace routing and via placement. The high switching

frequency and current mode architecture enable a very

fast transient response to line and load changes without

sacrificing stability. The device supports frequency syn-

chronization, programmable multiphase and/or spread

spectrum operation, output voltage tracking for supply

rail sequencing and voltage margining.

Fault protection features include overvoltage protection,

overcurrent protection and thermal shutdown. The power

module is offered in a compact and thermally enhanced

9mm × 15mm × 2.82mm surface mount LGA package.

The LTM4608A is RoHS compliant with Pb-free finish.

2.7V to 5.5V Input to 1.8V Output DC/DC µModule

Regulator

n Complete Standalone Power Supply

n ±1.75% Total DC Output Error (–55°C to 125°C)

n 2.7V to 5.5V Input Voltage Range

n 8A DC, 10A Peak Output Current

n 0.6V Up to 5V Output

n Output Voltage Tracking and Margining

n Power Good Tracks Margining

n Multiphase Operation

n Parallel Current Sharing

n Onboard Frequency Synchronization

n Spread Spectrum Frequency Modulation

n Overcurrent/Thermal Shutdown Protection

n Current Mode Control/Fast Transient Response

n Selectable Burst Mode

Operation

n Up to 95% Efficiency

n Output Overvoltage Protection

n Small, Low Profile 9mm × 15mm × 2.82mm

LGA Package (0.630mm Pads)

n Telecom, Networking and Industrial Equipment

n Storage Systems

n Point of Load Regulation

Efficiency vs Load Current

L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode, µModule and PolyPhase

are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation.

All other trademarks are the property of their respective owners. Protected by U.S. Patents

including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.

LOAD CURRENT (A)

EFFICIENCY (%)

100

2 4 6 8

4608A TA01b

VOUT = 1.8V

VIN = 5V

VIN = 3.3V

VIN

SVIN

RUN

PLLLPF

TRACK

VOUT

ITH

ITHM

PGOOD

MGN

CLKOUT GND

CLKIN

4.87k

4608A TA01a

100µF10µF

PGOOD

VOUT

1.8V

VIN

2.7V TO 5.5V

LTM4608A

SGND

LTM4608A

4608afd

pin conFiguraTion

absoluTe MaxiMuM raTings

VIN, SVIN ...................................................... –0.3V to 6V

CLKOUT ....................................................... –0.3V to 2V

PGOOD, PLLLPF, CLKIN, PHMODE, MODE . –0.3V to VIN

ITH, ITHM, RUN, FB, TRACK,MGN, BSEL ...... –0.3V to VIN

VOUT, SW ...................................... –0.3V to (VIN + 0.3V)

Internal Operating Temperature Range

(Note 2) .................................................. –55°C to 125°C

Storage Temperature Range .................. –55°C to 125°C

(Note 1)

orDer inForMaTion

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN(DC) Input DC Voltage l2.7 5.5 V

VOUT(DC) Output Voltage, Total Variation

with Line and Load

CIN = 10µF × 1, COUT = 100µF Ceramic,

100µF POSCAP, RFB = 6.65k, MODE = 0V

VIN = 2.7V to 5.5V, IOUT = IOUT(DC)MIN to

IOUT(DC)MAX (Note 3)

1.472

1.464

1.49

1.508

1.516

Input Specifications

VIN(UVLO) Undervoltage Lockout Threshold SVIN Rising

SVIN Falling

2.05

1.85

2.2

2.0

2.35

2.15

The l denotes the specifications which apply over the specified internal

operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise noted. See Figure 1.

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE (NOTE 2)

LTM4608AEV#PBF LTM4608AEV#PBF LTM4608AV 68-Lead (15mm × 9mm × 2.82mm) LGA –40°C to 125°C

LTM4608AIV#PBF LTM4608AIV#PBF LTM4608AV 68-Lead (15mm × 9mm × 2.82mm) LGA –40°C to 125°C

LTM4608AMPV#PBF LTM4608AMPV#PBF LTM4608AMPV 68-Lead (15mm × 9mm × 2.82mm) LGA –55°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

LGA PACKAGE

68-LEAD (15mm × 9mm × 2.82mm)

GND

RUN

SGND

B C D E F G

GND VOUT

VIN

TOP VIEW

CLKOUT

PLLLPF

CLKIN

SVIN

PHMODE

MODE

BSEL

MGN

PGOOD

ITHM

TRACK

ITH

TJMAX = 125°C, θJA = 25°C/W, θJCbottom = 7°C/W, θJCtop = 50°C/W, WEIGHT = 1.0g

LTM4608A

4608afd

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal

operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise noted. See Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IQ(VIN) Input Supply Bias Current VIN = 3.3V, No Switching, MODE = VIN

VIN = 3.3V, No Switching, MODE = 0V

VIN = 3.3V, VOUT = 1.5V, Switching Continuous

400

1.15

µA

VIN = 5V, No Switching, MODE = VIN

VIN = 5V, No Switching, MODE = 0V

VIN = 5V, VOUT = 1.5V, Switching Continuous

450

1.3

µA

Shutdown, RUN = 0, VIN = 5V 1 µA

IS(VIN) Input Supply Current VIN = 3.3V, VOUT = 1.5V, IOUT = 8A

VIN = 5V, VOUT = 1.5V, IOUT = 8A

4.5

2.93

Output Specifications

IOUT(DC) Output Continuous Current Range

(Note 3)

VOUT = 1.5V

VIN = 3.3V, 5.5V

VIN = 2.7V

∆VOUT(LINE)

VOUT

Line Regulation Accuracy VOUT = 1.5V, VIN from 2.7V to 5.5V, IOUT = 0A l0.1 0.25 %/V

∆VOUT(LOAD)

VOUT

Load Regulation Accuracy VOUT = 1.5V (Note 3)

VIN = 3.3V, 5.5V, ILOAD = 0A to 8A

VIN = 2.7V, ILOAD = 0A to 5A

0.3

0.75

VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF X5R Ceramic, VIN = 5V,

VOUT = 1.5V

mVP-P

fSSwitching Frequency IOUT = 8A, VIN = 5V, VOUT = 1.5V 1.25 1.5 1.75 MHz

fSYNC SYNC Capture Range 0.75 2.25 MHz

∆VOUT(START) Turn-On Overshoot COUT = 100µF, VOUT = 1.5V, IOUT = 0A

VIN = 3.3V

VIN = 5V

tSTART Turn-On Time COUT = 100µF, VOUT = 1.5V, VIN = 5V,

IOUT = 1A Resistive Load, Track = VIN,

100 µs

∆VOUT(LS) Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load,

COUT = 100µF Ceramic, 100µF POSCAP,

VIN = 5V, VOUT = 1.5V

15 mV

tSETTLE Settling Time for Dynamic Load

Step

Load: 0% to 50% to 0% of Full Load, VIN = 5V,

VOUT = 1.5V, COUT = 100µF

10 µs

IOUT(PK) Output Current Limit COUT = 100µF

VIN = 2.7V, VOUT = 1.5V

VIN = 3.3V, VOUT = 1.5V

VIN = 5V, VOUT = 1.5V

Control Section

VFB Voltage at FB Pin IOUT = 0A, VOUT = 1.5V, VIN = 2.7V to 5.5V

0.590

0.587

0.596

0.602

0.606

SS Delay Internal Soft-Start Delay 90 µs

IFB 0.2 µA

VRUN RUN Pin On/Off Threshold RUN Rising

RUN Falling

1.4

1.3

1.55

1.4

1.7

1.5

LTM4608A

4608afd

elecTrical characTerisTics

The l denotes the specifications which apply over the specified internal

operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 5V unless otherwise noted. See Figure 1.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

TRACK Tracking Threshold (Rising)

Tracking Threshold (Falling)

Tracking Disable Threshold

RUN = VIN

RUN = 0V

0.57

0.18

VIN – 0.5

RFBHI Resistor Between VOUT and FB

Pins

9.95 10 10.05 kΩ

∆VPGOOD PGOOD Range ±10 %

%Margining Output Voltage Margining

Percentage

MGN = VIN, BSEL = 0V

MGN = VIN, BSEL = VIN

MGN = VIN, BSEL = Float

MGN = 0V, BSEL = 0V

MGN = 0V, BSEL = VIN

MGN = 0V, BSEL = Float

–4

–9

–14

–5

–10

–15

–6

–11

–16

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4608A is tested under pulsed load conditions such that

TJ ≈ TA. The LTM4608AE is guaranteed to meet specifications from

0°C to 125°C internal temperature. Specifications over the –40°C to

125°C internal operating temperature range are assured by design,

characterization and correlation with statistical process controls.

The LTM4608AI is guaranteed over the –40°C to 125°C internal operating

temperature range and the LTM4608AMP is tested and guaranteed over

the full –55°C to 125°C internal operating temperature range. Note that

the maximum ambient temperature consistent with these specifications

is determined by specific operating conditions in conjunction with board

layout, the rated package thermal impedance and other environmental

factors.

Note 3: See output current derating curves for different VIN, VOUT and TA.

LTM4608A

4608afd

VIN (V)

VOUT (V)

1.5

2.0

2.5

3 5

4608A G06

1.0

0.5

3.0

3.5

4.0

IOUT = 6A

VOUT = 1.2V

VOUT = 1.5V

VOUT = 1.8V

VOUT = 2.5V

VOUT = 3.3V

VIN (V)

VOUT (V)

1.5

2.0

2.5

4608A G05

1.0

0.5

3.0

3.5

4.0

IOUT = 8A

VOUT = 1.2V

VOUT = 1.5V

VOUT = 1.8V

VOUT = 2.5V

VOUT = 3.3V

Typical perForMance characTerisTics

Efficiency vs Load Current

Burst Mode Efficiency with

5V Input VIN to VOUT Step-Down Ratio

Supply Current vs VIN Load Transient Response Load Transient Response

Efficiency vs Load Current Efficiency vs Load Current

LOAD CURRENT

EFFICIENCY (%)

100

2 4 6 8

4608A G01

5VIN 1.2VOUT

5VIN 1.5VOUT

5VIN 1.8VOUT

5VIN 2.5VOUT

5VIN 3.3VOUT

CONTINUOUS MODE

LOAD CURRENT

EFFICIENCY (%)

100

2468

4608A G02

3.3VIN 1.2VOUT

3.3VIN 1.5VOUT

3.3VIN 1.8VOUT

3.3VIN 2.5VOUT

CONTINUOUS MODE

LOAD CURRENT (A)

EFFICIENCY (%)

100

245

4608A G03

1367

2.7VIN 1.0VOUT

2.7VIN 1.5VOUT

2.7VIN 1.8VOUT

CONTINUOUS MODE

VIN to VOUT Step-Down Ratio

LOAD CURRENT (A)

EFFICIENCY (%)

100

0.2 0.4 0.6 0.8

4608A G04

1.11.00.10 0.3 0.5 0.7 0.9

VOUT = 1.5V

VOUT = 2.5V

VOUT = 3.3V

INPUT VOLTAGE (V)

2.5

SUPPLY CURRENT (mA)

4.5

1.6

1.4

1.2

0.8

0.6

0.4

0.2

4608A G07

3.53 5

45.5

VO = 1.2V PULSE-SKIPPING MODE

VO = 1.2V BURST MODE

ILOAD

1A/DIV

VIN

2V/DIV

VOUT

20mV/DIV

AC COUPLED

20µs/DIVVIN = 5V

VOUT = 3.3V, RFB = 2.21k

2A/µs STEP

COUT = 100µF X5R

C1 = 100pF, C3 = 22pF FROM FIGURE 18

4608A G08 20µs/DIVVIN = 5V

VOUT = 2.5V, RFB = 3.09k

2.5A/µs STEP

COUT = 100µF X5R

C1 = 120pF, C3 = 47pF FROM FIGURE 18

4608A G09

ILOAD

2A/DIV

VOUT

20mV/DIV

AC COUPLED

LTM4608A

4608afd

TEMPERATURE (°C)

–55

VFB (mV)

592

594

596

35 95

4608A G14

590 –25 5 65

598

600

602

125

VIN = 5.5V

VIN = 3.3V

VIN = 2.7V

Load Transient Response

Start-Up VFB vs Temperature Load Regulation vs Current

2.5V Output Current

Short-Circuit Protection

(2.5V Short, No Load)

Load Transient Response Load Transient Response

VOUT

0.5V/DIV

VIN

2V/DIV

50µs/DIVVIN = 5V

VOUT = 1.5V

COUT = 100µF NO LOAD AND 8A LOAD

(DEFAULT 100µs SOFT-START)

4608A G13

LOAD CURRENT (A)

–0.5

LOAD REGULATION (%)

–0.4

–0.2

–0.3

–0.6

2 4

–0.1

6 8

4608A G15

FC MODE

VIN = 3.3V

VOUT = 1.5V

Short-Circuit Protection

(2.5V Short, 4A Load)

OUTPUT CURRENT (A)

OUTPUT VOLTAGE (V)

0.5

1.0

1.5

2.0

2.5

3.0

5 10 15 20

4608A G16

2V/DIV

5A/DIV

50µs/DIV 4608A G17

VOUT

VIN

IOUT

VIN = 5V

VOUT = 2.5V

5V/DIV

5A/DIV

50µs/DIV 4608A G18

VOUT

VIN

IOUT LOAD

VIN = 5V

VOUT = 2.5V

Typical perForMance characTerisTics

20µs/DIVVIN = 5V

VOUT = 1.8V, RFB = 4.87k

2.5A/µs STEP

COUT = 100µF X5R

C1 = NONE, C3 = NONE FROM FIGURE 18

4608A G10

ILOAD

2A/DIV

VOUT

20mV/DIV

AC COUPLED

20µs/DIVVIN = 5V

VOUT = 1.5V, RFB = 6.65k

2.5A/µs STEP

COUT = 100µF X5R

C1 = NONE, C3 = NONE FROM FIGURE 18

4608A G11

ILOAD

2A/DIV

VOUT

20mV/DIV

AC COUPLED

20µs/DIVVIN = 5V

VOUT = 1.2V, RFB = 10k

2.5A/µs STEP

COUT = 2 × 100µF

C1 = 100pF, C3 = NONE FROM FIGURE 18

4608A G12

ILOAD

2A/DIV

VOUT

20mV/DIV

AC COUPLED

LTM4608A

4608afd

PLLLPF (E3): Phase Locked Loop Lowpass Filter. An in-

ternal lowpass filter is tied to this pin. In spread spectrum

mode, placing a capacitor here to SGND controls the slew

rate from one frequency to the next. Alternatively, floating

this pin allows normal running frequency at 1.5MHz, tying

this pin to SVIN forces the part to run at 1.33 times its

normal frequency (2MHz), tying it to ground forces the

frequency to run at 0.67 times its normal frequency (1MHz).

PHMODE (B4): Phase Selector Input. This pin determines

the phase relationship between the internal oscillator and

CLKOUT. Tie it high for 2-phase operation, tie it low for

3-phase operation, and float or tie it to VIN/2 for 4-phase

operation.

MGN (B8): Margining Pin. Increases or decreases the

output voltage by the amount specified by the BSEL pin.

To disable margining, tie the MGN pin to a voltage divider

with 50k resistors from VIN to ground. See the Applications

Information section and Figure 20.

BSEL (B7): Margining Bit Select Pin. Tying BSEL low se-

lects ±5%, tying it high selects ±10%. Floating it or tying

it to VIN/2 selects ±15%.

TRACK (E5): Output Voltage Tracking Pin. Voltage track-

ing is enabled when the TRACK voltage is below 0.57V.

If tracking is not desired, then connect the TRACK pin to

SVIN. If TRACK is not tied to SVIN, then the TRACK pin’s

voltage needs to be below 0.18V before the chip shuts

down even though RUN is already low. Do not float this

pin. A resistor divider and capacitor can be applied to the

TRACK pin to increase the soft-start time of the regulator.

See the Applications Information section. Can tie together

for parallel operation and tracking. Load current needs to

be present during track down.

pin FuncTions

VIN (C1, C8, C9, D1, D3-D5, D7-D9 and E8): Power Input

Pins. Apply input voltage between these pins and GND

pins. Recommend placing input decoupling capacitance

directly between VIN pins and GND pins.

VOUT (C10-C11, D10-D11, E9-E11, F9-F11, G9-G11):

Power Output Pins. Apply output load between these pins

and GND pins. Recommend placing output decoupling

capacitance directly between these pins and GND pins.

See Table 1.

GND (A1-A11, B1, B9-B11, F3, F7-F8, G1-G8): Power

Ground Pins for Both Input and Output Returns.

SVIN (F4): Signal Input Voltage. This pin is internally con-

nected to VIN through a lowpass filter.

SGND (E1): Signal Ground Pin. Return ground path for all

analog and low power circuitry. Tie a single connection to

GND in the application.

MODE (B5): Mode Select Input. Tying this pin high enables

Burst Mode operation. Tying this pin low enables forced

continuous operation. Floating this pin or tying it to VIN/2

enables pulse-skipping operation.

CLKIN (B3): External Synchronization Input to Phase

Detector. This pin is internally terminated to SGND with a

50k resistor. The phase locked loop will force the internal

top power PMOS turn on to be synchronized with the

rising edge of the CLKIN signal. Connect this pin to SVIN

to enable spread spectrum modulation. During external

synchronization, make sure the PLLLPF pin is not tied to

VIN or GND.

LTM4608A

4608afd

FB (E7): The Negative Input of the Error Amplifier. Internally,

this pin is connected to VOUT with a 10k precision resistor.

Different output voltages can be programmed with an ad-

ditional resistor between FB and GND pins. In PolyPhase

operation, tie FB pins together for parallel operation. See

the Applications Information section for details.

ITH (F6): Current Control Threshold and Error Amplifier

Compensation Point. The current comparator threshold

increases with this control voltage. Tie together in parallel

operation.

ITHM (F5): Negative Input to the Internal ITH Differential

Amplifier. Tie this pin to SGND for single phase operation.

For PolyPhase operation, tie the master’s ITHM to SGND

while connecting all of the ITHM pins together.

PGOOD (C7): Output Voltage Power Good Indicator.

Open-drain logic output that is pulled to ground when the

output voltage is not within ±10% of the regulation point.

Disabled during margining.

RUN (F1): Run Control Pin. A voltage above 1.5V will turn

on the module.

SW (C3-C5): Switching Node of the Circuit is Used for

Testing Purposes. This can be connected to an electri-

cally open circuit copper pad on the board for improved

thermal performance.

CLKOUT (F2): Output Clock Signal for PolyPhase Opera-

tion. The phase of CLKOUT is determined by the state of

the PHMODE pin.

pin FuncTions

LTM4608A

4608afd

siMpliFieD block DiagraM

INTERNAL

FILTER

POWER

CONTROL

INTERNAL

COMP

INTERNAL

FILTER

SVIN

TRACK

MGN

BSEL

PGOOD

MODE

RUN

CLKIN

CLKOUT

PHMODE

PLLLPF

SGND

ITH

ITHM

22µF COUT

10µF 10µF 10µF CIN

VIN

2.7 TO 5.5V

VOUT

1.5V

VOUT

VIN

GND

22pF

10k

RFB

6.65k

4608A BD

0.22µH

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

CIN External Input Capacitor Requirement

(VIN = 2.7V to 5.5V, VOUT = 1.5V)

IOUT = 8A 10 µF

COUT External Output Capacitor Requirement

(VIN = 2.7V to 5.5V, VOUT = 1.5V)

IOUT = 8A 100 µF

Table 1. Decoupling Requirements. TA = 25°C, Block Diagram Configuration

Figure 1. Simplified LTM4608A Block Diagram

operaTion

The LTM4608A is a standalone nonisolated switch mode

DC/DC power supply. It can deliver up to 8A of DC output

current with few external input and output capacitors.

This module provides precisely regulated output voltage

programmable via one external resistor from 0.6V DC to

5.0V DC over a 2.7V to 5.5V input voltage. The typical

application schematic is shown in Figure 18.

The LTM4608A has an integrated constant frequency cur-

rent mode regulator and built-in power MOSFET devices

with fast switching speed. The typical switching frequency

is 1.5MHz. For switching noise sensitive applications, it

can be externally synchronized from 0.75MHz to 2.25MHz.

Even spread spectrum switching can be implemented in

the design to reduce noise.

LTM4608A

4608afd

operaTion

With current mode control and internal feedback loop

compensation, the LTM4608A module has sufficient

stability margins and good transient performance with

a wide range of output capacitors, even with all ceramic

output capacitors.

Current mode control provides cycle-by-cycle fast current

limit and thermal shutdown in an overcurrent condition.

Internal overvoltage and undervoltage comparators pull

the open-drain PGOOD output low if the output feedback

voltage exits a ±10% window around the regulation point.

Pulling the RUN pin below 1.3V forces the controller into

its shutdown state, by turning off both M1 and M2 at low

load current. The TRACK pin is used for programming the

output voltage ramp and voltage tracking during start-up.

See Applications Information.

The LTM4608A is internally compensated to be stable

over all operating conditions. Table 3 provides a guideline

for input and output capacitances for several operating

The typical LTM4608A application circuit is shown in

Figure 18. External component selection is primarily

determined by the maximum load current and output

voltage. Refer to Table 3 for specific external capacitor

requirements for a particular application.

VIN to VOUT Step-Down Ratios

There are restrictions in the maximum VIN to VOUT step-

down ratio that can be achieved for a given input voltage.

The LTM4608A is 100% duty cycle, but the VIN to VOUT

minimum dropout is a function of its load current. Please

refer to the curves in the Typical Performance Charac-

teristics section of this data sheet for more information.

Output Voltage Programming

The PWM controller has an internal 0.596V reference

voltage. As shown in the Block Diagram, a 10k 0.5%

internal feedback resistor connects VOUT and FB pins

together. The output voltage will default to 0.596V with

conditions. The Linear Technology µModule Power Design

Tool is provided for transient and stability analysis. The

FB pin is used to program the output voltage with a single

external resistor to ground.

Multiphase operation can be easily employed with the

synchronization and phase mode controls. Up to 12 phases

can be cascaded to run simultaneously with respect to

each other by programming the PHMODE pin to different

levels. The LTM4608A has clock in and clock out for poly

phasing multiple devices or frequency synchronization.

High efficiency at light loads can be accomplished with

selectable Burst Mode operation using the MODE pin. These

light load features will accommodate battery operation.

Efficiency graphs are provided for light load operation in

the Typical Performance Characteristics.

Output voltage margining is supported, and can be pro-

gramed from ±5% to ±15% using the MGN and BSEL pins.

The PGOOD pin is disabled during margining

applicaTions inForMaTion

no feedback resistor. Adding a resistor RFB from FB pin

to GND programs the output voltage:

VOUT =0.596V •10k +RFB

RFB

Table 2. RFB Resistor vs Output Voltage

VOUT 0.596V 1.2V 1.5V 1.8V 2.5V 3.3V

RFB Open 10k 6.65k 4.87k 3.09k 2.21k

Input Capacitors

The LTM4608A module should be connected to a low AC

impedance DC source. Three 10µF ceramic capacitors

are included inside the module. Additional input capaci-

tors are only needed if a large load step is required up to

the 4A level. A 47µF to 100µF surface mount aluminum

electrolytic bulk capacitor can be used for more input bulk

capacitance. This bulk input capacitor is only needed if

the input source impedance is compromised by long in-

ductive leads, traces or not enough source capacitance.

LTM4608A

4608afd

applicaTions inForMaTion

If low impedance power planes are used, then this 47µF

capacitor is not needed.

For a buck converter, the switching duty-cycle can be

estimated as:

OUT

VIN

Without considering the inductor current ripple, the RMS

current of the input capacitor can be estimated as:

ICIN(RMS) =IOUT(MAX)

η%•D•1– D

( )

In the above equation, η% is the estimated efficiency of

the power module. The bulk capacitor can be a switcher-

rated electrolytic aluminum capacitor, polymer capacitor

for bulk input capacitance due to high inductance traces

or leads. If a low inductance plane is used to power the

device, then only one 10µF ceramic is required. The three

internal 10µF ceramics are typically rated for 2A of RMS

ripple current, so the ripple current at the worse case for

8A maximum current is 4A or less.

Output Capacitors

The LTM4608A is designed for low output voltage ripple

noise. The bulk output capacitors defined as COUT are

chosen with low enough effective series resistance (ESR)

to meet the output voltage ripple and transient require-

ments. COUT can be a low ESR tantalum capacitor, a low

ESR polymer capacitor or ceramic capacitor. The typical

output capacitance range is from 47µF to 220µF. Additional

output filtering may be required by the system designer,

if further reduction of output ripple or dynamic transient

spikes is desired. Table 3 shows a matrix of different output

voltages and output capacitors to minimize the voltage

droop and overshoot during a 3A/µs transient. The table

optimizes total equivalent ESR and total bulk capacitance

to optimize the transient performance. Stability criteria are

considered in the Table 3 matrix, and the Linear Technology

LTpowerCAD™ Design Tool is available for stability analysis.

Multiphase operation will reduce effective output ripple as

a function of the number of phases. Application Note 77

discusses this noise reduction versus output ripple cur-

rent cancellation, but the output capacitance will be more

a function of stability and transient response. The Linear

Technology LTpowerCAD Design Tool will calculate the

output ripple reduction as the number phases implemented

increases by N times.

Burst Mode Operation

The LTM4608A is capable of Burst Mode operation in which

the power MOSFETs operate intermittently based on load

demand, thus saving quiescent current. For applications

where maximizing the efficiency at very light loads is a

high priority, Burst Mode operation should be applied. To

enable Burst Mode operation, simply tie the MODE pin to

VIN. During this operation, the peak current of the inductor

is set to approximately 20% of the maximum peak current

value in normal operation even though the voltage at the

ITH pin indicates a lower value. The voltage at the ITH pin

drops when the inductor’s average current is greater than

the load requirement. As the ITH voltage drops below 0.2V,

the BURST comparator trips, causing the internal sleep

line to go high and turn off both power MOSFETs.

In sleep mode, the internal circuitry is partially turned off,

reducing the quiescent current to about 450µA. The load

current is now being supplied from the output capacitor.

When the output voltage drops, causing ITH to rise above

0.25V, the internal sleep line goes low, and the LTM4608A re-

sumes normal operation. The next oscillator cycle will turn

on the top power MOSFET and the switching cycle repeats.

Pulse-Skipping Mode Operation

In applications where low output ripple and high efficiency

at intermediate currents are desired, pulse-skipping mode

should be used. Pulse-skipping operation allows the

LTM4608A to skip cycles at low output loads, thus increasing

efficiency by reducing switching loss. Floating the MODE

pin or tying it to VIN/2 enables pulse-skipping operation.

This allows discontinuous conduction mode (DCM) opera-

tion down to near the limit defined by the chip’s minimum

on-time (about 100ns). Below this output current level,

the converter will begin to skip cycles in order to maintain

output regulation. Increasing the output load current slightly,

above the minimum required for discontinuous conduction

mode, allows constant frequency PWM.

LTM4608A

4608afd

Forced Continuous Operation

In applications where fixed frequency operation is more

critical than low current efficiency, and where the lowest

output ripple is desired, forced continuous operation should

be used. Forced continuous operation can be enabled by

tying the MODE pin to GND. In this mode, inductor cur-

rent is allowed to reverse during low output loads, the ITH

voltage is in control of the current comparator threshold

Table 3. Output Voltage Response Versus Component Matrix (Refer to Figure 18) 0A to 3A Load Step

TYPICAL MEASURED VALUES

COUT1 VENDORS VALUE PART NUMBER COUT2 VENDORS VALUE PART NUMBER

TDK 22µF, 6.3V C3216X7S0J226M Sanyo POSCAP 150µF, 10V 10TPD150M

Murata 22µF, 16V GRM31CR61C226KE15L CIN (BULK) VENDORS VALUE PART NUMBER

TDK 100µF, 6.3V C4532X5R0J107MZ Sanyo 100µF, 10V 10CE100FH

Murata 100µF, 6.3V GRM32ER60J107M

VOUT

(V)

CIN

(CERAMIC)

CIN

(BULK)*

COUT1

(CERAMIC)

COUT2

(BULK)

ITH

VIN

(V)

DROOP

(mV)

PEAK-TO- PEAK

DEVIATION (mV)

RECOVERY

TIME (µs)

LOAD STEP

(A/µs)

RFB

(kΩ)

1.0 10µF 100µF 100µF × 2 None 68pF None 5 13 26 7 3 14.7

1.0 10µF 100µF 22µF × 1 150µF × 2 None None 100pF 5 17 34 8 3 14.7

1.0 10µF 100µF 100µF × 2 None 68pF None 3.3 13 26 7 3 14.7

1.0 10µF 100µF 22µF × 1 150µF × 2 None None 100pF 3.3 17 34 10 3 14.7

1.0 10µF 100µF 100µF × 2 None 68pF None 2.7 13 26 7 3 14.7

1.0 10µF 100µF 22µF × 1 150µF × 2 None None 100pF 2.7 17 34 8 3 14.7

1.2 10µF 100µF 100µF × 2 None 100pF None 5 16 32 8 3 10

1.2 10µF 100µF 22µF × 1 150µF × 2 None None 100pF 5 20 41 10 3 10

1.2 10µF 100µF 100µF × 2 None 100pF None 3.3 16 32 8 3 10

1.2 10µF 100µF 22µF × 1 150µF × 2 None None 100pF 3.3 20 41 10 3 10

1.2 10µF 100µF 100µF × 2 None 100pF None 2.7 16 32 10 3 10

1.2 10µF 100µF 22µF × 1 150µF × 2 None 47pF None 2.7 16 32 8 3 10

1.5 10µF 100µF 100µF × 2 None 100pF None 5 18 36 8 3 6.65

1.5 10µF 100µF 22µF × 1 150µF × 2 None None 47pF 5 20 41 12 3 6.65

1.5 10µF 100µF 100µF × 2 None 100pF None 3.3 16 32 10 3 6.65

1.5 10µF 100µF 22µF × 1 150µF × 2 None None 47pF 3.3 20 41 12 3 6.65

1.5 10µF 100µF 100µF × 2 None 100pF None 2.7 18 36 10 3 6.65

1.5 10µF 100µF 22µF × 1 150µF × 2 None None None 2.7 20 41 12 3 6.65

1.8 10µF 100µF 100µF × 1 None 47pF None 5 22 42 8 3 4.87

1.8 10µF 100µF 22µF × 1 150µF × 2 None None 47pF 5 21 42 12 3 4.87

1.8 10µF 100µF 100µF × 2 None 120pF None 3.3 21 43 12 3 4.87

1.8 10µF 100µF 22µF × 1 150µF × 2 None None 47pF 3.3 21 41 12 3 4.87

1.8 10µF 100µF 100µF × 2 None 120pF None 2.7 22 44 12 3 4.87

1.8 10µF 100µF 22µF × 1 150µF × 2 None None None 2.7 21 42 14 3 4.87

2.5 10µF 100µF 100µF × 1 None 100pF None 5 28 42 10 3 3.09

2.5 10µF 100µF 22µF × 1 150µF × 1 None 22pF None 5 33 60 10 3 3.09

2.5 10µF 100µF 100µF × 1 None 100pF None 3.3 30 60 10 3 3.09

2.5 10µF 100µF 22µF × 1 150µF × 1 None 22pF None 3.3 21 41 10 3 3.09

3.3 10µF 100µF 100µF × 1 100pF 22pF None 5 38 74 10 3 2.21

3.3 10µF 100µF 22µF × 1 150µF × 1 None None None 5 39 75 12 3 2.21

*Bulk capacitance is optional if VIN has very low input impedance.

applicaTions inForMaTion

throughout, and the top MOSFET always turns on with each

oscillator pulse. During start-up, forced continuous mode

is disabled and inductor current is prevented from revers-

ing until the LTM4608A’s output voltage is in regulation.

Multiphase Operation

For output loads that demand more than 8A of current,

multiple LTM4608As can be cascaded to run out of phase to

LTM4608A

4608afd

applicaTions inForMaTion

provide more output current without increasing input and

output voltage ripple. The CLKIN pin allows the LTM4608A

to synchronize to an external clock (between 0.75MHz

and 2.25MHz) and the internal phase locked loop allows

the LTM4608A to lock onto CLKIN’s phase as well. The

CLKOUT signal can be connected to the CLKIN pin of the

following LTM4608A stage to line up both the frequency

and the phase of the entire system. Tying the PHMODE

pin to SVIN, SGND or SVIN/2 (floating) generates a phase

difference (between CLKIN and CLKOUT) of 180°, 120°

or 90° respectively, which corresponds to a 2-phase,

3-phase or 4-phase operation. A total of 6 phases can be

cascaded to run simultaneously with respect to each other

by programming the PHMODE pin of each LTM4608A to

different levels. For a 6-phase example in Figure 2, the

2nd stage that is 120° out of phase from the 1st stage

can generate a 240° (PHMODE = 0) CLKOUT signal for

the 3rd stage, which then can generate a CLKOUT signal

that’s 420°, or 60° (PHMODE = SVIN) for the 4th stage.

With the 60° CLKIN input, the next two stages can shift

120° (PHMODE = 0) for each to generate a 300° signal

for the 6th stage. Finally, the signal with a 60° phase shift

on the 6th stage (PHMODE is floating) goes back to the

1st stage. Figure 3 shows the configuration for 12-phase

operation.

A multiphase power supply significantly reduces the

amount of ripple current in both the input and output

capacitors. The RMS input ripple current is reduced by,

and the effective ripple frequency is multiplied by, the

number of phases used (assuming that the input voltage

is greater than the number of phases used times the output

voltage). The output ripple amplitude is also reduced by

the number of phases used.

Figure 2. 6-Phase Operation

Figure 3. 12-Phase Operation

4608A F02

+120

PHASE 1

CLKOUTCLKIN

PHMODE

120

PHASE 3

CLKOUTCLKIN

PHMODE

240

+180+120

PHASE 5

CLKOUTCLKIN

PHMODESVIN

(420)

PHASE 2

CLKOUTCLKIN

PHMODE

+120

180

PHASE 4

CLKOUTCLKIN

PHMODE

+120

300

PHASE 6

CLKOUTCLKIN

PHMODE

4608 F02

+120

PHASE 1

CLKOUTCLKIN

PHMODE

120

PHASE 5

CLKOUTCLKIN

PHMODE

240

+180+120

PHASE 9

CLKOUTCLKIN

PHMODESVIN

(420)

PHASE 3

CLKOUTCLKIN

PHMODE

+120

180

PHASE 7

CLKOUTCLKIN

PHMODE

+120

300

PHASE 11

CLKOUTCLKIN

PHMODE

4608A F03

+120

PHASE 4

CLKOUTCLKIN

PHMODE

OUT1

OUT2

V+

LTC6908-2

210

PHASE 8

CLKOUTCLKIN

PHMODE

330

+180+120

PHASE 12

CLKOUTCLKIN

PHMODESVIN

(510)

150

PHASE 6

CLKOUTCLKIN

PHMODE

+120

270

PHASE 10

CLKOUTCLKIN

PHMODE

+120

(390)

PHASE 2

CLKOUTCLKIN

PHMODE

LTM4608A

4608afd

applicaTions inForMaTion

The LTM4608A device is an inherently current mode con-

trolled device. Parallel modules will have very good current

sharing. This will balance the thermals on the design.

Tie the ITH pins of each LTM4608A together to share the

current evenly. To reduce ground potential noise, tie the

ITHM pins of all LTM4608As together and then connect to

the SGND at only one point. Figure 19 shows a schematic

of the parallel design. The FB pins of the parallel module

are tied together. With parallel operation, input and out-

put capacitors may be reduced in part according to the

operating duty cycle.

Input RMS Ripple Current Cancellation

Application Note 77 provides a detailed explanation of

multiphase operation. The input RMS ripple current can-

cellation mathematical derivations are presented, and a

graph is displayed representing the RMS ripple current

reduction as a function of the number of interleaved phases.

Figure 4 shows this graph.

Spread Spectrum Operation

Switching regulators can be particularly troublesome

where electromagnetic interference (EMI) is concerned.

Switching regulators operate on a cycle-by-cycle basis to

transfer power to an output. In most cases, the frequency

of operation is fixed based on the output load. This method

of conversion creates large components of noise at the

frequency of operation (fundamental) and multiples of the

operating frequency (harmonics).

To reduce this noise, the LTM4608A can run in spread

spectrum operation by tying the CLKIN pin to SVIN. In

spread spectrum operation, the LTM4608A’s internal

oscillator is designed to produce a clock pulse whose

period is random on a cycle-by-cycle basis but fixed

between 70% and 130% of the nominal frequency. This

has the benefit of spreading the switching noise over

a range of frequencies, thus significantly reducing the

peak noise. Spread spectrum operation is disabled if

DUTY FACTOR (VO/VIN)

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

4608A F04

RMS INPUT RIPPLE CURRENT

DC LOAD CURRENT

6-PHASE

4-PHASE

3-PHASE

2-PHASE

1-PHASE

Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Phases

LTM4608A

4608afd

applicaTions inForMaTion

CLKIN is tied to ground or if it’s driven by an external

frequency synchronization signal. A capacitor value of

0.01µF must be placed from the PLLLPF pin to ground to

control the slew rate of the spread spectrum frequency

change. Add a control ramp on the TRACK pin with RSR

and CSR referenced to VIN. Figure 21 shows an example

for spread spectrum operation.

RSR ≥1

−ln 1−0.592









•500 •CSR











Output Voltage Tracking

Output voltage tracking can be programmed externally

using the TRACK pin. The output can be tracked up and

down with another regulator. The master regulator’s output

is divided down with an external resistor divider that is the

Figure 5. Dual Outputs (3.3V and 1.5V) with Tracking

same as the slave regulator’s feedback divider to implement

coincident tracking. The LTM4608A uses an accurate 10k

resistor internally for the top feedback resistor. Figure 5

shows an example of coincident tracking:

Slave =1+10k

RFB4









•VTRACK

VTRACK is the track ramp applied to the slave’s track pin.

VTRACK has a control range of 0V to 0.596V, or the internal

reference voltage. When the master’s output is divided

down with the same resistor values used to set the slave’s

output, this resistor divider is connected to the slave’s track

pin. The slave will then coincident track with the master

until it reaches its final value. The master will continue to

its final value from the slave’s regulation point. Voltage

tracking is disabled when VTRACK is more than 0.596V.

VIN

SVIN

RUN

PLLLPF

TRACK

MODE

PHMODE

VOUT

ITH

ITHM

PGOOD

BSEL

MGN

CLKOUT GND

CLKIN

RUN

TRACK

RSR CSR

100pF

22pF

RFB1

2.21k

100µF

MASTER

3.3V

VIN

TIE TO VIN

FOR DISABLE

AND DEFAULT

100µs SOFT-START

APPLY A CONTROL

RAMP WITH RSR AND

CSR TIED TO VIN WHERE

t = –(ln (1 – 0.596/VIN) • RSR • CSR)

OR APPLY AN EXTERNAL TRACKING RAMP

LTM4608A

SGND

VIN

SVIN

RUN

PLLLPF

TRACK

MODE

PHMODE

VOUT

ITH

ITHM

PGOOD

BSEL

MGN

CLKOUT GND

CLKIN

RUN

MASTER

3.3V RFB2

6.65k

50k

VIN

RFB3

10k

RFB4

6.65k

4608A F05

100µF

SLAVE

1.5V

LTM4608A

SGND

LTM4608A

4608afd

applicaTions inForMaTion

The track pin of the master can be controlled by an external

ramp or by RSR and CSR in Figure 5 referenced to VIN. The

RC ramp time can be programmed using equation:

t=– ln 1– 0.596V









•RSR •CSR













Ratiometric tracking can be achieved by a few simple

calculations and the slew rate value applied to the mas-

ter’s track pin. As mentioned above, the TRACK pin has

a control range from 0V to 0.596V. The master’s TRACK

pin slew rate is directly equal to the master’s output slew

rate in Volts/Time:

•10k =RFB3

where MR is the master’s output slew rate and SR is the

slave’s output slew rate in Volts/Time. When coincident

tracking is desired, then MR and SR are equal, thus RFB3

is equal the 10k. RFB4 is derived from equation:

RFB4 =0.596V

VFB

10k +VFB

RFB2

–VTRACK

RFB3

where VFB is the feedback voltage reference of the regulator

and VTRACK is 0.596V. Since RFB3 is equal to the 10k top

feedback resistor of the slave regulator in equal slew rate

or coincident tracking, then RFB4 is equal to RFB2 with VFB =

VTRACK. Therefore RFB3 = 10k and RFB4 = 6.65k in Figure 5.

In ratiometric tracking, a different slew rate maybe desired

for the slave regulator. RFB3 can be solved for when SR

is slower than MR. Make sure that the slave supply slew

rate is chosen to be fast enough so that the slave output

voltage will reach it final value before the master output.

For example: MR = 3.3V/ms and SR = 1.5V/ms. Then

RFB3 = 22.1k. Solve for RFB4 to equal to 4.87k.

For applications that do not require tracking or sequencing,

simply tie the TRACK pin to SVIN to let RUN control the

turn on/off. Connecting TRACK to SVIN also enables the

~100µs of internal soft-start during start-up. Load current

needs to be present during track down.

Power Good

The PGOOD pin is an open-drain pin that can be used to

monitor valid output voltage regulation. This pin monitors

a ±10% window around the regulation point. As shown

in Figure 20, the sequencing function can be realized in a

dual output application by controlling the RUN pins and the

PGOOD signals from each other. The 1.5V output begins

its soft starting after the PGOOD signal of 3.3V output

becomes high, and 3.3V output starts its shut down after

the PGOOD signal of 1.5V output becomes low. This can

be applied to systems that require voltage sequencing

between the core and sub-power supplies.

Figure 6. Output Voltage Coincident Tracking

OUTPUT VOLTAGE (V)

TIME

MASTER OUTPUT

SLAVE OUTPUT

4608A F06

LTM4608A

4608afd

Figure 7. 3.3VIN, 2.5V and 1.5VOUT Power Loss Figure 8. 5VIN, 3.3V and 1.5VOUT Power Loss

LOAD CURRENT (A)

POWER LOSS (W)

2.0

2.5

3.0

4608A F07

1.5

1.0

0246

0.5

4.0

3.5

3.3VIN 1.5VOUT

3.3VIN 2.5VOUT

LOAD CURRENT (A)

POWER LOSS (W)

2.0

2.5

3.0

4608A F08

1.5

1.0

0246

0.5

4.0

3.5

5VIN 1.5VOUT

5VIN 3.3VOUT

applicaTions inForMaTion

Slope Compensation

The module has already been internally compensated for

all output voltages. Table 3 is provided for most applica-

tion requirements. A spice model will be provided for other

control loop optimization. For single module operation,

connect ITHM pin to SGND. For parallel operation, tie ITHM

pins together and then connect to SGND at one point. Tie

ITH pins together to share currents evenly for all phases.

Output Margining

For a convenient system stress test on the LTM4608A’s

output, the user can program the LTM4608A’s output to

±5%, ±10% or ±15% of its normal operational voltage.

The margin pin with a voltage divider is driven with a small

three-state gate as shown in Figure 18, for the three margin

states (high, low, no margin). When the MGN pin is <0.3V,

it forces negative margining in which the output voltage

is below the regulation point. When MGN is >VIN – 0.3V,

the output voltage is forced above the regulation point.

The amount of output voltage margining is determined by

the BSEL pin. When BSEL is low, it is 5%. When BSEL is

high, it is 10%. When BSEL is floating, it is 15%. When

margining is active, the internal output overvoltage and

undervoltage comparators are disabled and PGOOD re-

mains high. Margining is disabled by tying the MGN pin

to a voltage divider as shown in Figure 20.

Thermal Considerations and Output Current Derating

The power loss curves in Figures 7 and 8 can be used

in coordination with the load current derating curves in

Figures 9 to 16 for calculating an approximate θJA for the

module with various heat sinking methods. Thermal models

are derived from several temperature measurements at

the bench, and thermal modeling analysis. Thermal Ap-

plication Note 103 provides a detailed explanation of the

analysis for the thermal models and the derating curves.

Tables 4 and 5 provide a summary of the equivalent θJA

for the noted conditions. These equivalent θJA parameters

are correlated to the measured values and improve with

air flow. The junction temperature is maintained at 125°C

or below for the derating curves.

LTM4608A

4608afd

applicaTions inForMaTion

Figure 9. No Heat Sink with 3.3VIN to 1.5VOUT Figure 10. BGA Heat Sink with 3.3VIN to 1.5VOUT

Figure 11. No Heat Sink with 5VIN to 1.5VOUT Figure 12. BGA Heat Sink with 5VIN to 1.5VOUT

Figure 13. No Heat Sink with 3.3VIN to 2.5VOUT Figure 14. BGA Heat Sink with 3.3VIN to 2.5VOUT

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F09

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F10

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F11

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F12

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F13

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F14

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

LTM4608A

4608afd

applicaTions inForMaTion

Table 4. 1.5V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)

Figures 9, 11 3.3, 5 Figures 7, 8 0 None 25

Figures 9, 11 3.3, 5 Figures 7, 8 200 None 21

Figures 9, 11 3.3, 5 Figures 7, 8 400 None 20

Figures 10, 12 3.3, 5 Figures 7, 8 0 BGA Heat Sink 23.5

Figures 10, 12 3.3, 5 Figures 7, 8 200 BGA Heat Sink 22

Figures 10, 12 3.3, 5 Figures 7, 8 400 BGA Heat Sink 22

Table 5. 3.3V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIR FLOW (LFM) HEAT SINK θJA (°C/W)

Figure 15 5 Figure 8 0 None 25

Figure 15 5 Figure 8 200 None 21

Figure 15 5 Figure 8 400 None 20

Figure 16 5 Figure 8 0 BGA Heat Sink 23.5

Figure 16 5 Figure 8 200 BGA Heat Sink 22

Figure 16 5 Figure 8 400 BGA Heat Sink 22

Figure 15. No Heat Sink with 5VIN to 3.3VOUT Figure 16. BGA Heat Sink with 5VIN to 3.3VOUT

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F15

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

AMBIENT TEMPERATURE (°C)

LOAD CURRENT (A)

120

4608A F16

60 80 100

50 70 90 110

400LFM

200LFM

0LFM

LTM4608A

4608afd

applicaTions inForMaTion

Figure 17. Recommended PCB Layout

Safety Considerations

The LTM4608A modules do not provide isolation from VIN

to VOUT. There is no internal fuse. If required, a slow blow

fuse with a rating twice the maximum input current needs

to be provided to protect each unit from catastrophic failure.

Layout Checklist/Example

The high integration of LTM4608A makes the PCB board

layout very simple and easy. However, to optimize its

electrical and thermal performance, some layout con-

siderations are still necessary.

• Use large PCB copper areas for high current path,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Placehighfrequencyceramicinputandoutputcapaci-

tors next to the VIN, GND and VOUT pins to minimize

high frequency noise.

• Placeadedicatedpowergroundlayerunderneaththe

unit.

• Tominimizetheviaconductionlossandreducemodule

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Donotputviasdirectlyonthepads,unlesstheyare

capped.

• UseaseparatedSGNDgroundcopperareaforcom-

ponents connected to signal pins. Connect the SGND

to GND underneath the unit.

Figure 17 gives a good example of the recommended layout.

GND

4608A F17

CIN

COUT

CIN

VIN

VOUT

LTM4608A

4608afd

Typical applicaTions

Figure 18. Typical 3V to 5.5VIN, 2.5V at 8A Design

Figure 19. Two LTM4608As in Parallel, 1.5V at 16A Design.