ICS951901
Integrated
Circuit
Systems, Inc.
0670B—07/15/04
Programmable Frequency Generator & Integrated Buffers for Pentium III Processor
Block Diagram
Recommended Application:
Single chip clock solution for IA platform.
Output Features:
• 3 - CPU @ 2.5V
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 2 - AGP @ 3.3V
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
• 2 - REF @3.3V, 14.318MHz.
Features:
• Programmable ouput frequency.
• Programmable ouput rise/fall time.
• Programmable SDRAM and CPU skew.
• Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
• Watchdog timer technology to reset system
if over-clocking causes malfunction.
• Uses external 14.318MHz crystal.
• FS pins for frequency select
Skew Specifications:
• CPU - CPU: < 175ps
• SDRAM - SDRAM < 250ps (except SDRAM12)
• PCI - PCI: < 500ps
• CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND.
1 These are double strength.
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK (2:0)
SDRAM (12:0)
PCICLK (4:0)
AGP (1:0)
PCICLK_F
2
5
13
3
2
X1
X2 XTAL
OSC
CPU
DIVDER
SDRAM
DIVDER
PCI
DIVDER
Stop
Stop
Stop
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
AGP_SEL
Control
Logic
Config.
Reg.
/ 2
REF(1:0)
AGP
DIVDER
VDDA
(AGPSEL)REF0
*(FS3)REF1
GND
X1
X2
VDDPCI
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
VDDAGP
AGPCLK0
AGPCLK1
GND
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
SDATA
SCLK
11
*VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
ICS951901
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FS3FS2FS1FS0CPU
SDRAM PCI AGP1 AGP0
Bit7 Bit6 Bit5 Bit4 MHz MHz MHz SEL=1 SEL=0
0 0 0 0 0 66.67 66.67 33.33 66.67 64
0 0 0 0 1 66.67 100.00 33.33 66.67 64
0 0 0 1 0 66.67 133.34 33.33 66.67 64
0 0 0 1 1 75.00 75.00 37.50 75.00 64
0 0 1 0 0 83.31 83.31 33.32 66.64 64
0 0 1 0 1 90.00 90.00 30.00 60.00 64
0 0 1 1 0 95.00 95.00 31.67 63.33 64
0 0 1 1 1 100.00 66.67 33.33 66.67 64
0 1 0 0 0 100.00 100.00 33.33 66.67 64
0 1 0 0 1 100.00 133.34 33.33 66.67 64
0 1 0 1 0 105.00 105.00 35.00 70.00 64
0 1 0 1 1 112.00 112.00 33.60 67.20 64
0 1 1 0 0 117.99 117.99 35.40 70.80 64
0 1 1 0 1 124.09 124.09 31.02 62.05 64
0 1 1 1 0 133.34 100.00 33.33 66.67 64
01111
133.34 133.34 33.33 66.67 64
Bit2
2
ICS951901
0670B—07/15/04
General Description
Pin Configuration
The ICS951901 is a single chip clock solution for desktop
designs using 630S chipsets. It provides all necessary
clock signals for such a system.
The ICS951901 belongs to ICS new generation of
programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing
output functions, changing output frequency, configuring
output strength, configuring output to output skew, changing
spread spectrum amount, changing group divider ratio and
dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system becomes
unstable from over clocking.
Power Gr oups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
EDOM 12niP 72niP82niP03niP13niP
011MARDS01MARDS9MARDS8MARDS
1#POTS_UPC#POTS_ICP#POTS_MARDS#DP
MODE Pin Power Management Control Input
PIN NUMBER PIN NAME TYPE DESCRIPTI O N
1, 7, 15, 22, 25,
35, 43 VDD PWR 3.3V Power supply for SD RA M output buffers , PCI output buf fers,
reference out put buffer s and 48MHz out put
AG PSEL IN AG P frequency s elect pin.
REF 0 O UT 14. 318 MHz reference c lock .
F S 3 I N Frequency s elec t pin.
REF 1 O UT 14. 318 MHz reference c lock .
4, 14, 18, 19, 29,
32, 39, 44 G ND PW R G r ound pin f or 3V out puts.
5 X1 I N Cr ys t al input,nom inally 14. 318M Hz .
6 X2 O UT Cry s t al out put, nominally 14. 318M Hz .
F S 1 I N Frequency s elec t pin.
PCICLK_F O UT PCI clock output, not affec ted by PCI _S T OP#
F S 2 I N Frequency s elec t pin.
PCICLK0 O UT PCI clock output.
13, 12, 11, 10 PCICLK (4: 1) O UT PCI clock outputs .
17, 16, AGP (1:0) O UT AGP out put s def ined as 2X P CI . T hese m ay not be stopped.
F S 0 I N Frequency s elec t pin.
48MHz O UT 48MHz output c loc k
MODE IN P in 27, 28, 30, & 31 func tion select pin
0=Des k top 1=Mobile mode
24_48MHz O UT Clock output for super I/ O /USB default is 24MHz
23 SDATA I/O Data pin for I2C c irc uit r y 5V tolerant
24 SCLK IN Clock pin of I 2C circ uit r y 5V toler ant
CPU_STOP# IN S tops all PCI CLK s bes ides the PCI CLK_F clock s at logic 0 level,
when input is low and MO DE pin is in Mobile mode
SD RAM11 OUT SD RAM clock output
PCI_STOP# IN Stops all CPUCLKs cloc k s at logic 0 level, when input is low and
MODE pin is in Mobile mode
SD RAM10 OUT SD RAM clock output
SDRA M9 OUT SDRA M c loc k output
SDRAM_STOP# IN S tops all SDRAM cloc k s at logic 0 level, w hen input is low and
MODE pin is in Mobile mode
PD# IN
Asynchronous
active
low
input
pin
used
to
power
down
the
device
int o a low power state. The int er nal cloc k s ar e disabled and t he
VCO and t he c r ys tal are st opped. The latenc y of the power down will
notbe greater than 3ms
SDRA M8 OUT SDRA M c loc k output
26 33, 34, 36,
37, 38, 40, 41,
42
SDRA M ( 12,
7:0) OUT SDRA M clock outputs
45, 46, 47 CPUCLK (2:0) O UT CP U cloc k out puts.
48 VDDL PWR Power pin for t he CPUCLK s . 2.5V
31
20
2
8
9
21
3
30
27
28
3
ICS951901
0670B—07/15/04
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
I2C is a trademark of Philips Corporation
FS3 FS2 FS1 FS0 CPU SDRAM P CI AGP1 AGP0 Spread % PWD
Bit2 Bit7 Bit6 Bit5 Bit4 MHz MHz MHz SEL=1 SEL=0
0000066.6766.6733.3366.6764± 0.35% cent er s pread
0000166.67100.0033.3366.6764± 0.35% center s pread
0001066.67133.3433.3366.6764± 0.35% center s pread
0001175.0075.0037.5075.0064± 0.35% center s pread
0010083.3183.3133.3266.6464± 0.35% center s pread
0010190.0090.0030.0060.0064± 0.35% center s pread
0011095.0095.0031.6763.3364± 0.35% center s pread
00111
100.00 66.67 33.33 66.67 64 ± 0. 35% cent er s pread
01000
100.00 100.00 33.33 66.67 64 ± 0.35% cent er spread
01001100.00133.3433.3366.6764± 0.35% center s pread
01010105.00105.0035.0070.0064± 0.35% center s pread
01011112.00112.0033.6067.2064± 0.35% center s pread
01100117.99117.9935.4070.8064± 0.35% center s pread
01101124.09124.0931.0262.0564± 0.35% center s pread
Bit 201110133.34100.0033.3366.6764± 0.35% center s pread 00000
Bit 7:401111
133.34 133.34 33.33 66.67 64 ± 0.35% cent er spread Note1
10000
75.00 100.00 37.50 75.00 64 ± 0.35% cent er s pread
1000175.00112.5032.1464.2964± 0.35% center s pread
1001075.00150.0032.1464.2964± 0.35% center s pread
1001183.31111.0733.3266.6464± 0.35% center s pread
1010083.32166.6531.2562.4964± 0.35% center s pread
1010190.0060.0030.0060.0064± 0.35% center s pread
1011090.00120.0030.0060.0064± 0.35% center s pread
10111
95.00 63.33 31.67 63.33 64 ± 0.35% center s pread
11000
95.00 126.66 31.67 63.33 64 ± 0.35% cent er s pread
11001105.0070.0035.0070.0064± 0.35% center s pread
11010105.00140.0035.0070.0064± 0.35% center s pread
11011112.0084.0033.6067.2064± 0.35% center s pread
11100117.9988.4935.4070.8064± 0.35% center s pread
11101124.0993.0731.0262.0564± 0.35% center s pread
11110129.9997.4932.5064.9964± 0.35% center s pread
11111140.00105.0035.0070.0064
± 0. 35% cent er s
p
read
B it 3 0 - Frequency i s s el ect ed by hardware s el ec t, Lat ched i nputs 0
1 - Frequenc y i s s el ected by Bi t , 2 7:4
Bit 1 0 - Normal 1
1 - Spread Spec trum Enabled
B it 0 0 - Running 0
1 - Tristate all outputs
Bit
Description
4
ICS951901
0670B—07/15/04
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB311 4KLCICP
4tiB211 3KLCICP
3tiB111 2KLCICP
2tiB011 1KLCICP
1tiB91 0KLCICP
0tiB81 F_KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB121 zHM84_42
5tiB021 zHM84
4tiB621 21MARDS
3tiB721 11MARDS
2tiB821 01MARDS
1tiB031 9MARDS
0tiB131 8MARDS
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X )kcabdaeR(3SF
6tiB-X )kcabdaeR(2SF
5tiB-X )kcabdaeR(1SF
4tiB-X )kcabdaeR(0SF
3tiB310FER
2tiB211FER
1tiB711 1KLCPGA
0tiB611 0KLCPGA
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB331 7MARDS
6tiB431 6MARDS
5tiB631 5MARDS
4tiB731 4MARDS
3tiB831 3MARDS
2tiB041 2MARDS
1tiB141 1MARDS
0tiB241 0MARDS
TIB#NIPDWPNOITPIRCSED
7tiB-1 84_42leS )zHM84:0,zHM42:1(
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB741 0KLCUPC
2tiB641 1KLCUPC
1tiB541 2KLCUPC
0tiB-1 devreseR
5
ICS951901
0670B—07/15/04
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-1 devreseR
4tiB-0 devreseR
3tiB-1 devreseR
2tiB-0 devreseR
1tiB-0 devreseR
0tiB-1 devreseR
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB3,20 X2=1,X1=0htgnertsFER
6tiB540 lortnoC-potS-2KLCUPC ,2KLCUPClortnoclliw#POTS_UPC=0 wolsi#POTS_UPCfinevegninnureerfsi2KLCUPC=1
5tiB-X )kcabdaeR(LESPGA
4tiB-X )kcabdaeR(EDOM
3tiB-X )kcabdaeR(#POTS_UPC
2tiB-X )kcabdaeR(#POTS_ICP
1tiB-X )kcabdaeR(#POTS_MARDS
0tiB-0 elggoTdeepSPGA ,gnittestupnihctalybdenimretedeblliw)2nip(LESPGA=0 gnittestupnihctalfoetisoppoeblliwLESPGA=1
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 devreseR
3tiB-0 devreseR
2tiB-1 devreseR
1tiB-0 devreseR
0tiB-0 devreseR
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
tiBDWPnoitpircseD
7tiB0 qerf21&11B=1/qerf0B/wH=0
6tiB0 elbane=1/elbasid=0elbanEDW
5tiB0 mrala=1/lamron=0sutatSDW
4tiB0 2tib0etyB,ycneuqerFefaSDW
3tiB0 3SF,ycneuqerFefaSDW
2tiB0 2SF,ycneuqerFefaSDW
1tiB0 1SF,ycneuqerFefaSDW
0tiB0 0SF,ycneuqerFefaSDW
Byte 9: Watchdog Timer Count Register
tiBDWPnoitpircseD
7tiB0 esehtfonoitatneserperlamicedehT sm1rosm092otdnopserrocstib8 erofebtiawlliwremitgodhctaweht ehtteserdnaedommralaotseogti tluafeD.gnittesefasehtotycneuqerf 6.4=sm092X61sipurewopta .sdnoces
6tiB0
5tiB0
4tiB1
3tiB0
2tiB0
1tiB0
0tiB0
6
ICS951901
0670B—07/15/04
Notes:
1. PWD = Power on Default
Byte 11: VCO Frequency Control Register
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
tiBDWPnoitpircseD
7tiBX 0tiBrediviDOCV
6tiBX 6tiBrediviDFER
5tiBX 5tiBrediviDFER
4tiBX 4tiBrediviDFER
3tiBX 3tiBrediviDFER
2tiBX 2tiBrediviDFER
1tiBX 1tiBrediviDFER
0tiBX 0tiBrediviDFER
Byte 12: VCO Frequency Control Register
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
tiBDWPnoitpircseD
7tiBX 8tiBrediviDOCV
6tiBX 7tiBrediviDOCV
5tiBX 6tiBrediviDOCV
4tiBX 5tiBrediviDOCV
3tiBX 4tiBrediviDOCV
2tiBX 3tiBrediviDOCV
1tiBX 2tiBrediviDOCV
0tiBX 1tiBrediviDOCV
Byte 13: Spread Sectrum Control Register Byte 14: Spread Sectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
tiBDWPnoitpircseD
7tiBX 7tiBmurtcepSdaerpS
6tiBX 6tiBmurtcepSdaerpS
5tiBX 5tiBmurtcepSdaerpS
4tiBX 4tiBmurtcepSdaerpS
3tiBX 3tiBmurtcepSdaerpS
2tiBX 2tiBmurtcepSdaerpS
1tiBX 1tiBmurtcepSdaerpS
0tiBX 0tiBmurtcepSdaerpS
tiBDWPnoitpircseD
7tiBX devreseR
6tiBX devreseR
5tiBX devreseR
4tiBX 21tiBmurtcepSdaerpS
3tiBX 11tiBmurtcepSdaerpS
2tiBX 01tiBmurtcepSdaerpS
1tiBX 9iBmurtcepSdaerpS
0tiBX 8tiBmurtcepSdaerpS
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control Byte 16: Output Skew Control
tiBDWPnoitpircseD
7tiB1 lortnoCwekS21MARDS
6tiB0
5tiB0 lortnoCwekS)0:11(MARDS
4tiB1
3tiB1 lortnoCwekS2KLCUPC
2tiB1
1tiB1 lortnoCwekS)0:1(KLCUPC
0tiB0
tiBDWPnoitpircseD
7tiBX devreseR
6tiBX devreseR
5tiBX devreseR
4tiBX devreseR
3tiBX devreseR
2tiBX devreseR
1tiBX devreseR
0tiBX devreseR
7
ICS951901
0670B—07/15/04
Byte 17: Output Rise/Fall Time Select Register Byte 18: Output Rise/Fall Time Select Register
tiBDWPnoitpircseD
7tiB1 lortnoCetaRwelS)0:3(ICP
6tiB0
5tiB1 lortnoCetaRwelSF_ICP
4tiB0
3tiB1 lortnoCetaRwelS2KLCUPC
2tiB0
1tiB 0lortnoCetarwelS1KLCUPC
0tiB
tiBDWPnoitpircseD
7tiB1 lortnoCetaRwelS:21MARDS
6tiB0
5tiB1 lortnoCetaRwelS:1KLCPGA
4tiB0
3tiB1 lortnoCetaRwelS:0KLCPGA
2tiB0
1tiB1 lortnoCetaRwelS:4KLCICP
0tiB0
Byte 19: Output Rise/Fall Time Select Register Byte 20: Output Rise/Fall Time Select Register
tiBDWPnoitpircseD
7tiB1 lortnoCetaRwelS:zHM84
6tiB0
5tiB1 lortnoCetaRwelS:zHM84_42
4tiB0
3tiB1 lortnoCetaRwelS:1FER
2tiB0 lortnoCetaRwelS:0FER
1tiB1 lortnoCetaRwelS:)0:11(MARDS
0tiB0
tiBDWPnoitpircseD
7tiB0 devreseR
6tiB0 devreseR
5tiB0 devreseR
4tiB0 devreseR
3tiB0 devreseR
2tiB0 devreseR
1tiB 0lortnoCetaRwelS0KLCUPC
0tiB
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
T o program the VCO frequency for over -clocking.
0. Bef ore trying to program our cloc k manually, consider using ICS pro vided software utilities f or easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware pow er up frequency .
2. Write 0001, 1001 (19H) to b yte 8 for readbac k of 21 bytes (b yte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to b yte 13 to 20 with the v alues you copy from step 3. This maintains the output spread, ske w and sle w
rate.
7. The abov e procedure is only needed when changing the VCO f or the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
8
ICS951901
0670B—07/15/04
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
El ect r i cal Char act er ist i cs - I n put /Suppl y/Comm on Ou tp ut Par am et er s
TA = 0 - 70°C; Supply Volt age VDD = 3.3 V +/-5%VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input High Voltage VIH 2V
DD + 0 .3 V
Input Lo w Voltage VIL VSS - 0.3 0 .8 V
Supply Curr ent IDD CL=30 pF, CPU @ 66, 100 M Hz 3 90 400 m A
Powe r D own PD 300 600 mA
Input freque ncy Fi VDD = 3.3 V; 12 14.32 16 MHz
In p u t Ca p aci ta nce 1CIN Log i c Inputs 5 pF
CINX X1 & X2 pins 27 45 pF
Transition Time Ttrans To 1st crossing of target Freq. 3
Settling Tim e TSFrom 1 st crossing to 1% target Freq.
Clk Stabilization1TSTAB From VDD= 3.3 V to 1% target Freq. 3 m s
Skew TCPU-PCI CPUVT= 1 .5 V PCI VT=1.25V 1 1.9 4 ns
Skew TCPU-SDRAM CPUVT= 1.5 V SDRAM VT=1.25 -500 -300 0 ps
1 Guaranteed b
y
desi
g
n, not 100% tested in
p
roduction.
9
ICS951901
0670B—07/15/04
Elect r i cal Charact eri st ics - CPU
TA = 0 - 70°C; V DDL = 2.5 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless ot herwis e spec i f i ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance1RDSP2B VO = VDD*(0.5) 10 20
Output Impedance1RDSN2B VO = VDD*(0.5) 10 20
Out put High Vol t age VOH2B IOH = -12.0 mA 2 V
Out put Low V oltage V OL2B IOL = 12 mA 0.4 V
Output High Current IOH2B VOH = 1. 7 V -19 m A
Out put Low Current I OL2B VOL = 0.7 V 19 mA
Ri se T im e1tr2B VOL = 0.4 V, VOH = 2.0 V 0. 4 1.2 1.6 ns
Fall Time1tf2B VOH = 2.0 V, VOL = 0.4 V 0. 4 1. 1 1. 6 ns
Duty Cyc le1dt2B VT = 1. 25 V 45 46. 9 55 %
S kew window0:1 tsk2B VT = 1. 25 V 43 175 ps
S kew window0:2 tsk2B VT = 1. 25 V 142 375 ps
Jitter, Cycle-to-cycle1tjcyc-cyc VT = 1.25 V, CPU= 66 M Hz 177 250 ps
1Guarant eed by desi gn, not 100% t es ted in produc tion.
Elect r i cal Charact eri st ics - 24-48M Hz
TA = 0 - 70°C; V DD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 10-20 pF (unles s ot herwi s e spec ified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance RDSP5B1VO = VD
D
*(0.5) 20 60
Output Impedance RDSN5B1VO = VD
D
*(0.5) 20 60
Output High Voltage VOH15 IOH = -14 mA 2.4 V
Outpu t Lo w V o l tage V OL5 IOL = 6. 0 m A 0. 4 V
Out put High Current IOH5 VOH = 2.0 V -20 m A
Out put Low Current IOL5 VOL = 0.8 V 10 mA
Ri se Tim e 1tr5 VOL = 0.4 V, VOH = 2. 4 V 0. 4 1.45 4 ns
Fall Time1tf5 VOH = 2. 4 V , VOL = 0.4 V 0. 4 1.5 4 ns
Duty Cyc le1dt5 VT = 1.5 V 45 52. 5 55 %
Jitter tcycle to cycle VT = 1. 5 V 210 500 ps
1Guarant eed by desi gn, not 100% test ed i n produc tion.
10
ICS951901
0670B—07/15/04
Elect r i cal Charact eri st ics - PCI
TA = 0 - 70°C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-30 pF (unles s ot herwi s e spec i f i ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put Impedanc e RDSP1B1VO = VDD*(0.5) 12 55
Out put Impedanc e RDSN1B1VO = VDD*(0.5) 12 55
Out put High Vol tage V OH1 IOH = -1 mA 2.4 V
Out put Low V oltage V OL1 IOL = 1 m A 0. 5 5 V
Out put Hi gh Current IOH1 VOH @ MIN = 1. 0 V -29 m A
Out put Low Current IOL1 VOL @ MI N = 1. 95 V 29 m A
Ri se T im e1tr1 VOL = 0.4 V, VOH = 2.4 V 0. 5 2.3 2. 5 ns
Fall Time1tf1 VOH = 2.4 V, VOL = 0.4 V 0. 5 2.3 2.5 ns
Dut
y
C
y
cle1dt1 VT = 1.5 V 45 51.2 55 %
S kew window1tsk1 VT = 1.5 V 108 500 ps
Jitter, Cycle-to-cycle1tjcyc-cyc1 VT = 1.5 V 353 500 ps
1Guarant eed by design, not 100% t es ted i n produc tion.
Ele c tr ic a l Ch a r a c te r is tic s - S DRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20-30 pF (unless ot herwise spec i f i ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put I m pedanc e RDSP3B1VO = VD
D
*(0.5) 10 24
Out put I m pedanc e RDSN3B1VO = VD
D
*(0.5) 10 24
Out put High Vol t age V OH3 IOH = -18 mA 2.4 V
Out put Low V oltage V OL3 IOL = 9.4 mA 0.4 V
Out put High Current IOH3 VOH = 2.0 V -46 mA
Out put Low Current I OL3 VOL = 0.8V m A
Rise T ime1tr3 VOL = 0.4 V, VOH = 2.4 V 0. 8 1. 6 ns
Fall Time1tf3 VOH = 2.4 V, VOL = 0. 4 V 0. 8 1.6 ns
Duty Cycle1dt3 VT = 1. 5 V 45 48.5 55 %
S kew window1(0:11) tsk3 VT = 1. 5 V 192 250 ps
S kew window1( 0:12) tsk3 VT = 1. 5 V 290 500 ps
Jitter, Cycle-to-cy cle1tjcyc-cyc3 VT = 1.5 V, CPU=66,100,133 MHz 173 250 ps
1Guarant eed by design, not 100% tes t ed i n produc tion.
11
ICS951901
0670B—07/15/04
Elect r i cal Charact eri st ics - AG P
TA = 0 - 70°C; V DD=3.3V +/-5%; CL = 20 pF (unles s ot herwise s pecif i ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put I m pedance RDSP4B1VO=VD
D
*(0.5) 12 55
Out put I m pedance RDSN4B1VO=VD
D
*(0.5) 12 55
Out put Hi gh V olt age V OH4B IOH = -18 mA 2 V
Out put Low V oltage V OL4B IOL = 18 m A 0. 4 V
Output High Current IOH4B VOH = 2.0 V -19 m A
Out put Low Current I OL4B VOL = 0.8 V 19 mA
Ri se Tim e1tr4B VOL = 0.4 V, VOH = 2. 4 V 0. 5 1.5 2 ns
Fall Time1tf4B VOH = 2.4 V , V OL = 0. 4 V 0. 5 1.6 2 ns
Dut
y
C
y
cle1dt4B VT = 1.5 V 45 52. 3 55 %
S kew window1 tsk1VT = 1. 5 V 55. 5 175 ps
Jitter Cyc-Cyc tjcyc-cyc1VT = 1. 5 V 239 500 ps
1Guarant eed by desi gn, not 100% test ed i n produc tion.
El ectr i cal Charact er i st i cs - REF
TA = 0 - 70° C; V DD = 3.3 V +/ -5%;V DDL = 2.5 V +/ -5%; CL = 20 pF (unl ess ot he rwise st ated)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Hi gh Vol t age VOH5 IOH = -1 2 mA 2.4 V
O ut put Low V ol tage V OL5 IOL = 9 mA 0.4 V
Output High Current IOH5 VOH = 2.0 V -22 m A
Output Low Current IOL5 VOL = 0.8 V 16 m A
Rise T i m e1tr5 VOL = 0.4 V, VO H = 2.4 V 1.8 4 ns
Fall Time1tf5 VOH = 2. 4 V , V OL = 0.4 V 1. 9 4 ns
Duty Cycle1dt5 VT = 50% 45 54.5 55 %
1Guaran teed b
y
desi
g
n, not 100% teste d in producti on.
12
ICS951901
0670B—07/15/04
General I2C serial interface information for the ICS951901
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending Byte 0 through Byte 28
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends Byte 0 through byte 6 (default)
• ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 6).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
*See notes on the following page.
Controll er (Host) ICS (Sla ve/Receiver)
Start Bit
Address D2(H) ACK
Dum m y Com m a nd Code ACK
Dum m y B yt e Count ACK
Byte 0 ACK
Byte 1 ACK
Byte 2 ACK
Byte 3 ACK
Byte 4 ACK
Byte 5 ACK
Byte 6 ACK
Byte 18 ACK
Byte 19 ACK
Byte 20 ACK
Stop Bit
H ow to Write: Control l er (Host) ICS (Slave/Receiver)
Start Bit
Address D3(H) ACK
Byte Count
ACK Byte 0
ACK Byte 1
ACK Byte 2
ACK Byte 3
ACK Byte 4
ACK Byte 5
ACK Byte 6
ACK
If 7H has been wri tten t o B6 Byte 7
ACK
If 1 AH has b een wri t ten t o B6 Byte18
ACK
If 1 BH has b een wri t ten t o B6 Byte 19
ACK
If 1 C H has b een wri tt en to B 6 Byte 20
ACK
Stop Bit
How to Read:
13
ICS951901
0670B—07/15/04
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4. The input is operating at 3.3V logic levels.
5. The data byte format is 8 bit bytes.
6. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
7. At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I2C registers description for ICS951901
Programmable System Frequency Generator
Reg ister Name Byte Descri p t ion PWD Defau lt
F unc tionality &
F r equency S elec t
Register 0Output frequency , hardware / I 2C
f r equency s elec t, s pr ead spec trum &
out put enable c ontrol regis ter.
See indiv idual
byte
description
O utput Control Registers 1-6 A ctive / inact iv e out put cont r ol
regis t er s /latc h inputs read bac k .
See indiv idual
byte
description
Vendor ID & Revis ion I D
Registers 7
By te 11 bit[7:4] is ICS vendor id -
1001. Other bits in t his r egister
designate devic e r ev ision ID of this
part.
See indiv idual
byte
description
By t e Count
Read Bac k Register 8
W r iting to this regis ter will configure
byte count and how many by te will
be read back . Do not write 00H to
this byte.
08H
W atchdog T im er
Count Register 9W r iting to this regis ter will configure
t he num ber of seconds for t he
wat c hdog t im er t o r es et. 10H
W atchdog Cont r ol
Registers 10 Bit [6:0] W atchdog enable, wat c hdog s t atus
and progr amm able 'saf e' frequency '
can be c onf igur ed in t his r egis ter. 000,0000
VCO Contr ol S elec tion
Bit 10 Bit [7]
T his bit s elec t whether the output
f r equenc y is c ontrol by
hardwar e/ by te 0 conf igur at ions or
byte 11&12 progr am ming.
0
VCO Fr equenc y Cont r ol
Registers 11-12
T hes e r egisters c ontrol t he div ider s
ratio into the phase det ector and
t hus control t he V CO output
f r equency .
Depended on
hardware/byte
0 configurat ion
Spr ead S pectrum
Cont r ol Registers 13-14 T hese r egisters c ontrol t he s pr ead
perc ent age am ount.
Depended on
hardware/byte
0 configurat ion
G r oup S kews Control
Registers 15-16 Incr em ent or decr em ent the group
sk ew am ount as c om pared to t he
init ial s k ew.
See indiv idual
byte
description
O utput Ris e/Fall Time
Selec t Registers 17-20 These r egis ters will c ontrol t he
out put rise and fall tim e.
See indiv idual
byte
description
14
ICS951901
0670B—07/15/04
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS951901
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of P ow er-
On reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
8.2K
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor .
15
ICS951901
0670B—07/15/04
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94209. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94209.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
16
ICS951901
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PCI_STOP# Timing Diagram
PCI_ST OP# is an asynchronous input to the ICS94209. It is used to turn off the PCICLK clocks for lo w po wer oper ation.
PCI_STOP# is synchronized by the ICS94209 internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94209.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
17
ICS951901
0670B—07/15/04
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power
operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS94209. All other clocks will
continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and
start in such a manner that guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the SDRAM clocks inside the ICS94209.
3. All other clocks continue to run undisturbed.
18
ICS951901
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PD# Timing Diagram
The power down selection is used to put the par t into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in po wer do wn. When PD# is active lo w all cloc ks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but confor ming to the sequence requirements shown below.
PCI_ST OP# and CPU_ST OP# are considered to be don't cares during the power do wn operations. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping
and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94209 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Cr ystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
19
ICS951901
0670B—07/15/04
Ordering Information
ICS951901yFLF-T
INDEX
AREA
12
N
D
h x 45°
E1 E
SEATING
PLANE
A1
A
e
-C-
b
.10 (.004) C
c
L
300 mil SSOP Package
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α0° 8° 0° 8°
MIN MAX MIN MAX
48 15.75 16.00 .620 .630
10-0034
SYMBOL In Millimeters In Inches
COMMON DIMENSI ONS COMMON DIMENSION S
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
Example:
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
ICS XXXXXX y F LF- T