2008 Microchip Technology Inc. DS21160G-page 1
24LC21A
Features:
• Single Supply with Operation Down to 2.5V
• Completely Implements DDC1™/DDC2™
Interface for Monitor Identification, Including
Recovery to DDC1
• Pin and Function Compatible with 24LC21
• Low-Power CMOS Technology
- 1 mA typical active cur rent
-10 A standby current typical at 5.5V
• 2-Wire Serial Interface Bus, I2C™ Compatible
• 100 kHz (2.5V) and 400 kHz (5V) Compatibility
• Self-Timed Wri te Cycle (includ ing au to-erase)
• Page Write Buffer for up to Eight Bytes
• 1,000,000 Erase/Write Cycles Ensured
• Data Retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC Package
• Available for Extended Temperature Ranges
• Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24LC21A is a 128 x 8-bit
dual-mode Electrically Erasable PROM. This device is
designed for use in applications requiring storage and
serial transmission of configuration and control informa-
tion. Two modes of operation have been implemented:
Transmit-Only mode and Bidirectional mode. Upon
power-up, the devi ce will be in the Transmit-Only mode,
sending a serial bit stream of the memory array from 00h
to 7Fh, clocked by the VCLK pin. A valid high-to-low
transition on the SCL pin will caus e the device to enter
the transition mode, and look for a valid control byte on
the I2C bus. If it detects a valid control byte from the
master, it will switch into Bidirectional mode, with byte
selectable read/write capability of the memory array
using SCL. If no control byte is received, the device will
revert to the Transmit-Only mode after it receives 128
consecutive VCLK pulses while the SCL pin is idle. The
24LC21A is available in a standard 8-pin PDIP and
SOIC pac kage in industrial temperature range.
Package Types
Block Diagram
Pin Function Table
- Industrial (I): -40°Cto +85°C
Name Function
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bidirectional mode)
VCLK Serial Clock (Transmit-Only mode)
VCC +2.5V to 5.5V Power Supply
NC No Connection
PDIP
SOIC
24LC21A
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
Vcc
VCLK
SCL
SDA
24LC21A
NC
NC
NC
Vss
1
2
3
4
8
7
6
5
Vcc
VCLK
SCL
SDA
I/O
Control
Logic
HV Generator
EEPROM
Array
Page Lat ches
YDEC
XDEC
Sense AMP
R/W Control
Memory
Control
Logic
SDA SCL
VCC
VSS
VCLK
1K 2.5V Dual Mode I2C™ Serial EEPROM
DDC is a trademark of the Video Electronics Standards
Association.
I2C is a trademark of Philips Corporation.
24LC21A
DS21160G-page 2 2008 Microchip Technology Inc.
1.0 ELECTRICAL CHARAC TERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS.........................................................................................................................................-0.6V to VCC +1.0V
Storage temperature ...............................................................................................................................-65C to +150C
Ambient temperature with power applied................................................................................................-40C to +125C
ESD protection on all pins 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at those or any other conditions
above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to max imum rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS VCC = +2.5V to 5.5V
Industrial (I): TA =-40C to +85C
Parameter Symbol Min. Max. Units Conditions
SCL and SDA pins:
High-level inpu t voltage
Low-level input voltage VIH
VIL 0.7 VCC
——
0.3 VCC V
V
Input levels on VCLK pin:
High-level inpu t voltage
Low-level input voltage VIH
VIL 2.0
——
0.2 VCC V
VVCC 2.7V (Note)
VCC < 2.7V (Note)
Hysteresis of Schmitt Trigger inputs VHYS .05 VCC —V(Note)
Low-level output voltage VOL1—0.4VIOL = 3 mA, VCC = 2.5V (Note)
Low-level output voltage VOL2—0.6VIOL = 6 mA, VCC = 2.5V
Input leakage current ILI —±1AVIN = 0.1V to VCC
Output lea ka ge current ILO —±1AVOUT = 0.1V to VCC
Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note)
TA = 25C, FCLK = 1 MHz
Operati ng current ICC Write
ICC Read —
—3
1mA
mA VCC = 5.5V
VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —
—30
100 A
AVCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
VCLK = VSS
Note: This parameter is periodically sampled and not 100% tested.
2008 Microchip Technology Inc. DS21160G-page 3
24LC21A
TABLE 1-2: AC CHARACTERISTICS
Parameter Symbol Vcc = 2.5-5.5V
Standard Mode Vcc = 4.5 - 5.5V
Fast Mode Units Remarks
Min. Max. Min. Max.
Clock frequency FCLK —100—400kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time TLOW 4700 — 1300 — ns
SDA and SCL rise time TR— 1000 — 300 ns (Note 1)
SDA and SCL fall time TF— 300 — 300 ns (Note 1)
Start condition hold time THD:STA 4000 — 600 — ns Aft er this period the first clock
puls e is generated
Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
Start condition
Data input hold time THD:DAT 0—0—ns(Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
Stop condition setup time TSU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum TOF — 250 20 + 0.1
CB250 ns (Note 1), CB 100 pF
Input filter spike suppres-
sion (SDA and SCL pins) TSP —50—50ns(Note 3)
Write cycle time TWR — 10 — 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK TVAA — 2000 — 1000 ns
VCLK high time TVHIGH 4000 — 600 — ns
VCLK low time TVLOW 4700 — 1300 — ns
VCLK setup time TVHST 0—0—ns
VCLK hold time TSPVL 4000 — 600 — ns
Mode transition time TVHZ — 1000 — 500 ns
Transmit-only pow e r-up
time TVPU 0—0—ns
Input filter spike suppres-
sion (VCLK pin) TSPV — 100 — 100 ns
Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to Schmitt Trigger inputs which provide noise and
spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parame ter is not tested but en sured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
24LC21A
DS21160G-page 4 2008 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC21A is designed to comply to the DDC
Standard proposed by VESA (Figure 3-3) with the
except ion that it is not Access.b us capable. It operate s
in two modes, the Transmit-Only mode and the
Bidirect ional m ode. T here is a sep ara te 2- wire prot ocol
to support each mode, each having a separate clock
input but sharing a common data line (SDA). The
device enters the Transmit-Only mode upon power-up.
In this mode, the dev ice t ransm its dat a bit s o n the SD A
pin in response to a clock signal on the VCLK pin. The
device will remain in this mode until a valid high-to-low
transition is placed on the SCL input. When a valid
transition on SCL is recognized, the device will switch
into the Bidirectional mode and look for its control byte
to be sent by the master. If it detects its control byte, it
will stay in the Bidirectional mode. Otherwise, it will
revert to the Transmit-Only mode after it sees 128
VCLK pulses.
2.1 Transmit-Only Mode
The dev ic e w il l p ower-up in the Transmit-On ly mo de at
address 00h. This mode supports a unidirectional
2-wire protocol for continuous transmission of the
content s of th e memory a rray. Thi s device re quires th at
it be initialized prior to valid data being sent in the
Transmit-Only mode (Section 2.2 “Initialization Pro-
cedure”). In this mode, data is transmitted on the SDA
pin in 8-bit bytes, with each byte followed by a ninth,
null bit (Fig ure 2-1). The clock so urc e for th e Transmit-
Only mode is provided on the VCLK pin, and a data bit
is output on the rising e dge on this pi n. The eight bi ts in
each byte are transmitted Most Significant bit first.
Each byte within the memory array will be output in
sequence. After address 7Fh in the memory array is
transmitted, the internal Address Pointers will wrap
aroun d to the first memory location (00h) and c ontinue.
The Bidirectional mode Clock (SCL) pin must be held
high for the device to remain in the Transmit-Only
mode.
2.2 Initialization Procedure
After VCC has stabiliz ed, the devic e will be in the T rans-
mit-Only mode. Nine clock cycles on the VCLK pin
must be given to the device for it to perform internal
sychronization. During this period, the SDA pin will be
in a high-impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the Most Significant bit in address
00h. (Figure 2-2).
FIGURE 2-1: TRANSMI T-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
Tvaa Tvaa
Bit 1 (LSB) Null Bit Bit 1 (MSB) Bit 7
TvlowTvhigh
Tvaa Tvaa
Bit 8 Bit 7High-Imp edance for 9 C lock Cycles
Tvpu
12 891011
SCL
SDA
VCLK
Vcc
2008 Microchip Technology Inc. DS21160G-page 5
24LC21A
3.0 BIDIRECTIO NAL MO DE
Before the 24LC21A can be switched into the
Bidirectional mode (Figure 3-1), it must enter the
Transition mode, which is done by applying a valid
high-to-low transition on the Bidirectional mode clock
(SCL). As soon it enters the Transition mode, it looks
for a c ontrol byte ‘1010 000X’ on the I2C™ bus, and
starts to count pulses on VCLK. Any high-to-low transi-
tion on the SCL line will reset the count. If it sees a
pulse count of 128 on VCLK while the SCL line is idle,
it will revert back to the Transmit-Only mode, and
transmit its contents starting with the Most Significant
bit in address 00h. However, if it detects the control
byte on the I2C™ bus, (Figure 3-2) it will switc h to the
in the Bidirectional mode. Once the device has made
the transi tion to t he Bidire ctiona l mode , the onl y way to
switc h the devi ce back to the T r ansm it-On ly mode is to
remove power from the device. The mode transition
process is shown in detail in Figure 3-3.
Once the device has switched into the Bidirectional
mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two-wire
Bidirectional data transmission protocol (I2C™). In this
protoc ol, a dev ice that sends d ata on the bu s is def ined
to be the transmitter, and a device that receives data
from the bus is defined to be th e receiver . The bus must
be controlled by a master device that generates the
Bidi rec t iona l mo d e cl oc k (SC L) , c on t rol s ac cess t o the
bus and generates the Sta r t an d Stop conditio ns, w hil e
the 24LC21A acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated. In the
Bidirectional mode, the 24LC21A only responds to
commands for device ‘1010 000X’.
FIGURE 3-1: MODE TRANSITION WITH RECOVERY TO TRANSMIT-ONLY MODE
FIGURE 3-2: SUCCESSFUL MODE TRANSI TION TO BIDIRECTIONAL MODE
TVHZ
SCL
SDA
VCLK
Transmit-Only
MODE Bidirectional Recovery to Transmit-Only mode
Bit 8
(MSB of data in 00h)
VCLK count = 1 2 3 4 127 128
Transition mode with possibility to return to Transmit-Only mode Bidirectional
permanently
SCL
SDA
VCLK count = 1 2 n 0
VCLK
Transmit-Only
MODE
S1010 0000 ACK
n < 128
24LC21A
DS21160G-page 6 2008 Microchip Technology Inc.
FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA®
Communication
is idle
Is Vsync
present? No
Send EDID continuously
using Vsync as clock
High-to-Low
transition on
SCL? No
Yes
Yes
Stop sending EDID.
Switch to DDC2™ mode.
Display has
transition state
?
optional
Set Vsync counter = 0
Change on
VCLK lines?
SCL, SDA or
No
Yes
High-Low
transition on SCL
?
Reset Vsync counter = 0
No
Yes
Valid
received?
DDC2 address
No
No VCLK
cycle?
Yes
Increment VCLK counter
Yes
Switch back to DDC1™
mode.
DDC2 communication
idle. Display waiting for
address byte.
DDC2B
address
received?
Yes
Receive DDC2B
command
Respond to DDC2B
command
Is display
Access.busTM
Yes
Valid Access.bus
address? No
Yes
See Access.bus
specification to determine
correct procedure.
Yes
No
Yes
No
No
No
The 24LC21A was designed to
Display Power-on
or
DDC Circuit Powered
from +5 volts
or start timer
Reset counter or timer
(if appropriate)
Counter=128 or
timer expired?
High-to-Low
transition on
SCL?
No
Yes
comply to the port ion of flowcha rt inside dash box
Note 1: The base flowchart is copyright 1993, 199 4, 199 5 V id eo Elec tro nic Standard Associati on (VESA) fr om
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.
capable?
2008 Microchip Technology Inc. DS21160G-page 7
24LC21A
3.1 Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le when ever th e clock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 3-4).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2 START DATA T RANSFER (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3 STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of th e high period of the clock signal.
The data on the line must be changed during the low
period of t he cl oc k sig na l. There is one clock puls e per
bit of data.
Each dat a transf er is initiated w ith a S tart condition an d
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwri te does occur it will replace da ta in a firs t-in first-
out (FIFO) fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. Th e mast er device mus t ge nera te a n ex tra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Acknowledge bi t o n th e las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-4: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: Onc e switch ed int o Bidirection al mode , the
24LC21A will remain in that mode until
powe r is r e move d. Re mo vi ng po w er i s t he
only way to reset the 24LC21A into the
Transmit-Only mode.
Note: The 24LC21A does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
(A) (B) (D) (D) (A)(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
SDA
24LC21A
DS21160G-page 8 2008 Microchip Technology Inc.
FIGURE 3-5: BUS TIMING START/STOP
FIGURE 3-6: BUS TIMING DATA
3.1.6 SLAVE ADDR ESS
After generating a Start condition, the bus master
transmi ts t he slav e addre ss co nsis ting of a 7 -bit dev ice
code (1010000) for the 24LC21A.
The eigh th bit of s lave address determin es whether th e
master device wants to read or write to the 24LC21A
(Figure 3-7).
The 24LC21A monitors the bus for its corresponding
slave address continuously. It generates an
Ackno w l edg e bi t if the sl av e ad d r es s was tru e an d i t is
not in a programming mode.
FIGURE 3-7: CONTROL BYTE
ALLOCATION
SCL
SDA
Start Stop
VHYS
TSU:STO
THD:STA
TSU:STA
SCL
SDA
IN
SDA
OUT
TSU:STA
TSP
TAA
TF
TLOW
THIGH
THD:STA
THD:DAT TSU:DAT TSU:STO
TBUF
TAA
TR
Operation Slave Address R/W
Read 1010000 1
Write 1010000 0
R/WA
1010000
Read/Write
Start
Slave Address
2008 Microchip Technology Inc. DS21160G-page 9
24LC21A
4.0 WRITE OPERATION
4.1 Byte Write
Following the start signal from the master, the slave
address (four bits), three zero bits (000) and the R/W
bit which is a logic low are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will
follow after it has gen erated an Ackno wledge bit durin g
the ninth clock cycle. Therefore, the next byte
tran smit ted by the ma ster is the word add res s and wi ll
be written into the Address Pointer of the 24LC21A.
After receiving another acknowledge signal from the
24LC2 1A t he master device wil l transmit the data word
to be written into the addressed memory location. The
24LC21A acknowledges again and the master
generates a Stop condition. This initiates the internal
write cycle, and during this time the 24LC21A will not
generate acknowledge signals (Figure 4-1).
It is required that VCLK be held at a logic high level
during command and data transfer in order to program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
4.2 Page Write
The write control byte, word address and the first data
byte are transmitted to the 24LC21A in the same way
as in a byte write. But instead of generating a Stop
conditi on the m aster tran smit s up to eigh t dat a byt es to
the 24LC21A which are temporarily stored in the on-
chip page buffer and will be written into the memory
after the master has transmitted a Stop condition. After
the rece ipt of each wo rd, the three lower orde r Address
Pointer bits are internally incremented by one. The
higher order five bits of the word address remains
const a nt. If the maste r s hou ld tra nsm it more than eig ht
words prior to generating the Stop condition, the
address counter will roll over and the previously
receive d dat a will be overwri tten. As w ith the by te write
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-3).
It is required that VCLK be held at a logic high level
during command a nd data t ransfer in order t o program
the device. This applies to both byte write and page
write operation. Note, however, that the VCLK is
ignored during the self-timed program operation.
Changing VCLK from high-to-low during the self-timed
program operation will not halt programming of the
device.
Note: Page write opera tions are l imited to wri ting
bytes within a single physical page,
regardless of the nu mb er of bytes actuall y
being written. Physical page boundaries
start at addresses that are integer multi-
ples of t he page buf fer size ( or ‘page size’)
and end at addresses that are integer
multiples of [page size – 1]. If a Page Write
command attempts to write across a
physical page boundary, the result is that
the data wraps around to the beginning of
the current page (overwriting data
previously stored there), instead of being
written to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
24LC21A
DS21160G-page 10 2008 Microchip Technology Inc.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: VCLK WRITE ENABLE TIMING
FIGURE 4-3: PAG E WRITE
Bus Acti vity
Master
SDA Line
Bus Activit y
Control
Byte Word
Address Data S
T
O
P
S
T
A
R
T
A
C
K
SP
A
C
K
A
C
K
VCLK
SCL
SDA
IN
VCLK
THD:STA THD:STO
TVHST TSPVL
SDA Line
Control
Byte Word
Address
S
T
O
P
S
T
A
R
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data n + 1 Data n + 7
Data (n)
P
S
VCLK
Bus Ac tivit y
Master
Bus Acti vity
2008 Microchip Technology Inc. DS21160G-page 11
24LC21A
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be us ed to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
FIGURE 5-1: ACKNOWLEDGE
POLLING FLOW
6.0 WRITE PROTECTION
When using the 24LC21A in the Bidirecti onal mode, the
VCLK pin can be used as a write-protect control pin.
Setting VCLK high allows normal write operations,
while setting VCLK low prevent s w riting to any locatio n
in the array. Connecting the VCLK pin to VSS would
allow the 24LC21A to operate as a serial ROM,
although this configuration would prevent using the
device in the Transmit-Only mode.
Did Device
Acknowledge
(ACK = 0)?
Send
Write Command
Send Stop
Condition to
Initiate Writ e C y c l e
Send Start
Send Control Byte
with R/W = 0
Next
Operation
No
Yes
24LC21A
DS21160G-page 12 2008 Microchip Technology Inc.
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There a re three ba sic types
of read operat ions: current add r ess read, random rea d
and sequential read.
7.1 Current Address Read
The 24LC21A contains an address counter that
maintains the address of the last word accessed,
internally incremented by one. Therefore, if the
previous access (either a read or write operation) was
to address n, the next current address read operation
would ac ce ss d ata from addr ess n + 1. Upon rec ei pt of
the slav e address wit h R/W bit set to one , the 24LC21A
issues an acknow ledge a nd transm its the eight-bit data
word. Th e master w ill n ot acknow ledg e the tra nsfer but
does generate a Stop condition and the 24LC21A
discontinues transmission (Figure 7-1).
FIGURE 7-1: CURRENT ADDRESS
READ
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad ope r atio n, fi rst the w o rd ad dres s must
be set. This is done b y sendi ng the word address to the
24LC21A as part of a write operation. After the word
address is sent, the master genera tes a Start co nditio n
following the acknowledge. This terminates the write
operatio n, but not before the intern al Address Pointer is
set. Then the master issues the control byte again but
with the R/W bit set to a one. The 24LC21A will then
issue an acknowledge and transmits the 8-bit data
word. Th e master w ill n ot acknow ledg e the tra nsfer but
does generate a Stop condition and the 24LC21A
discontinues transmission (Figure 7-2).
7.3 Sequential Read
Sequential reads are initiated in the same way as a
random read except that after the 24LC21A transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24LC21A to transmit the next sequentially
addressed 8-bit word (Figure 7-3).
To provide sequential reads the 24LC21A contains an
internal Address Pointer which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
7.4 Noise Protection
The 24 LC21 A emp loys a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SDA, SCL and VCLK inputs have Schmitt Trigger
and filte r circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
Control
A
C
K
SP
Byte Data n
Bus Ac tivit y
SDA Line
Bus Ac tivit y A
C
K
N
O
Master
10100001
S
T
O
P
S
T
A
R
T
2008 Microchip Technology Inc. DS21160G-page 13
24LC21A
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTI AL READ
Bus Acti vity
Master
SDA Line
BUS Ac tivity
Control
Byte Word
Address Data n
A
C
K
S
T
A
R
T
N
O
S
T
A
RControl
Byte
A
C
K
A
C
K
SS
T
P
S
T
O
P
10100000 00000111
A
C
K
A
C
K
P
Bus Activit y
Master
SDA Line
Bus Activi t y
Control
Byte Data n Data n+1 Data n+2 Data n+X
A
C
K
A
C
K
A
C
K
N
O
A
C
K
S
T
O
P
24LC21A
DS21160G-page 14 2008 Microchip Technology Inc.
8.0 PIN DESCRIPTIONS
8.1 SDA
This p in is use d to transfer addresses and data into and
out of the device , when the dev ice is in th e Bidirectiona l
mode. In the Transmit-Only mode, which only allows
data to be read from the device, dat a is also tr ansferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10 K for 100 kHz, 2 K for 400 kHz).
For normal data transfer i n the Bidirectional mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
8.2 SCL
This pin is the clock input for the Bidirectional mode,
and is used to sync hronize data transfer to and from th e
device. It is also used as the signaling input to switch
the device from the Transmit-Only mode to the
Bidirectional mode. It must remain high for the chip to
continue operation in the Transmit-Only mode.
8.3 VCLK
This pin is the clock input for the Transmit-Only mode
(DDC1). In the T ransmit-Only mode, each bit is clocked
out on the ris ing edg e of this sign al. In the Bidire ctiona l
mode, a high logic level is req uired on this pin to enabl e
write capability.
2008 Microchip Technology Inc. DS21160G-page 15
24LC21A
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
24LC21A
I/PNNN
0145
8-Lead SOIC (3.90 mm) Example:
*Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, ma sk rev#, and assembly code).
XXXXXXXX
XXXXYYWW
NNN
24LC21A
I/SN0145
NNN
Legend: XX...X Part number or par t number code
T Temperature (I, E)
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
Note: For very small packages with no room for the Pb-free JEDEC designator
, the marking will only appear on the outer carton or reel label.
Note: In the eve nt the full Microchi p part number c annot be marked on one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
24LC21A
DS21160G-page 16 2008 Microchip Technology Inc.
!"#$%&"' ()"&'"!&)&#*&&&#
+%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#/!#
'!#&.0
1,21!'!&$& "!**&"&&!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 7,8.
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
&& = =
##44!! -
1!&& = =
"#&"#>#& . - -
##4>#& . <
: 9& -< -?
&& 9 -
9#4!! <
69#>#& ) ?
9*9#>#& ) <
: *+ 1 = = -
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
* ,<1
2008 Microchip Technology Inc. DS21160G-page 17
24LC21A
! ""#$%& !'
!"#$%&"' ()"&'"!&)&#*&&&#
+%&,&!&
- '!!#.#&"#'#%!&"!!#%!&"!!!&$#''!#
'!#&.0
1,2 1!'!&$& "!**&"&&!
.32 %'!("!"*&"&&(%%'&"!!
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
6&! 99..
'!9'&! 7 7: ;
7"')%! 7 <
& 1,
: 8& = =
##44!! = =
&#%%+ =
: >#& . ?1,
##4>#& . -1,
: 9& 1,
,'%@&A =
3&9& 9 =
3&& 9 .3
3& IB = <B
9#4!! =
9#>#& ) - =
#%& DB = B
#%&1&&' EB = B
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
* ,1
24LC21A
DS21160G-page 18 2008 Microchip Technology Inc.
! ""#$%& !'
3&'!&"&4#*!(!!&4%&&#&
&&255***''54
2008 Microchip Technology Inc. DS21160G-page 19
24LC21A
APPENDIX A: REVISION HISTORY
Revision F
Corrections to Section 1.0, Electrical Characteristics.
Revision G (07/2008)
Features Section - Deleted Commercial Temp and
added Pb-free; Revised Description; Table 1-1,
Delete d C ommerc ia l Temp; Ad ded Pac k age Dr awi ngs :
Revised Product ID section.
24LC21A
DS21160G-page 20 2008 Microchip Technology Inc.
NOTES:
2005 Microchip Technology Inc. DS21160G-page 21
24LC21A
THE MICROCHIP WEB SITE
Microc hip pro vides onl ine s upport v ia our W WW site at
www.microc hi p.c om . Thi s web site is used as a mean s
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
•Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
•General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online dis cu ss io n gr oups, Microchip consul tant
program member listing
•Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specif ied produ ct family or develo pment tool of interes t.
To register, access the Microchip web site at
www.microchip.com, click on Customer Change
Notification and follow the registration instructions.
CUSTOMER SUPP ORT
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Development Systems Information Line
Customers should contact their distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is a vailable through the web si te
at: http://support.microchip.com
24LC21A
DS21160G-page 22 2005 Microchip Technology Inc.
READER RESP ONSE
It is ou r intention to pro vi de you with the best documentation po ss ib le to ensure succes sfu l u se of y ou r M ic roc hip pro d-
uct. If you wi sh to prov ide you r comment s on org aniza tion, clar ity, su bject m atter , and ways in wh ich our doc umenta tion
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21160G24LC21A
1. What are the best feat ures of this docu ment?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you im prove this document?
2008 Microchip Technology Inc. DS21160G-page 23
24LC21A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device: 24LC21A Dual Mode Serial EEPROM
24LC21AT Dual Mode Serial EEPROM (Tape and Reel)
Temperature
Range: I -40C to +85C
Package: P = Plastic DIP (300 mil Bod y), 8-l e ad
SN = Plastic SOIC (3.90 mm Body), 8-lead
24LC21A
DS21160G-page 24 2008 Microchip Technology Inc.
NOTES:
2008 Microchip Technology Inc. DS21160G-page 25
Information contained in this publication regarding device
applications a nd t he like is pro vid ed only for your c onvenience
and may be su perseded by u pda t es . It is y our responsibil ity to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICm icro,
PICSTART, rfPIC and SmartShunt are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Linear Active Thermistor, MXDEV, MX LAB ,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Prog ra m ming, IC SP, ICE PIC, Min d i , MiW i , MPAS M , M PLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail , PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporat ed in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of it s kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code ho pping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21160G-page 26 2008 Microchip Technology Inc.
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