ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 1/15
Revision History :
Revision 1.0 (Jul. 4, 2007)
- Original
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 2/15
PSRAM 16-Mbit (1M x 16)
Pseudo Static RAM
Features
‧Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power— Typical active current: 3 mA @ f =
1 MHz— Typical active current: 18 mA @ f = fmax
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Deep Sleep Mode
• Offered in a Lead-Free 48-ball BGA package
• Operating Temperature: –40°C to +85°C
Functional Description[1]
The M24L16161ZA is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for portable applications such as cellular
telephones. The device can be put into standby mode when
deselected ( OE HIGH or both BHE and BLE are HIGH).
The input/output pins (I/O0 through I/O15) are placed in a
high-impedance state when: deselected ( OE HIGH), outputs
are disabled ( OE HIGH), both Byte High Enable and Byte
Low Enable are disabled ( BHE ,BLE HIGH), or during a
write operation ( CE LOW and WE LOW).
To write to the device, take Chip Enable ( CE LOW) and
Write Enable ( WE ) input LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O0 through I/O7), is written
into the location specified on the address pins (A0 through
A19). If Byte High Enable ( BHE ) is LOW, then data from I/O
pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
To read from the device, take Chip Enables ( CE LOW) and
Output Enable ( OE ) LOW while forcing the Write Enable
(WE ) HIGH. If Byte Low Enable ( BLE ) is LOW, then data
from the memory location specified by the address pins will
appear on I/O0 to I/O7. If Byte High Enable ( BHE ) is LOW,
then data from memory will appear on I/O8 to I/O15. Refer to
the Truth Table for a complete description of read and write
modes. To enable Deep Sleep Mode, drive ZZ LOW. See
the Truth Table for a complete description of Read, Write, and
Deep Sleep mode.
Logic Block Diagram
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 3/15
Pin Configuration[2, 3]
48-ball VFBGA
Top View
Product Portfolio Product
Power Dissipation
Operating ICC(mA)
VCC Range (V)
f = 1MHz f = fmax Standby ISB2(µA)
Product
Min. Typ.[4] Max
Speed(ns)
.Typ.[4] Max. .Typ.[4] Max .Typ. [4] Max
M24L16161ZA 2.2 3.0 3.6 70 3 5 18 25 55 70
Low-Power Modes
At power-up, all four sections of the die are activated and
thePSRAM enters into its default state of full memory size
andrefresh space. This device provides three different
Low-Power Modes.
1.Reduced Memory Size Operation
2.Partial Array Refresh
3.Deep Sleep Mode
4.Temperature Controlled Refresh
Reduced Memory Size Operation
In this mode, the 16-Mb PSRAM can be operated as a
12-Mbit,8-Mbit, and 4-Mbit memory block. Refer to “Variable
Address Space Register (VAR)” on page4 for the protocol to
turn on/off sections of the memory. The device remains in
RMS mode until changes to the Variable Address Space
register are made to revert back to a complete 16-Mbit
PSRAM.
Partial Array Refresh
The Partial Array Refresh mode allows customers to turn off
sections of the memory block in Standby mode (with ZZ tied
LOW) to reduce standby current. In this mode the PSRAM will
only refresh certain portions of the memory in Standby Mode,
as configured by the user through the settings in the Variable
Address Register.
Once ZZ returns HIGH in this mode, the PSRAM goes back
to operating in full address refresh. Refer to “Variable Address
Space Register (VAR)” on page4 for the protocol to turn off
sections of the memory in Standby mode. If the VAR register
is not updated after power-up, the PSRAM will be in its default
state. In the default state the whole memory array will be
refreshed in Standby Mode. The 16-Mbit is divided into four
4-Mbit sections allowing certain sections to be active (i.e.,
refreshed).
Deep Sleep Mode
In this mode, the data integrity in the PSRAM is not
guaranteed. This mode can be used to lower the power
consumption of the PSRAM in an application. This mode can
be enabled and disabled through VAR similar to the RMS and
PAR mode. Deep Sleep Mode is activated by driving ZZ
LOW. The device stays in the deep sleep mode until ZZ is
driven HIGH.
Notes:
2. Ball H6 and E3 can be used to upgrade to a 32M and a 64M density respectively.
3. NC “no connect” - not connected internally to the die.
4.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC (typ)
and TA = 25°C. Tested initially and after any design changes that may affect the parameter.
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 4/15
Variable Address Mode Register (VAR) Update[5, 6]
Deep Sleep Mode—Entry/Exit[7]
VAR Update and Deep Sleep Mode Timing[5, 6]
Parameter Description Min. Max. Unit
tZZWE ZZ LOW to Write Start 1 µs
tCDR Chip deselect to ZZ LOW 0 ns
tR[7] Operation Recovery Time (Deep Sleep Mode only) 200 µs
tZZMIN Deep Sleep Mode Time 8 µs
Notes:
5. OE and the data pins are in a don’t care state while the device is in variable address mode.
6. All other timing parameters are as shown in the data sheets.
7. tR applies only in the deep sleep mode.
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 5/15
Variable Address Space Register (VAR)
Variable Address Space—Address Patterns
Partial Array Refresh Mode (A3=0, A4=1)
A2 A1, A0 Refresh Section Address Size Density
0 1 1 1/4th of the array 00000h - 3FFFFh (A19 = A18 = 0) 256K x 16 4M
0 1 0 1/2th of the array 00000h - 7FFFFh (A19 = 0) 512K x 16 8M
0 0 1 3/4th of the array 00000h - BFFFFh (A19:A18 not equal to 11) 768K x 16 12M
1 1 1 1/4th of the array C0000h - FFFFFh (A19 = A18 = 1) 256K x 16 4M
1 1 0 1/2th of the array 80000h - FFFFFh (A19 = 1) 512K x 16 8M
1 0 1 3/4th of the array 40000h - FFFFFh (A19:A18 not equal to 00) 786K x 16 12M
Reduced Memory Size Mode (A3=1, A4=1)
0 1 1 1/4th of the array 00000h - 3FFFFh (A19 = A18= 0) 256K x 16 4M
0 1 0 1/2th of the array 00000h - 7FFFFh (A19 = 0) 512K x 16 8M
0 0 1 3/4th of the array 00000h - BFFFFh (A19:A18 not equal to 1 1) 768K x 16 12M
0 0 0 Full array 00000h - FFFFFh (Default) 1M x 16 16M
1 1 1 1/4th of the array C0000h - FFFFFh (A19 = A18 = 1) 256K x 16 4M
1 1 0 1/2th of the array 80000h - FFFFFh (A19 = 1) 512K x 16 8M
1 0 1 3/4th of the array 40000h - FFFFFh (A19:A18 not equal to 00) 768K x 16 12M
1 0 0 Full array 00000h - FFFFFh (Default) 1M x 16 16M
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 6/15
Power-up Characteristics
The initialization sequence is shown in the figure below. Chip
Select ( CE ) should be HIGH for at least 200 µs after VCC
has reached a stable value. No access must be attempted
during this period of 200 µs. ZZ is high (H) for the duration
of power-up.
Parameter Description Min. Max. Unit
TPU Chip Enable Low After Stable VCC 200 µs
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 7/15
Maximum Ratings
(Above which the useful life may be impaired. For user
guide-lines, not tested.)Storage
Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to
Ground Potential..............................–0.3V to VCCMAX + 0.3V
DC Voltage Applied to Outputs
in High Z State[8, 9, 10]......................–0.3V to VCCMAX + 0.3V
DC Input Voltage[8, 9, 10]..................–0.3V to VCCMAX + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)Latch-Up
Current....................................................> 200 mA
Operating Range
Range Ambient
Temperature (TA) VCC
Industrial −40°C to +85°C 2.2V to 3.6V
DC Electrical Characteristics (Over the Operating Range) [8, 9, 10]
-70
Parameter Description Test Conditions Min. Typ.[4] Max. Unit
VCC Supply Voltage 2.2 3.0 3.6 V
VOH Output HIGH
Voltage
IOH = −0.1 mA
VCC = 2.2V to 3.6V VCC-0.2 V
VOL Output LOW
Voltage IOL = 0.1 mA, VCC = 2.2V to 3.6V 0.2 V
VIH Input HIGH
Voltage VCC = 2.2V to 3.6V 0.8* VCC V
CC+0.3V V
VIL Input LOW Voltage VCC = 2.2V to 3.6V -0.3 0.2* VCC V
IIX Input Leakage
Current GND ≤VIN < VCC -1 +1
µA
IOZ Output Leakage
Current GND ≤ V
OUT ≤ V
CC -1 +1
µA
f = fMAX = 1/tRC
VCC= VCCmax
IOUT = 0mA
CMOS levels
18 25
ICC VCC Operating
Supply Current
f = 1 MHz 3 5
mA
ISB1
Automatic CE
Power-Down
Current
—CMOS Inputs
CE > VCC − 0.2V, VIN > VCC − 0.2V, VIN <
0.2V, f = fMAX (Address and Data Only), f
= 0 ( OE , WE , BHE and BLE ),
VCC=3.60V, ZZ ≥ V
CC – 0.2V
55 70 µA
ISB2
Automatic CE
Power-Down
Current
—CMOS Inputs
CE > VCC−0.2V, VIN > VCC − 0.2V or VIN
< 0.2V, f = 0, VCC = VCCMAX,
ZZ ≥ V
CC – 0.2V
55 70 µA
IZZ Deep Sleep
Current
VCC = VCCMAX, ZZ < 0.2V, CE = HIGH or
BHE and BLE = HIGH
10 µA
Capacitance[11]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance
TA = 25°C, f = 1 MHz
VCC = VCC(typ) 8 pF
Notes:
8. VIL(MIN) = –0.5V for pulse durations less than 20 ns.
9.VIH(Max) = VCC + 0.5V for pulse durations less than 20 ns.
10.Overshoot and undershoot specifications are characterized and are not 100% tested.
11.Tested initially and after any design or process changes that may affect these parameters..
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 8/15
Thermal Resistance[11]
Parameter Description Test Conditions VFBGA Unit
ΘJA Thermal Resistance
(Junction to Ambient) 56 °C/W
ΘJC Thermal Resistance
(Junction to Case)
Test conditions follow standard test methods
and procedures for measuring thermal
impedence, per EIA/JESD51. 11 °C/W
Parameters 3.0V VCC Unit
R1 26000 Ω
R2 26000 Ω
RTH 13000 Ω
VTH 1.50 V
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 9/15
Switching Characteristics Over the Operating Range [12, 13, 14, 15, 18]
-70
Parameter Description Min. Max.
Unit
Read Cycle
tRC[17] Read Cycle Time 70 40000 ns
tCD Chip Deselect Time
CE , BLE /BHE High Pulse Time 15
ns
tAA Address to Data Valid 70 ns
tOHA Data Hold from Address Change 5 ns
tACE CE LOW to Data Valid 70
ns
tDOE OE LOW to Data Valid 35
ns
tLZOE OE LOW to Low Z[13, 14, 16] 5
ns
tHZOE OE HIGH to High Z[13, 14, 16] 25
ns
tLZCE CE LOW to Low Z[13, 14, 16] 10
ns
tHZCE CE HIGH to High Z[13, 14, 16] 25
ns
tDBE BLE /BHE LOW to Data Valid 70
ns
tLZBE BLE /BHE LOW to Low Z[13, 14, 16] 5
ns
tHZBE BLE /BHE HIGH to High Z[13, 14, 16] 25
ns
Write Cycle[15]
tWC Write Cycle Time 70 40000 ns
tSCE CE LOW to Write End 60 ns
tAW Address Set-Up to Write End 60 ns
tCD Chip Deselect Time CE , BLE /BHE High Pulse
Time 15 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-Up to Write Start 0 ns
tPWE WE Pulse Width 50 ns
tBW BLE /BHE LOW to Write End 60 ns
tSD Data Set-Up to Write End 25 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[13, 14, 16] 25 ns
tLZWE WE HIGH to Low-Z[13, 14, 16] 10 ns
Notes:
12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference
levels of VCC/2, input pulse levels of 0V to VCC, and output loading of the specified IOL/IOH as shown in the “AC Test Loads and
Waveforms” section.
13. At any given temperature and voltage conditions tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and
tHZWE is less than tLZWE for any given device. All low-Z parameters will be measured with a load capacitance of 30 pF (3V).
14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
15. The internal Write time of the memory is defined by the overlap of WE , CE = VIL, BHE and/or BLE = VIL. All signals
must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up
and hold timing should be referenced to the edge of the signal that terminates the write.
16. High-Z and Low-Z parameters are characterized and are not 100% tested.
17. If invalid address signals shorter than min. tRC are continuously repeated for 40 µs, the device needs a normal read timing
(tRC) or needs to enter standby state at least once in every 40 µs.18.In order to achieve 70-ns performance, the read access
must be CE controlled. That is, the addresses must be stable prior to CE going active.
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 10/15
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[20, 21]
Read Cycle 2 (OE Controlled) [19, 21]
Notes:
19. Whenever CE , BHE /BLE are taken inactive, they must remain inactive for a minimum of 15 ns.
20. Device is continuously selected. OE , CE = VIL.
21. WE is HIGH for Read Cycle.
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 11/15
Switching Waveforms (continued)
Notes:
22.Data I/O is high-Impedance if OE > VIH.
23.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied.
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 12/15
Switching Waveforms (continued)
Write Cycle 2 (CE Controlled) [15, 16, 19, 22, 23]
Write Cycle 3 (WE Controlled, O
E
LOW)[19, 23]
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 13/15
Switching Waveforms (continued)
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[15, 19, 22, 23]
Truth Table[24, 25]
ZZ CE WE OE BHE BLE Inputs/Outputs Mode Power
H H X X X X High Z Deselect/Power-Down Standby (ISB)
H X X X H H High Z Deselect/Power-Down Standby (ISB)
H L X X H H High Z Deselect/Power-Down Standby (ISB)
H L H L L L Data Out (I/O0–I/O15) Read Active (ICC)
H L H L H L
Data Out (I/O0–I/O7);
(I/O8–I/O15) in High Z Read Active (ICC)
H L H L L H
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z Read Active (ICC)
H L H H L L High Z Output Disabled Active (ICC)
H L H H H L High Z Output Disabled Active (ICC)
H L H H L H High Z Output Disabled Active (ICC)
H L L X L L Data In (I/O0–I/O15) Write (Upper Byte and Lower
Byte) Active (ICC)
L L L X H L
Data In (I/O0–I/O7);
(I/O8–I/O15) in High Z Write (Lower Byte Only) Active (ICC)
L L L X L H
Data Out (I/O8–I/O15);
(I/O0–I/O7) in High Z Write (Upper Byte Only) Active (ICC)
L L L X L L Data In (A0–A4) Write (Variable Address Mode
Register) Active (ICC)
L H X X X X High Z Deep Power-down/PAR Deep Sleep (IZZ)/Stand
b
Notes:
24.H = Logic HIGH, L = Logic LOW, X = Don’t Care.
25.During ZZ = L and CE = H, Mode depends on how the VAR is set up either in PAR or Deep Sleep Modes.
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 14/15
Ordering Information
Speed (ns) Ordering Code Packag e Type Operating Range
70 M24L16161ZA -70BIG 48-ball Very Fine Pitch BGA (6 x 8 x 1 mm) (Pb-Free) Industrial
Package Diagrams
ESMT M24L16161ZA
Elite Semiconductor Memory Technology Inc. Publication Date : Jul. 2007
Revision : 1.0 15/15
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time of publication. ESMT assumes no responsibility for any error in this
document, and reserves the right to change the products or specification in
this document without notice.
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infringement of patents, copyrights, or other intellectual property rights of third
parties which may result from its use. No license, either express , implied or
otherwise, is granted under any patents, copyrights or other intellectual
property rights of ESMT or others.
Any semiconductor devices may have inherently a certain rate of failure. To
minimize risks associated with customer's application, adequate design and
operating safeguards against injury, damage, or loss from such failure, should
be provided by the customer when making application designs.
ESMT's products are not authorized for use in critical applications such as,
but not limited to, life support devices or system, where failure or abnormal
operation may directly affect human lives or cause physical injury or property
damage. If products described here are to be used for such kinds of
application, purchaser must do its own quality assurance testing appropriate
to such applications.
