bq29200 bq29209 www.ti.com SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 Voltage Protection with Automatic Cell Balance for 2-Series Cell Li-Ion Batteries Check for Samples: bq29200 , bq29209 FEATURES 1 * * * * * * 2-Series Cell Secondary Protection Automatic Cell Imbalance Correction with External Enable Control - 30 mV Enable, 0 mV Disable Thresholds Typical External Capacitor-Controlled Delay Timer External Resistor-Controlled Cell Balance Current Low Power Consumption ICC < 3 A Typical (VCELL(ALL) < VPROTECT) Internal Cell Balancing Handles Current up to 15 mA * * * * External Cell Balancing Mode Supported High-Accuracy Overvoltage Protection: - 25 mV with TA = 0C to 60C Fixed Overvoltage Protection Thresholds: 4.30 V, 4.35 V Small 8L DRB Package APPLICATIONS * 2nd Level Protection in Li-Ion Battery Packs - Netbook Computers - Power Tools - Portable Equipment and Instrumentation - Battery Backup Systems DESCRIPTION The bq2920x device is a secondary overvoltage protection IC for 2-series cell lithium-ion battery packs that incorporates a high-accuracy precision overvoltage detection circuit and automatic cell imbalance correction. The voltage of each cell in a 2-series cell battery pack is compared to an internal reference voltage. If either cell reaches an overvoltage condition, the bq2920x device starts a timer that provides a delay proportional to the capacitance on the CD pin. Upon expiration of the internal timer, the OUT pin changes from low to high state. If enabled, the bq2920x performs automatic cell imbalance correction where the two cells are automatically corrected for voltage imbalance by loading the cell with the higher charge voltage with a small balancing current. When the cells are measured to be equal within nominally 0 mV, the load current is removed. It will be re-applied if the imbalance exceeds nominally 30 mV. The cell mismatch correction circuitry is enabled by pulling the CB_EN pin low, and disabled when CB_EN is pulled to VDD or greater than 2.2 V. If the internal cell balancing current of up to 15 mA is insufficient, the bq2920x may be configured via external circuitry to support much higher external cell balancing current. VC2 1 8 VC1 2 7 VDD VC1_CB 3 CD 4 OUT 6 CB_EN _ 5 GND 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010, Texas Instruments Incorporated bq29200 bq29209 SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PART NUMBER -40C to +110C PACKAGE BQ29200 PACKAGE DESIGNATOR PACKAGE MARKING OVP DRB 200 209 QFN-8 BQ29209 ORDERING INFORMATION TAPE AND REEL (LARGE) TAPE AND REEL (SMALL) 4.35 V BQ29200DRBR BQ29209DRBT 4.30 V BQ29209DRBR BQ29209DRBT THERMAL INFORMATION bq2920x THERMAL METRIC (1) DRB UNITS 8 PINS Junction-to-ambient thermal resistance (2) qJA 50.5 (3) qJC(top) Junction-to-case(top) thermal resistance qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter (3) (4) (5) (6) (7) 19.3 (5) Junction-to-case(bottom) thermal resistance qJC(bottom) (1) (2) 25.1 (4) 0.7 (6) C/W 18.9 (7) 5.2 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. PIN FUNCTIONS 2 PIN NAME NO. CB_EN 6 Cell balance enable DESCRIPTION CD 4 Connection to external capacitor for programmable delay time GND 5 Ground pin OUT 8 Output VC1 2 Sense voltage input for bottom cell VC1_CB 3 Cell balance input for bottom cell VC2 1 Sense voltage input for top cell VDD 7 Power supply Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 bq29200 bq29209 www.ti.com SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 FUNCTIONAL BLOCK DIAGRAM VDD 5 V LDO and POR VC2 CTRL CB2_EN + CB Logic VC1 Hys. - ICD(CHG) = 150 nA CB1_EN + VC1_CB OUT - GND CB_EN CD 0.1 F Figure 1. Block Diagram ABSOLUTE MAXIMUM RATINGS Over-operating free-air temperature range (unless otherwise noted) (1) VALUE/UNIT Supply voltage range, VMAX Input voltage range, VIN Output voltage range, VOUT VDD-GND -0.3 V to 16 V VC2-GND, VC1-GND -0.3 V to 16 V VC2-VC1, CD-GND -0.3 V to 8 V CB_EN-GND -0.3 V to 16 V OUT-GND -0.3 V to 16 V Continuous total power dissipation, PTOT See package dissipation rating Storage temperature range, TSTG -65C to 150C Lead temperature (soldering, 10 s), TSOLDER (1) 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VDD MAX UNIT 4 NOM 10 V 0 5 V Input voltage range VC2-VC1, VC1-GND Delay time capacitance, td(CD) CCD (See Figure 8.) Voltage monitor filter resistance RIN (See Figure 8.) 100 1K Voltage monitor filter capacitance CIN (See Figure 8.) 0.01 0.1 F Supply voltage filter resistance RVD (See Figure 8.) Supply voltage filter capacitance CVD (See Figure 8.) Cell balance resistance RCB (See Figure 8 and PROTECTION (OUT) TIMING.) Operating ambient temperature range, TA 0.1 100 F 1K 0.1 F 100 4.7K -40 110 C Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 3 bq29200 bq29209 SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS Typical values stated where TA = 25C and VDD = 7.2 V. Min/Max values stated where TA = -40C to 110C and VDD = 4 V to 10 V (unless otherwise noted). PARAMETER VPROTECT Overvoltage bq29209 detection bq29200 voltage VHYS Overvoltage detection hysteresis VOA Overvoltage detection accuracy VOA_DRIFT Overvoltage threshold temperature drift Overvoltage delay time scale factor XDELAY TEST CONDITION MIN NOM MAX UNIT 4.30 V 4.35 200 300 400 mV mV TA = 25C -10 10 TA = 0C to 60C -0.4 0.4 TA = -40C to 110C -0.6 0.6 TA = 0C to 60C Note: Does not include external capacitor variation. 6.0 9.0 12.0 TA = -40C to 110C Note: Does not include external capacitor variation. 5.5 9.0 13.5 mV/C s/F Overvoltage delay time scale factor in Customer Test Mode 0.08 s/F ICD(CHG) Overvoltage detection charging current 150 nA ICD(DSG) Overvoltage detection discharging current 60 A VCD Overvoltage detection external capacitor comparator threshold 1.2 V ICC Supply current XDELAY_CTM (1) (VC2-VC1) = (VC1-GND) = 3.5 V (See Figure 4.) (VC2-VC1) or (VC1-GND) > VPROTECT, VDD = 10 V, IOH = 0 (VC2-VC1) or (VC1-GND) = VPROTECT, VDD = VPROTECT, IOH = -100 A, TA = 0C to 60C VOUT OUT pin drive voltage 3.0 6.0 A 6 8.25 9.5 V 1.75 2.5 (VC2-VC1) and (VC1-GND) < VPROTECT , IOL = 100 A, TA = 25C (VC2-VC1) and (VC1-GND) < VPROTECT , IOL = 0 A, TA = 25C 0 VC2 = VC1 = VDD = 4 V, IOL = 100 A IOH High-level output current OUT = 1.75 V, (VC2-VC1) or (VC1-GND) = VPROTECT, VDD = VPROTECT to 10 V, TA = 0C to 60C -100 IOL Low-level output current OUT = 0.05 V, (VC2-VC1) or (VC1-GND) < VPROTECT, VDD = VPROTECT to 10 V, TA = 0C to 60C 30 IOH_ZV High-level short-circuit output current OUT = 0 V, (VC2-VC1) = (VC1-GND) = VPROTECT VDD = 4 to 10 V IIN Input current at VCx pins Measured at VC1, (VC2-VC1) = (VC1-GND) = 3.5 V, TA = 0C to 60C (See Figure 4.) V 200 mV 10 mV 200 mV A -0.2 Measured at VC2, (VC2-VC1) = (VC1-GND) = 3.5 V, TA = 0C to 60C (See Figure 4.) 85 A -8.0 mA 0.2 A 2.5 A VMM_DET_ON Cell mismatch detection threshold for turning ON (VC2-VC1) versus (VC1-GND) and vice-versa when cell balancing is enabled. VC2 = VDD = 7.6 V 17 30 45 mV VMM_DET_OFF Cell mismatch detection threshold for turning OFF Delta between (VC2-VC1) and (VC1-GND) when cell balancing is disabled. VC2 = VDD = 7.6 V -9 0 9 mV VCB_EN_ON Cell balance enable ON threshold Active LOW pin at CB_EN 1 V VCB_EN_OFF Cell balance enable OFF threshold Active HIGH at CB_EN ICB_EN Cell balance enable ON input current CB_EN = GND (See Figure 5.) (1) 4 2.2 V 0.2 A Specified by design. Not 100% tested in production. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 bq29200 bq29209 www.ti.com SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 RECOMMENDED CELL BALANCING CONFIGURATIONS Typical values stated where TA = 25C and (VC2-VC1), (VC1-GND) = 3.8 V. Min/Max values stated where TA = -40C to 110C, VDD = 4 V to 10 V, and (VC2-VC1), (VC1-GND) = 3.0 V to 4.2 V. All values assume recommended supply voltage filter resistance RVD of 100 and 5% accurate or better cell balance resistor RCB. PARAMETER ICB TEST CONDITION Cell balance input current MIN NOM MAX RCB = 4700 0.5 0.75 1 RCB = 2200 1 1.5 2 RCB = 910 2 3 4 RCB = 560 3 4.5 6 RCB = 360 3.5 6 8.5 RCB = 240 4 7.5 11 RCB = 120 5 10 15 UNIT mA The cell balancing current may be calculated as follows: Cell 1 (VC1-GND): ICB1 = VC1 RCB Cell 2 (VC2-VC1): ICB2 = (VC2 - VC1) (RCB + R VD ) TYPICAL CHARACTERISTICS ICD CHARGE CURRENT vs TEMPERATURE ICD DISCHARGE CURRENT vs TEMPERATURE -80 80 -90 75 -100 ICD Discharge Current (A) ICD Charge Current (nA) 70 -110 -120 -130 -140 -150 65 60 55 50 -160 45 -170 -180 -40 -20 0 20 40 60 Temperature (C) 80 40 -40 100 -20 0 20 40 60 Temperature (C) 80 100 G001 Figure 2. ICD Charge Current G002 Figure 3. ICD Discharge Current Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 5 bq29200 bq29209 SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 www.ti.com TEST CONDITIONS IIN IIN 1 VC2 OUT 8 2 VC1 VDD 7 3 VC1_CB ICC CB_EN 6 4 CD GND 5 Figure 4. ICC, IIN Measurement VCELL ICB VCELLVCB 1 VC2 OUT 8 2 VC1 VDD 7 3 VC1_CB ICB CB_EN 6 4 CD ICB_EN GND 5 Figure 5. ICB Measurement PROTECTION (OUT) TIMING Sizing the external capacitor is based on the desired delay time as follows: CCD = td XDELAY Where td is the desired delay time and XDELAY is the overvoltage delay time scale factor, expressed in seconds per microFarad. XDELAY is nominally 9.0 s/F. For example, if a nominal delay of 3 seconds is desired, use a CCD capacitor that is 3 s / 9.0 s/F = 0.33 F. The delay time is calculated as follows: t d = CCD XDELAY If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the internal current source is disabled and an internal discharge block is employed to discharge the external capacitor down to 0 V. In this instance, the OUT pin remains in a low state. Cell Voltage > VPROTECT When one or both of the cell voltages rises above VPROTECT, the internal comparator is tripped, and the delay begins to count to td. If the input remains above VPROTECT for the duration of td, the bq2920x output changes from a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V when IOH = 0 mA. The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed. 6 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 bq29200 bq29209 www.ti.com SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 VPROTECT VPROTECT - VHYS Cell Voltage VC2-VC1, VC1-GND td L H OUT Figure 6. Timing for Overvoltage Sensing CELL CONNECTION SEQUENCE NOTE Before connecting the cells, propagate the overvoltage delay timing capacitor, CCD. The recommended cell connection sequence begins from the bottom of the stack, as follows: 1. GND 2. VC1 3. VC2 While not advised, connecting the cells in a sequence other than that described above does not result in errant activity on the OUT pin. For example: 1. GND 2. VC2 or VC1 3. Remaining VCx pin CELL BALANCE ENABLE CONTROL To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance Enable Control pin at lower State of Charge (SOC) levels. CELL IMBALANCE AUTO-DETECTION (VIA CELL VOLTAGE) The VMM_DET_ON and VMM_DET_OFF specifications are calibrated where VDD = VC2 = 7.6 V and VC1 = 3.8 V. The recommended range of cell balancing is VC2 and VDD between 6.0 V and 8.4 V, and VC1 between 3.0 V and 4.2 V. Below VDD = 6.0 V, it is recommended to pull CB_EN high to disable the cell balancing function. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 7 bq29200 bq29209 SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 www.ti.com 111% 100% 79% VC2 8.4 V 7.6 V 6V Figure 7. VMM_DET_ON and VMM_DET_OFF Threshold BATTERY CONNECTION Figure 8 shows the configuration for the 2-series cell battery connection. RVD CELL2 RIN CIN RIN CIN 1 VC2 OUT 8 2 VC1 VDD 7 3 VC1_CB CELL1 4 CD RCB CB_EN 6 GND 5 CVD CCD Figure 8. 2-Series Cell Configuration EXTERNAL CELL BALANCING Higher cell balancing currents can be supported by means of a simple external network, as shown in Figure 9. RVD CELL2 RIN CIN RIN CIN 1 VC2 OUT 8 2 VC1 VDD 7 3 VC1_CB CELL1 RCB_EXT Q1 4 CD RCLAMP CB_EN 6 GND 5 CVD CCD Q2 Figure 9. External Cell Balancing Configuration RCLAMP ensures that both Q1 and Q2 remain off when balancing is disabled, and should be sized above 2 k to prevent excessive internal device current when the balancing network is activated. RCB_EXT determines the value of the balancing current, and is dependent on the voltage of the balanced cell, as follows: 8 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 bq29200 bq29209 www.ti.com SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 Ibal = VCELL RCB _EXT CUSTOMER TEST MODE Customer Test Mode (CTM) helps to greatly reduce the overvoltage detection delay time and enable quicker customer production testing. This mode is intended for quick-pass board-level verification tests, and, as such, individual cell overvoltage levels may deviate slightly from the specifications (VPROTECT, VOA). If accurate overvoltage thresholds are to be tested, use the standard delay settings that are intended for normal use. To enter CTM, VDD should be set to approximately 9.5 V higher than VC2. When CTM is entered, the device switches from the normal overvoltage delay time scale factor, XDELAY, to a significantly reduced factor of approximately 0.08, thereby reducing the delay time during an overvoltage condition. CAUTION Avoid exceeding any Absolute Maximum Voltages on any pins when placing the part into CTM. Also, avoid exceeding Absolute Maximum Voltages for the individual cell voltages (VC1-GND) and (VC2-VC1). Stressing the pins beyond the rated limits may cause permanent damage to the device. To exit CTM, power off the device and then power it back on. 15 V VDD Test Mode Entered VC2 > 10 ms 4.5 V (VC2-VC1) or (VC1-GND) VPROTECT VPROTECT -VHYST 4V OUT <<td Figure 10. Voltage Test Limits Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 9 bq29200 bq29209 SLUSA52A - SEPTEMBER 2010 - REVISED NOVEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (June 2010) to Revision A Page * Changed values in XDELAY and XDELAY_CTM electrical characteristics ..................................................................................... 4 * Changed specifications for VOUT ........................................................................................................................................... 4 * Changed test conditions for VOUT, IOH, and IOL ..................................................................................................................... 4 * Added VMM_DET_ON: VC2 = VDD = 7.6 V ............................................................................................................................... 4 * Changed VMM_DET_OFF: From VDD - VC2 - 7.6 V to VC2 = VDD = 7.6 V ............................................................................ 4 * Changed content in Recommended Cell Balancing Configurations section ........................................................................ 5 * Added ICD Charge Current figure .......................................................................................................................................... 5 * Added ICD Discharge Current figure ...................................................................................................................................... 5 * Changed XDELAY from nominally 8.0 s/F to nominally 9.0 s/F ........................................................................................... 6 * Changed Timing for Overvoltage Sensing figure .................................................................................................................. 6 * Added Cell Imbalance Auto-Detection (Via Cell Voltage) section ........................................................................................ 7 * Added External Cell Balancing section ................................................................................................................................. 8 * Changed VDD value in Customer Test Mode from 8.5 V to 9.5 V ....................................................................................... 9 * Changed the Voltage Test Limits figure ............................................................................................................................... 9 10 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): bq29200 bq29209 PACKAGE OPTION ADDENDUM www.ti.com 6-Oct-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) BQ29200DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ29200DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ29209DRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR BQ29209DRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing BQ29200DRBR SON DRB 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ29200DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ29209DRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 BQ29209DRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ29200DRBR SON DRB 8 3000 367.0 367.0 35.0 BQ29200DRBT SON DRB 8 250 210.0 185.0 35.0 BQ29209DRBR SON DRB 8 3000 367.0 367.0 35.0 BQ29209DRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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