 
  
FEATURES APPLICATIONS
DESCRIPTION
Lch In
Rch In Analog Front-End Delta-Sigma
Modulator
Digital
Decimation
Filter
Serial Interface
and
Mode Control
Digital Out
Parallel Mode Control
System Clock
B0006-02
Digital In
Oversampling
Digital
Interpolation
Filter
Lch Out
Rch Out
Low-Pass Filter
and
Output Buffer
Multilevel
Delta-Sigma
Modulator
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
16-Bit, Single-Ended Analog Input/Output Stereo Audio Codec
•Sampling Keyboards•Monolithic 16-Bit ∆ Σ ADC and DAC
•Digital Mixers•Stereo ADC:
•Effects Processors– Single-Ended Voltage Input
•Hard-Disk Recorders– Antialiasing Filter
•Data Recorders– 64 ×Oversampling
•Digital Video Cameras– High Performance
•THD+N: –84 dB•SNR: 89 dB
The PCM3006 is a low-cost, single-chip stereo audio•Dynamic Range: 89 dB
codec (analog-to-digital and digital-to-analog con-verters) with single-ended analog voltage input and– Digital High-Pass Filter
output.•Stereo DAC:
Both ADCs and DACs employ delta-sigma modu-– Single-Ended Voltage Output
lation with 64-times oversampling. The ADCs include– Analog Low-Pass Filter
a digital decimation filter, and the DACs include an– 8 ×Oversampling Digital Filter
8-times oversampling digital interpolation filter. TheDACs also include a digital de-emphasis function.– High Performance
The PCM3006 operates with 16-bit, left-justified for•THD+N: –84 dB
ADC, right-justified for DAC data formats.•SNR: 93 dB
The PCM3006 provides a power-down mode that•Dynamic Range: 93 dB
operates on the ADCs and DACs independently.•Special Features
The PCM3006 is fabricated using a highly advanced– Digital De-Emphasis
CMOS process, and is available in a small 24-pin– Power Down: ADC/DAC Independent
TSSOP package. The PCM3006 is suitable for a widevariety of cost-sensitive consumer applications where•Sampling Rate: 4 kHz to 48 kHz
good performance is required.•System Clock: 256 f
S
, 384 f
S
, 512 f
S•Single 3-V Power Supply•Small Package: 24-Lead TSSOP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.System Two, Audio Precision are trademarks of Audio Precision, Inc.All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2004, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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ELECTRICAL CHARACTERISTICS
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.
All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S
, and 16-bit data, unless otherwise noted
PCM3006TPARAMETER CONDITIONS UNITSMIN TYP MAX
DIGITAL INPUT/OUTPUT
Input Logic
V
IH
(1)
0.7 V
DDInput logic level VDCV
IL
(1)
0.3 V
DD
I
IN
(2)
±1Input logic current µAI
IN
(3)
100
Output Logic
V
OH
(4)
I
OUT
= –1 mA V
DD
– 0.3 VDCOutput logic levelV
OL
(4)
I
OUT
= 1 mA 0.3
CLOCK FREQUENCY
f
s
Sampling frequency 4 44.1 48 kHz256 f
S
1.024 11.2896 12.288System clock frequency 384 f
S
1.536 16.9344 18.432 MHz512 f
S
2.048 22.5792 24.576
ADC CHARACTERISTICS
Resolution 16 Bits
DC Accuracy
Gain mismatch, channel-to-channel ±1±3 % of FSRGain error ±2±5 % of FSRGain drift ±20 ppm of FSR/ °C
Dynamic Performance
(5)
V
IN
= –0.5 dB –84 –77THD+N dBV
IN
= –60 dB –26Dynamic range A-weighted 84 89 dBSignal-to-noise ratio A-weighted 84 89 dBChannel separation 82 86 dB
Digital Filter Performance
Pass band 0.454 f
S
HzStop band 0.583 f
S
HzPass-band ripple ±0.05 dBStop-band attenuation –65 dBDelay time 17.4/f
S
s
(1) Pins 7, 8, 9, 10, 11, 15, 17, 18: PDAD, PDDA, SYSCLK, LRCIN, BCKIN, DIN, DEM1, DEM0 (Schmitt-trigger input with 100-k Ωtypicalinternal pulldown resistor)(2) Pins 9, 10, 11, 15: SYSCLK, LRCIN, BCKIN, DIN (Schmitt-trigger input)(3) Pins 7, 8, 17, 18: PDAD, PDDA, DEM1, DEM0 (Schmitt-trigger input, 100-k Ωtypical internal pulldown resistor)(4) Pin 12: DOUT(5) f
IN
= 1 kHz, using System Two™ audio measurement system by Audio Precision™, rms mode with 20-kHz LPF, 400-Hz HPF used forperformance calculation.
2
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PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S
, and 16-bit data, unless otherwise noted
PCM3006TPARAMETER CONDITIONS UNITSMIN TYP MAX
HPF frequency response –3 dB 0.019 f
S
mHz
Analog Input
Voltage range 0.6 V
CC
Vp-pCenter voltage 0.5 V
CC
VDCInput impedance 30 k ΩAntialiasing filter frequency –3 dB 150 kHzresponse
DAC CHARACTERISTICS
Resolution 16 Bits
DC Accuracy
Gain mismatch, channel-to-channel ±1 3 % of FSRGain error ±1 5 % of FSRGain drift ±20 ppm of FSR/ °CBipolar zero error ±2.5 % of FSRBipolar zero drift ±20 ppm of FSR/ °C
Dynamic Performance
(6)
V
OUT
= 0 dB (full scale) –84 –77THD+N dBV
OUT
= –60 dB –30Dynamic range EIAJ, A-weighted 86 93 dBSignal-to-noise ratio EIAJ, A-weighted 86 93 dBChannel separation 84 90 dB
Digital Filter Performance
Pass band 0.445 f
S
HzStop band 0.555 f
S
HzPass-band ripple ±0.17 dBStop-band attenuation –35 dBDelay time 11.1/f
S
s
Analog Output
Voltage range 0.6 V
CC
Vp-pCenter voltage 0.5 V
CC
VDCLoad impedance AC coupling 10 k ΩLPF frequency response f = 20 kHz –0.16 dB
(6) f
OUT
= 1 kHz, using System Two audio measurement system by Audio Precision, rms mode with 20-kHz LPF, 400-Hz HPF used forperformance calculation.
3
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PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
ELECTRICAL CHARACTERISTICS (continued)All specifications at T
A
= 25 °C, V
DD
= V
CC
= 3 V, f
S
= 44.1 kHz, SYSCLK = 384 f
S
, and 16-bit data, unless otherwise noted
PCM3006TPARAMETER CONDITIONS UNITSMIN TYP MAX
POWER SUPPLY REQUIREMENTS
–25 °C to 85 °C 2.7 3 3.6V
CC
, V
DD
Voltage range VDC0°C to 70 °C
(7)
2.4 3 3.6ADC/DAC operation, V
CC
= 18 24V
DD
= 3 VADC operation, V
CC
= V
DD
12 16
mA= 3 VSupply current
DAC operation, V
CC
= V
DD
7 10= 3 VADC/DAC power down
(8)
, 50 µAV
CC
= V
DD
= 3 VADC/DAC operation, V
CC
= 54 72V
DD
= 3 VADC operation, V
CC
= V
DD
36 48
mW= 3 VPower dissipation
DAC operation, V
CC
= V
DD
21 30= 3 VADC/DAC power down
(8)
, 150 µWV
CC
= V
DD
= 3 V
TEMPERATURE RANGE
T
A
Operation –25 85
°CT
stg
Storage –55 125θ
JA
Thermal resistance 100 °C/W
(7) Applies for voltages between 2.4 V and 2.7 V, for 0 °C to 70 °C, and 256-f
S
/512-f
S
operation (384-f
S
not available)(8) SYSCLK, BCKIN, and LRCIN are stopped.
4
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P0006-01
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC1
VCC1
VINR
VREF1
VREF2
VINL
PDAD
PDDA
SYSCLK
LRCIN
BCKIN
DOUT
VCC2
NC
AGND
VCOM
VOUTR
VOUTL
DEM0
DEM1
NC
DIN
VDD
DGND
PCM3006
(TOP VIEW)
NC = No Connection
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
PIN CONFIGURATION
PIN ASSIGNMENTS
NAME PIN I/O DESCRIPTION
AGND 22 – Analog groundBCKIN 11 I Bit clock input
(1)
DEM0 18 I De-emphasis control 0
(1) (2)
DEM1 17 I De-emphasis control 1
(1) (2)
DGND 13 – Digital groundDIN 15 I Data input
(1)
DOUT 12 O Data outputLRCIN 10 I Sample rate clock input (f
s
)
(1)
NC 16, 23 – No connectionPDAD 7 I ADC power down, active LOW
(1) (2)
PDDA 8 I DAC power down, active LOW
(1) (2)
SYSCLK 9 I System clock input
(1)
V
CC
1 1, 2 – ADC analog power supplyV
CC
2 24 – DAC analog power supplyV
COM
21 – ADC/DAC commonV
DD
14 – Digital power supplyV
IN
L 6 I ADC analog input, LchV
IN
R 3 I ADC analog input, RchV
OUT
L 19 O DAC analog output, LchV
OUT
R 20 O DAC analog output, RchV
REF
1 4 – ADC reference, 1V
REF
2 5 – ADC reference, 2
(1) Schmitt-trigger input(2) With 100-k Ωtypical internal pulldown resistor
5
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
Supply voltage: V
DD
, V
CC
1, V
CC
2 –0.3 V to 6.5 VSupply voltage differences ±0.1 VGND voltage differences ±0.1 VDigital input voltage –0.3 V to V
DD
+ 0.3 V, < 6.5 VAnalog input voltage –0.3 to V
CC
1, V
CC
2 + 0.3 V, < 6.5 VPower dissipation 300 mWInput current (any pins except supplies) ±10 mAOperating temperature –25 °C to 85 °CStorage temperature –55 °C to 125 °CLead temperature, soldering 260 °C, 5 sPackage temperature (IR reflow, peak) 235 °C
over operating free-air temperature range
MIN NOM MAX UNIT
Analog supply voltage , V
CC
1, V
CC
2 2.7 3 3.6 VDigital supply voltage , V
DD
2.7 3 3.6 VAnalog input voltage, full scale (–0 db) V
CC
= 3 V 1.8 Vp-pDigital input logic family CMOSDigital input clock frequency System clock 8.192 24.576 MHzSampling clock 32 48 kHzAnalog output load resistance 10 k ΩAnalog output load capacitance 30 pFDigital output load capacitance 10 pFOperating free-air temperature, T
A
–25 85 °C
PACKAGE/ORDERING INFORMATION
PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE QUANTITYCODE MARKING NUMBER MEDIA
PCM3006T Rails 128PCM3006T 24-pin TSSOP DCV PCM3006T
PCM3006T/2K Tape and reel 2000
6
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TYPICAL PERFORMANCE CURVES
ADC SECTION
84
86
88
90
92
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range − dB
SNR
92
90
88
84
86
SNR − Signal-to-Noise Ratio − dB
G002
Dynamic Range
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
−0.5 dB
6
5
4
2
3
−60 dB
G001
THD+N − Total Harm. Dist. + Noise at −60 dB − %
84
86
88
90
92
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply Voltage − V
Dynamic Range − dB
92
90
88
84
86
SNR − Signal-to-Noise Ratio − dB
G004
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
6
5
4
2
3
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G003
−60 dB
−0.5 dB
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
THD+N DYNAMIC RANGE and SNRvs vsTEMPERATURE TEMPERATURE
Figure 1. Figure 2.
THD+N DYNAMIC RANGE and SNRvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 3. Figure 4.
NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 f
S
.
7
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84
86
88
90
92
Dynamic Range − dB
92
90
88
84
86
SNR − Signal-to-Noise Ratio − dB
G006
Dynamic Range
SNR
fS − Sampling Frequency − kHz
4832 44.1
0.002
0.004
0.006
0.008
0.010
fS − Sampling Frequency − kHz
THD+N − Total Harm. Dist. + Noise at −0.5 dB − %
6
5
4
2
3
G005
THD+N − Total Harm. Dist. + Noise at −60 dB − %
4832 44.1
−60 dB
−0.5 dB
DAC SECTION
88
90
92
94
96
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
Dynamic Range − dB
SNR
96
94
92
88
90
SNR − Signal-to-Noise Ratio − dB
G008
Dynamic Range
0.002
0.004
0.006
0.008
0.010
−25 0 25 50 75 100
TA − Free-Air Temperature − °C
THD+N − Total Harm. Dist. + Noise at FS − %
FS
4
3
2
0
1
−60 dB
G007
THD+N − Total Harm. Dist. + Noise at −60 dB − %
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
THD+N DYNAMIC RANGE and SNRvs vsSAMPLING FREQUENCY SAMPLING FREQUENCY
Figure 5. Figure 6.
THD+N DYNAMIC RANGE and SNRvs vsTEMPERATURE TEMPERATURE
Figure 7. Figure 8.
8
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88
90
92
94
96
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply Voltage − V
Dynamic Range − dB
96
94
92
88
90
SNR − Signal-to-Noise Ratio − dB
G010
Dynamic Range
SNR
0.002
0.004
0.006
0.008
0.010
2.1 2.4 2.7 3.0 3.3 3.6 3.9
VCC − Supply V oltage − V
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
THD+N − Total Harm. Dist. + Noise at −60 dB − %
G009
−60 dB
FS
88
90
92
94
96
Dynamic Range − dB
96
94
92
88
90
SNR − Signal-to-Noise Ratio − dB
G012
SNR
fS − Sampling Frequency − kHz
4832 44.1
256 fS, 512 fS
384 fS
Dynamic
Range
0.002
0.004
0.006
0.008
0.010
fS − Sampling Frequency − kHz
THD+N − Total Harm. Dist. + Noise at FS − %
4
3
2
0
1
G011
THD+N − Total Harm. Dist. + Noise at −60 dB − %
4832 44.1
384 fS
256 fS, 512 fS
384 fS
FS
−60 dB
256 fS, 512 fS
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, f
SYSCLK
= 384 f
S
, and f
SIGNAL
= 1 kHz, unless otherwise noted
THD+N DYNAMIC RANGE and SNRvs vsSUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 9. Figure 10.
NOTE: All characteristics at supply voltages from 2.4 V to 2.7 V are measured at SYSCLK = 256 f
S
.
THD+N DYNAMIC RANGE and SNRvs vsSAMPLING FREQUENCY and SYSTEM CLOCK SAMPLING FREQUENCY and SYSTEM CLOCK
Figure 11. Figure 12.
9
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs)
DECIMATION FILTER
Normalized Frequency [× fS Hz]
−200
−150
−100
−50
0
0 8 16 24 32
Amplitude − dB
G013
Normalized Frequency [× fS Hz]
−100
−80
−60
−40
−20
0
0.0 0.2 0.4 0.6 0.8 1.0
Amplitude − dB
G014
Normalized Frequency [× fS Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G015
Normalized Frequency [× fS Hz]
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
0.45 0.47 0.49 0.51 0.53 0.55
Amplitude − dB
G016
−4.13 dB at 0.5 fS
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
OVERALL CHARACTERISTICS STOP-BAND ATTENUATION CHARACTERISTICS
Figure 13. Figure 14.
PASS-BAND RIPPLE CHARACTERISTICS TRANSITION BAND CHARACTERISTICS
Figure 15. Figure 16.
10
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HIGH-PASS FILTER
Normalized Frequency [× fS/1000 Hz]
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
0 1 2 3 4
Amplitude − dB
G018
Normalized Frequency [× fS/1000 Hz]
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0.0 0.1 0.2 0.3 0.4 0.5
Amplitude − dB
G017
ANTIALIASING FILTER
−50
−40
−30
−20
−10
0
f − Frequency − Hz
Amplitude − dB
110 100 10M1k 10k
G019
100k 1M
−1.0
−0.8
−0.6
−0.4
−0.2
0.0
0.2
f − Frequency − Hz
Amplitude − dB
110 100 100k1k 10k
G020
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (ADCs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
HIGH-PASS FILTER RESPONSE HIGH-PASS FILTER RESPONSE
Figure 17. Figure 18.
ANTIALIASING FILTER ANTIALIASING FILTEROVERALL FREQUENCY RESPONSE PASS-BAND FREQUENCY RESPONSE
Figure 19. Figure 20.
11
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TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs)
DIGITAL FILTER
−100
−80
−60
−40
−20
0
Level − dB
f − Frequency − Hz
75k25k 50k
G021
0 175k100k 125k 150k
−1.00
−0.80
−0.60
−0.40
−0.20
0.00
Level − dB
f − Frequency − Hz
5k
G022
0 20k10k 15k
DE-EMPHASIS FILTER
−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G023
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
3628
G024
0 145127256 10884
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
OVERALL FREQUENCY CHARACTERISTICS PASS-BAND RIPPLE CHARACTERISTICS(f
S
= 44.1 kHz) (f
S
= 44.1 kHz)
Figure 21. Figure 22.
DE-EMPHASIS FREQUENCY RESPONSE (32 kHz) DE-EMPHASIS ERROR (32 kHz)
Figure 23. Figure 24.
12
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−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G025
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
4999.8375
G026
0 19999.359999.675 14999.5125
−12
−10
−8
−6
−4
−2
0
Level − dB
f − Frequency − Hz
5k
G027
0 25k10k 15k 20k
−0.6
−0.4
−0.2
0.0
0.2
0.4
0.6
Error − dB
f − Frequency − Hz
5442
G028
0 2176810884 16326
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
DE-EMPHASIS FREQUENCY RESPONSE (44.1 kHz) DE-EMPHASIS ERROR (44.1 kHz)
Figure 25. Figure 26.
DE-EMPHASIS FREQUENCY RESPONSE (48 kHz) DE-EMPHASIS ERROR (48 kHz)
Figure 27. Figure 28.
13
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ANALOG LOW-PASS FILTER
−100
−80
−60
−40
−20
0
20
f − Frequency − Hz
Level − dB
110 100 10M1k 10k
G029
100k 1M
−0.15
−0.10
−0.05
0.00
0.05
0.10
0.15
f − Frequency − Hz
Level − dB
110 100 100k1k 10k
G030
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
TYPICAL PERFORMANCE CURVES OF INTERNAL FILTERS (DACs) (continued)All specifications at T
A
= 25 °C, V
CC
= V
DD
= 3 V, f
S
= 44.1 kHz, and f
SYSCLK
= 384 f
S
, unless otherwise noted
INTERNAL ANALOG FILTER FREQUENCY RESPONSE INTERNAL ANALOG FILTER FREQUENCY RESPONSE(1 Hz–10 MHz) (1 Hz–100 kHz)
Figure 29. Figure 30.
14
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PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
BLOCK DIAGRAM
15
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30 kΩ
VINR
VCOM
3
21
5
Delta-Sigma
Modulator
(+)
VREF
VREF2
+
1.0 µF
4.7 µF+
+
−
(−)
+
−
S0011-03
VREF1
4
4.7 µF+
4.7 µF+
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 31. Analog Front End (Single-Channel)
16
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APPLICATION INFORMATION
PCM AUDIO INTERFACE
DAC: 16-Bit, MSB-First, Right-Justified
FORMAT 0: PCM3006
LRCIN Right-ChannelLeft-Channel
BCKIN
DIN
MSB LSB MSB LSB
321 16151416 321 161514
BCKIN
LRCIN Right-ChannelLeft-Channel
DOUT 1
14 15 16321
MSB LSB MSB LSB
14 15 16321
ADC: 16-Bit, MSB-First, Left-Justified
T0016-06
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
The four-wire digital audio interface for the PCM3006 comprises LRCIN (pin 10), BCKIN (pin 11), DIN (pin 15),and DOUT (pin 12). The PCM3006 accepts 16-bit MSB-first, right-justified format for the DAC and 16-bitMSB-first, left-justified format for the ADC. The PCM3006 can accept 32, 48, or 64 bit clocks (BCKIN) in oneclock of LRCIN. Figure 32 and Figure 33 illustrate audio data input/output format and timing.
Figure 32. Audio Data Input/Output Format
17
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BCKIN
LRCIN
DIN
t(BCH)
t(BCL)
t(LRP)
t(LB)
t(BCY)
0.5 VDD
t(BL)
DOUT
t(BDO) t(LDO)
0.5 VDD
t(DIS) t(DIH)
0.5 VDD
0.5 VDD
T0021−01
SYSTEM CLOCK
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
BCKIN pulse cycle time t
(BCY)
300 ns (min)BCKIN pulse duration, HIGH t
(BCH)
120 ns (min)BCKIN pulse duration, LOW t
(BCL)
120 ns (min)BCKIN rising edge to LRCIN edge t
(BL)
40 ns (min)LRCIN edge to BCKIN rising edge t
(LB)
40 ns (min)LRCIN pulse duration t
(LRP)
t
(BCY)
(min)DIN setup time t
(DIS)
40 ns (min)DIN hold time t
(DIH)
40 ns (min)DOUT delay time to BCKIN falling edge t
(BDO)
40 ns (max)DOUT delay time to LRCIN edge t
(LDO)
40 ns (max)Rising time of all signals t
(RISE)
20 ns (max)Falling time of all signals t
(FALL)
20 ns (max)
Figure 33. Audio Data Input/Output Timing
The system clock for the PCM3006 must be either 256 f
S
, 384 f
S
or 512 f
S
, where f
S
is the audio samplingfrequency. The system clock should be provided to SYSCLK (pin 9).
The PCM3006 also has a system clock detection circuit that automatically senses if the system clock is operatingat 256 f
S
, 384 f
S
, or 512 f
S
. When a 384-f
S
or 512-f
S
system clock is used, the clock is divded into 256 f
Sautomatically. The 256-f
S
clock is used to operate the digital filter and the delta-sigma modulator.
Table 1 lists the relationship of typical sampling frequencies and system clock frequencies, and Figure 34illustrates the system clock timing.
Table 1. System Clock Frequencies
SAMPLING RATE FREQUENCY SYSTEM CLOCK FREQUENCY(kHz) MHz
256 f
s
384 f
s
512 f
s
32 8.1920 12.2880 16.384044.1 11.2896 16.9344 22.579248 12.2880 18.4320 24.5760
18
www.ti.com
t(SCKH)
SYSCLK 0.3 VDD
0.7 VDD
t(SCKL)
1/256 fS,
1/384 fS,
or 1/512 fS
H
L
T0005-05
RESET
1024 System Clock Periods
Reset Reset Removal
2.4 V
2.2 V
2.0 V
VDD
Internal Reset
System Clock
T0014-03
3 Clocks Minimum
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
System clock duration, HIGH t
(SCKH)
12 ns (min)System clock duration, LOW t
(SCKL)
12 ns (min)
Figure 34. System Clock Timing
The PCM3006 has an internal power-on reset circuit, as well as an external forced reset. The internal power-onreset initializes (resets) when the supply voltage V
DD
> 2.2 V (typ). External forced reset occurs when PDAD =LOW and PDDA = LOW. Figure 35 shows the internal power-on reset timing and Figure 36 shows the externalforced reset timing by PDAD and PDDA. During external forced reset, the outputs of the DAC are forced to GND(see Figure 37 ). The analog outputs are then forced to 0.5 V
CC
during t
(DACDLY1)
(16384/f
S
) after reset removal.The outputs of ADC are also invalid; digital outputs are forced to all zero during t
(ADCDLY1)
(18432/f
S
) after resetremoval.
Figure 35. Internal Power-On Reset Timing
19
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t(RST)
Reset Removal
1024 System Clock Periods
PDAD and PDDA
Internal Reset
System Clock
t(RST) = 40 ns (min)
Reset
T0015-03
PDAD = LOW and PDDA = LOW Pulse Duration
T0019-02
Reset Ready/Operation
Internal Reset
or Power Down
DAC VOUT
t(DACDLY1)
(16384/fS)
Reset Removal or Power Down Off
Power Down
ADC DOUT Zero Data Normal Data(1)
VCOM
(0.5 VCC)
t(ADCDLY1)
(18432/fS)
Zero Data
GND
SYNCHRONIZATION WITH THE DIGITAL AUDIO SYSTEM
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
Figure 36. External Forced-Reset Timing
(1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant)appears initially.
Figure 37. DAC Output and ADC Output for Reset and Power Down
The PCM3006 operates with LRCIN synchronized to the system clock. The PCM3006 does not require anyspecific phase relationship between LRCIN and the system clock, but there must be synchronization of LRCINand the system clock. If the relationship between the system clock and LRCIN changes more than 6 bit clocks(BCKIN) during one sample (LRCIN) period because of phase jitter on LRCIN, internal operation of the DACstops within 1/f
S
, and the analog output is forced to bipolar zero (0.5 V
CC
) until t
(DACDLY2)
delay time after thesystem clock is resynchronized to LRCIN. Internal operation of the ADC also stops within 1/f
S
, and the digitaloutput codes are set to bipolar zero until t
(DACDLY2)
delay time after resynchronization occurs. If LRCIN remainssynchronized to the system clock within 5 or fewer bit clocks, operation is normal. Figure 38 illustrates the effectson the output when synchronization is lost. Before the outputs are forced to bipolar zero (<1/f
S
seconds), theoutputs are not defined and some noise may occur. During the transitions between normal data and undefinedstates, the output has discontinuities, which cause output noise.
20
www.ti.com
Within 1/fSt(DACDLY2)
(32/fS)
Normal Data
VCOM
(0.5 VCC)
Undefined
Data
Normal Data
SynchronousAsynchronousSynchronous
Resynchronization
Synchronization Lost
DAC VOUT
State of Synchronization
T0020-03
Normal Data(1)
Zero DataNormal Data
ADC DOUT
t(ADCDLY2)
(32/fS)
Undefined
Data
OPERATIONAL CONTROL
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) The HPF transient response (exponentially attenuated signal from ±0.2% dc of FSR with 200-ms time constant)appears initially.
Figure 38. DAC Output and ADC Output for Loss of Synchronization
The PCM3006 has hardwire functional control using PDAD (pin 7) and PDDA (pin 8) for power-down control andDEM0 (pin 18) and DEM1 (pin 17) for de-emphasis.
PDAD: ADC Power-Down Control (Pin 7)This pin places the ADC section in the lowest power-consumption mode. The ADC operation isstopped by cutting the supply current to the ADC section, and DOUT is fixed to zero during ADCpower-down-mode enable. Figure 37 illustrates the ADC DOUT response for ADC power-downON/OFF. This does not affect the DAC operation.PDAD POWER DOWN
Low ADC power-down mode enabledHigh ADC power-down mode disabled
PDDA: DAC Power-Down Control (Pin 8)This pin places the DAC section in the lowest power-consumption mode. The DAC operation isstopped by cutting the supply current to the DAC section and VOUT is fixed to GND during DACpower-down-mode enable. Figure 37 illustrates the DAC VOUT response for DAC power-down ON/OFF. This does not affect the ADC operation.PDDA POWER DOWN
Low DAC power-down mode enabledHigh DAC power-down mode disabled
DEM [1:0]: DAC De-Emphasis Control (Pin 17 and Pin 18)These pins select the de-emphasis mode as shown below:DEM1 DEM0 DE-EMPHASIS
Low Low De-emphasis 44.1 kHz ONLow High De-emphasis OFFHigh Low De-emphasis 48 kHz ONHigh High De-emphasis 32 kHz ON
21
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APPLICATION AND LAYOUT CONSIDERATIONS
POWER-SUPPLY BYPASSING
GROUNDING
VOLTAGE INPUT
V
REF
INPUTS
V
COM
INPUT
SYSTEM CLOCK
RST CONTROL
EXTERNAL MUTE CONTROL
TYPICAL CONNECTION DIAGRAM
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
The digital and analog power supply lines to the PCM3006 should be bypassed to the corresponding ground pinswith both 0.1- µF ceramic and 10- µF tantalum capacitors as close to the device pins as possible. Although thePCM3006 has three power supply lines to optimize dynamic performance, the use of one common power supplyis generally recommended to avoid unexpected latch-up or pop noise due to power-supply sequencing problems.If separate power supplies are used, back-to-back diodes are recommended to avoid latch-up problems.
In order to optimize the dynamic performance of the PCM3006, the analog and digital grounds are not connectedinternally. The PCM3006 performance is optimized with a single ground plane for all returns. It is recommendedto tie all PCM3006 ground pins to the analog ground plane using low-impedance connections. The PCM3006should reside entirely over this plane to avoid coupling high-frequency digital switching noise into the analogground plane.
A tantalum capacitor, between 1 µF and 10 µF, is recommended as an ac-coupling capacitor at the inputs.Combined with the 30-k Ωcharacteristic input impedance, a 1- µF coupling capacitor establishes a 5.3-Hz cutofffrequency for blocking dc. The input voltage range can be increased by adding a series resistor on the analoginput line. This series resistor, when combined with the 30-k Ωinput impedance, creates a voltage divider andenables larger input ranges.
A 4.7- µF to 10- µF tantalum capacitor is recommended between V
REF
1, V
REF
2, and AGND to ensure low sourceimpedance for the ADC references. These capacitors should be located as close as possible to the referencepins to reduce dynamic errors on the ADC reference.
A 4.7- µF to 10- µF tantalum capacitor is recommended between V
COM
and AGND to ensure low sourceimpedance of the ADC and DAC common voltage. This capacitor should be located as close as possible to theV
COM
pin to reduce dynamic errors on the ADC and DAC common voltage.
The quality of the system clock can influence dynamic performance of both the ADC and DAC in the PCM3006.The duty cycle and jitter at the system clock input pin should be carefully managed. When power is supplied tothe part, the system clock, bit clock (BCKIN), and word clock (LCRIN) must also be supplied simultaneously.Failure to supply the audio clocks results in a power dissipation increase of up to three times normal dissipationand can degrade long-term reliability if the maximum power-dissipation limit is exceeded.
If capacitors larger than 22 µF are used between V
REF
and V
COM
, external reset control by PDAD = LOW andPDDA = LOW is required after the V
REF
, V
COM
transient response has settled.
Click noises are caused by dc level changes at the DAC output. To avoid any click noises going in and out ofpower-down mode, an external mute control is generally required. The recommended control sequence is asfollows: external mute ON, codec power-down OFF, and then external mute OFF.
NOTE: If SYSCLK is stopped when the PCM3006 is in power-down mode, the device is internally reset.
Figure 39 is a schematic diagram showing typical connections for the PCM3006.
22
www.ti.com
VREF220
19
18
17
16
15
14
13
5
6
7
8
9
10
11
12
VINL
PDAD
PDDA
SYSCLK
LRCIN
BCKIN
DOUT
VOUTR
DGND
VOUTL
DEM0
DEM1
NC
VDD
DIN
Rch In
Audio
Interface
VCC124
23
22
21
1
2
3
4
VCC1
VINR
VREF1
VCC2
NC
AGND
VCOM
+
+
0.1 µF
and 10 µF(1)
DEM0
Control
Interface
PCM3006
+
+
1 µF(3)
4.7 µF(2)
4.7 µF(2)
Lch In +
1 µF(3)
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
S0014-02
+3 V Analog VCC
+
+
0.1 µF
and 10 µF(1)
4.7 µF(2)
+
4.7 µF(4) Rch Out(5)
Lch Out(5)
DEM1
0.1 µF
and 10 µF(1)
PDDA
PDAD
4.7 µF(4) +
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
(1) 0.1- µF ceramic and 10- µF tantalum, typical, depending on power supply quality and pattern layout(2) 4.7- µF, typical, gives settling time with a 30-ms (4.7 µF×6.4 k Ω) time constant in the power ON and power-downOFF periods.(3) 1- µF, typical, gives a 5.3-Hz cutoff frequency for the input HPF in normal operation, and gives a settling time with a30-ms (1 µF×30 k Ω) time constant in the power ON and power-down OFF periods.(4) 4.7- µF, typical, gives a 3.4-Hz cutoff frequency for the output HPF in normal operation, and gives a settling time witha 47-ms (4.7 µF×10 k Ω) time constant in the power ON and power-down OFF periods.(5) Post low-pass filter with RIN > 10 k Ω, depending on the system performance requirements
Figure 39. Typical Connection Diagram for PCM3006
23
www.ti.com
THEORY OF OPERATION
ADC SECTION
1st
SW-CAP
Integrator
Analog
In
X(z) +
−
+−2nd
SW-CAP
Integrator
3rd
SW-CAP
Integrator
+−4th
SW-CAP
Integrator
++++
++++
5th
SW-CAP
Integrator
Digital
Out
Y(z)
Comparator
Qn(z)
H(z)
1-Bit
DAC
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1 / [1 + H(z)]
Y(z) = STF(z) * X(z) + NTF(z) * Qn(z)
Signal Transfer Function
Noise Transfer Function B0005-01
DAC SECTION
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
The PCM3006 ADC consists of two reference circuits, a stereo single-to-differential converter, a fully differential5-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit. Theblock diagram in this data sheet illustrates the architecture of the ADC section, Figure 31 shows thesingle-to-differential converter, and Figure 40 illustrates the architecture of the 5-order delta-sigma modulator andtransfer functions.
Figure 40. Simplified 5-Order Delta-Sigma Modulator
An internal reference circuit with three external capacitors provides all reference voltages that are required by theADC, which defines the full-scale range for the converter. The internal single-to-differential voltage convertersaves the design, space, and extra parts needed for the external circuitry required by many delta-sigmaconverters. The internal full-differential signal processing architecture provides wide dynamic range and excellentpower-supply rejection performance. The input signal is sampled at 64 ×the oversampling rate, eliminating theneed for a sample-and-hold circuit and simplifying antialias filtering requirements. The 5-order delta-sigma noiseshaper consists of five integrators using switched-capacitor topology, a comparator, and a feedback loopconsisting of a one-bit DAC. The delta-sigma modulator shapes the quantization noise, shifting it out of the audioband in the frequency domain. The high order of the modulator enables it to randomize the modulator outputs,reducing idle tone levels.
The 64-f
S
one-bit data stream from the modulator is converted to 1-f
S
16-bit data words by the decimation filter,which also acts as a low-pass filter to remove the shaped quantization noise. The dc components are removedby a high-pass filter function contained within the decimation filter.
The delta-sigma DAC section of the PCM3006 is based on a 5-level amplitude quantizer and a third-order noiseshaper. This section converts the oversampled input data to 5-level delta-sigma format. A block diagram of the5-level delta-sigma modulator is shown in Figure 41 . This 5-level delta-sigma modulator has the advantage ofstability and clock-jitter sensitivity over the typical one-bit (2-level) delta-sigma modulator. The combinedoversampling rate of the delta-sigma modulator and the internal 8 ×interpolation filter is 64 f
S
for a 256-f
S
systemclock. The theoretical quantization noise performance of the 5-level delta-sigma modulator shown in Figure 42 .
24
www.ti.com
+
+−Z−1
+ +
+
+−Z−1
In
8 fS
21-Bit
Out
64 fS
+
+Z−1
B0008-01
+
5-Level Quantizer
0
1
2
3
4
f − Frequency − kHz
−150
−140
−130
−120
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
0 5 10 15 20 25 30
Gain − dB
G031
PCM3006
SBAS089A – OCTOBER 2000 – REVISED OCTOBER 2004
THEORY OF OPERATION (continued)
Figure 41. 5-Level ∆ Σ Modulator Block Diagram
Figure 42. Quantization Noise Spectrum
25
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCM3006T ACTIVE SSOP DCV 24 128 Green (RoHS &
no Sb/Br) CU SNBI Level-1-260C-UNLIM
PCM3006T/2K ACTIVE SSOP DCV 24 2000 Green (RoHS &
no Sb/Br) CU SNBI Level-1-260C-UNLIM
PCM3006T/2KG6 ACTIVE SSOP DCV 24 2000 Green (RoHS &
no Sb/Br) CU SNBI Level-1-260C-UNLIM
PCM3006TG6 ACTIVE SSOP DCV 24 128 Green (RoHS &
no Sb/Br) CU SNBI Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jul-2006
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
PCM3006T/2K SSOP DCV 24 2000 330.0 17.4 8.1 8.5 1.75 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Aug-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCM3006T/2K SSOP DCV 24 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Aug-2008
Pack Materials-Page 2
MECHANICAL DATA
MPSS001 – MARCH 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCV (R-PSOP-G24) PLASTIC SMALL-OUTLINE
C
D
M
0,10
0,10
0,65
4202107/A 03/01
Area
A
A
7,70
8,20
7,40
7,80
6,00 MAX
0,30
0,19
1,45 MAX
1,15 TYP
0,05
0,15
Gage
Plane
0,25 REF
0°-10°
0,30
0,70
Base
Metal
With
Plating
0,09
0,20
0,09
0,16
0,19
0,25
0,30
0,19
112
1324
Index
Seating Plane
C
ESection A-A
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or
protrusions, but do include mold mismatch and are
measured at datum plane, mold parting line. Mold flash
or protrusion shall not exceed 0,20mm per side.
D. Lead width dimension does not include dambar protrusion/
intrusion. Allowable dambar protrusion shall be 0,13mm total
in excess of width dimension at maximum material condition.
Dambar intrusion shall not reduce width dimension by more
than 0,07mm at least material condition.
E. All dimensions in Section A-A apply to the flat section
of the lead between 0,10mm and 0,25mm from the lead tips.
F. A visual index feature must be located within the
cross-hatched area.
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Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
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