Philips Semiconductors Product specification Quad 2-input NAND gate 74LVCOOA FEATURES @ Wide supply range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A @ Inputs accept voltages up to 5.5V @ CMOS low power consumption Direct interface with TTL levels @ 5-volt tolerant inputs, for interfacing with 5-volt logic DESCRIPTION The 74LVCOOA is a high-performance, low power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from aither 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V/5 V environment. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fail times. The 74LVCOO0A provides the 2-input NAND function. QUICK REFERENCE DATA GND = 0 V; Tamb = 25C; t; =p $2.5 ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT teu Propagation delay Cy = 50 pF; 3.0 ns tou nA, nB-to nY Veco =3.3V . Cy Input capacitance 5.0 pF Cep Power dissipation capacitance per gate Vi = GND to Voc! 28 pF NOTES: 1. Cpp is used to determine the dynamic power dissipation (Pp in hw) Pp =Cpp * Voc? xf + w(CL x Vec* x fg) where: f, = input frequency in MHz; C;, = output load capacity in pF; fo = output frequency in MHz; Vcc = supply voltage in V; s (CL X Veo? x fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE | OUTSIDE NORTH AMERICA | NORTH AMERICA | DWG NUMBER 14-Pin Plastic SO 40C to +85C 74LVCO0A D T4LVCOOA D SOT108-1 14-Pin Plastic SSOP Type II 40C to +85C 74LVCO0A DB 74LVCO0A DB $0T337-1 14-Pin Plastic TSSOP Type | ~40C to +85C 74LVCOOA PW 74LVCOOAPW DH SOT402-1 PIN CONFIGURATION LOGIC SYMBOL 1A Veo ; 3 18 4B 4 Vv 4h 5 6 2A ay 9 a 28 | 38 10 ay f 3A 12 4 13 GND | 8} 3v syo0035 PIN DESCRIPTION LOGIC SYMBOL (IEEE/EC ( ) numBen | SYMBOL NAME AND FUNCTION 1 K 3 | * pe 1,4,9,12 | 1A-48 Data inputs * } 5 2,5,10,13 | 1B-4B * 3,6, 8,11 1-4Y | Data outputs sc * 8 7 GND Ground (0 V) 14 Voc Positive supply voltage ok $V00378 1998 Apr 28 467 853-2017 19310 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVCOOA LOGIC DIAGRAM (ONE GATE) FUNCTION TABLE IN Ae INPUTS . OUTPUTS \ nA nB ny B L L H $Vv00379 L H H H L H H H L NOTES: H_ =HIGH voltage level L =LOW voltage level RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS UNIT MIN MAX Voc DC supply voltage (for max. speed performance) 2.7 3.6 Vv Veco DC supply voltage (for low-voltage applications) 1.2 3.6 v Vi DC Input voltage range Q 5.5 Vv Vo DC output voltage range 0 Veco Vv Tamb Operating ambient temperature range in free-air 40 +85 C . . Voc = 1.2 to 2.7V 0 20 ty, te Input rise and fall times Veo = 2.7 10 3.6V 0 10 nsV ABSOLUTE MAXIMUM RATINGS! Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = OV) SYMBOL PARAMETER CONDITIONS RATING UNIT DC supply voltage (for max. speed Vec performance) ~0.5 to +6.5 v tik DC input diode current vi<0 ~50 mA vt DC input voltage Note 2 0.5 to +5.5 v lok OC output diode current Vo >Vec or Vo < 0 +50 mA Vo BC output voltage Note 2 0,5 to Voc + 0.5 v lo DC output source or sink current Vg =0to Voc +50 mA leno: lec =| DC Voc or GND current +100 mA Tstg Storage temperature range ~-65 to +150 C Power dissipation per package Pror ~ plastic mini-pack (SO) above +70C derate linearly with 8 mW/K 500 mw plastic shrink mini-pack (SSOP and TSSOP) above +60C derate linearly with 5.5 mW/K 500 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyand those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 1998 Apr 28 468 Philips Semiconductors Product specification Quad 2-input NAND gate 74LVCOOA DC CHARACTERISTICS Over recommended operating conditions voltages are referenced to GND (ground = 0V) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40C to +85C =| UNIT MIN TYP! | MAX Voo = 1.2V Voc Vin HIGH level Input voltage Vv Voc = 2.7 to 3.6V 2.0 Voc = 1.2V GND Vit LOW level Input voltage Vv Voc = 2.7 to 3.6V 0.8 Voo = 2.7V; Vj = Ving or Vit; lo = -12mA Vcoo 70.5 Voc = 3.0V; Vi = Vir or Viti lo = -100HA Veo~0.2 | Veco Vou HIGH level output voltage v Voc = 3.0V; Vi = Vip or Vi_; fo = -18mA Voc - 0.6 Voc = 3.0V, Vp = Vin or ViL; lp = -24mA Voc 0.8 Voc = 2.7V; Vi = Vin or Vii ig = 12mA 0.40 Vor LOW level output voltage Voc = 3.0V; Vi = Vin or Vin; lo = 100nA 0.20 v Voc = 3.0V; Vi = Viz oF Viz; lo = 24mA 0.55 f Input leakage current Voc = 3.6V; V, = 5,.5V or GND +04 +5 LA lec Quiescent supply current Voc = 3.6V; Vy = Voc or GND; Ip = 0 O41 10 uA Additional quiescent supply current 7 ye _t AV be a Alcc per input pin Voc = 2.7V to 3.6V; Vj = Veco -0.6V; Ip = 0 : 5 500 pA NOTES: . 1. All typical values are at Vcc = 3.3V and Tamp = 25C. AC CHARACTERISTICS GND = OV; t= % < 2.6 ns; C_ = 50 pF LIMITS SYMBOL PARAMETER WAVEFORM Veco = 3.3V +0.3V Vec = 2.7V Voc = 1.2V UNIT MIN Typ! MAX MIN TYP MAX TYP tpyy/ Propagation delay ten nA, nB to nY 1,2 16 3.0 5.0 1.5 3.4 5.8 cai ns NOTE: 1. These typical values are at Vcc = 3.3V and Tamb = 25C. AC WAVEFORMS TEST CIRCUIT Vy = 1.5 VatVeco = 2.7V Vm = 0.5 * Voc at Veg < 2.7 V y Vor and Vox are the typical output voltage drop that occur with the eC output load. | PULSE vi vo yy GENERATOR [-O DUT o L 1 7 nA. nB INPUT Rr | Ty Seok GND Voc vi Test Sy Vou <27v Voc teLHitPHL Open 27v~-a6v | 27V aY OUTPUT syo0077 Vou svo0377 Waveform 2. Load circuitry for switching times. Waveform 1. Input (nA) to output (nY) propagation delays. 1998 Apr 28 469