1
FEATURES DESCRIPTION
APPLICATIONS
Typical Application Circuit
PGor
RESET
OUT
OUT
4
3
5
IN
IN
EN
GND
17
6
8
9
VIN
0.22 Fm
PGor RESET Output
VOUT
47 Fm
+
COUT
(1)
SENSE 7
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007www.ti.com
TPS752xxQ with RESET Output, TPS754xxQ with Power Good OutputFAST-TRANSIENT-RESPONSE 2-A LOW-DROPOUT VOLTAGE REGULATORS
23
•2-A Low-Dropout Voltage Regulator
The TPS752xxQ and TPS754xxQ devices arelow-dropout regulators with integrated power-on reset•Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed
and power-good (PG) functions respectively. TheseOutput and Adjustable Versions
devices are capable of supplying 2 A of output•Open Drain Power-On Reset With 100ms Delay
current with a dropout of 210 mV (TPS75233Q,(TPS752xxQ)
TPS75433Q). Quiescent current is 75 μA at full load•Open Drain Power-Good (PG) Status Output
and drops down to 1 μA when the device is disabled.(TPS754xxQ)
These devices are designed to have fast transientresponse for larger load current changes.•Dropout Voltage Typically 210 mV at 2 A(TPS75233Q)
Because the PMOS device behaves as a low-valueresistor, the dropout voltage is very low (typically•Ultralow 75- μA Typical Quiescent Current
210 mV at an output current of 2 A for the•Fast Transient Response
TPS75x33Q) and is directly proportional to the output•2% Tolerance Over Specified Conditions for
current. Additionally, because the PMOS passFixed-Output Versions
element is a voltage-driven device, the quiescentcurrent is very low and independent of output loading•20-Pin TSSOP PowerPAD™ (PWP) Package
(typically 75 μA over the full range of output current,•Thermal Shutdown Protection
1 mA to 2 A). These two key specifications yield asignificant improvement in operating life forbattery-powered systems.•Telecom
The device is enabled when EN is connected to a•Servers
low-level input voltage. This LDO family also features•DSP, FPGA Supplies
a sleep mode; applying a TTL high signal to EN(enable) shuts down the regulator, reducing thequiescent current to less than 1 μA at T
J
= +25 °C.
blank
blank
(Fixed Voltage Options)
(1) See Application Information for capacitor selection details.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000 – 2007, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION, CONTINUED
ABSOLUTE MAXIMUM RATINGS
(1)
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer andmicroprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQmonitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage.When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-msdelay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during anoverload condition) of its regulated voltage.
The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-onreset or a low-battery indicator.
The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in anadjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as amaximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families areavailable in a 20-pin TSSOP (PWP) package.
blank
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS752 xxyyyz, TPS754 xxyyyz XX is nominal output voltage (for example, 15 = 1.5 V, 01 = Adjustable
(3)
).YYY is package designator.Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Custom fixed output voltages are available; minimum order quantities may apply. Contact factory for details and availability.(3) The TPS75x01 is programmable using an external resistor divider (see Application Information ).
Over operating temperature range (unless otherwise noted).
PARAMETER TPS752xxQ, TPS754xxQ UNIT
Input voltage range, V
IN
(2)
– 0.3 to +6 VVoltage range at EN – 0.3 to +16.5 VMaximum RESET voltage (TPS752xxQ) 16.5 VMaximum PG voltage (TPS754xxQ) 16.5 VPeak output current Internally limitedOutput voltage range at OUT, FB 5.5 VContinuous total power dissipation See Dissipation Ratings TableOperating virtual junction temperature range, T
J
– 40 to +125 °CStorage junction temperature range , T
STG
– 65 to +150 °CESD rating, HBM 2 kV
(1) Stresses above these ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extendedperiods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any otherconditions beyond those specified is not implied.(2) All voltages are with respect to network terminal ground.
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DISSIPATION RATINGS
RECOMMENDED OPERATING CONDITIONS
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
AIRFLOW DERATING FACTORBOARD PACKAGE (CFM) T
A
< +25 °C ABOVE T
A
= +25 °C T
A
= +70 °C T
A
= +85 °C
0 2.9 mW 23.5 mW/ °C 1.9 W 1.5 WLow-K
(1)
PWP
300 4.3 mW 34.6 mW/ °C 2.8 W 2.2 W0 3 W 23.8 mW/ °C 1.9 W 1.5 WHigh-K
(2)
PWP
300 7.2 W 57.9 mW/ °C 4.6 W 3.8 W
(1) This parameter is measured with the recommended copper heat sink pattern on a 1-layer, 5-in נ5-in printed circuit board (PCB), 1-ouncecopper, 2-in נ2-in coverage (4 in
2
).(2) This parameter is measured with the recommended copper heat sink pattern on a 8-layer, 1.5-in נ2-in PCB, 1-ounce copper with layers1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in
2
) and layers 3 and 6 at 100% coverage (6 in
2
). For more information, refer to TI technical briefSLMA002 .
MIN MAX MAX
V
IN
Input voltage range
(1)
2.7 5.5 VV
OUT
Output voltage range 1.5 5 VI
OUT
Output current 0 2.0 AT
J
Operating virtual junction temperature – 40 +125 °C
(1) To calculate the minimum input voltage for your maximum output current, use the following equation: V
IN(min)
= V
OUT(max)
+ V
DO(max load)
.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 3
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ELECTRICAL CHARACTERISTICS
LineRegulation(mV)=(%/V) ´´1000
V (V 2.7V)
100
-
OUT IN(Max)
LineRegulation(mV)=(%/V) ´´1000
V [V (V +1V)]
100
-
OUT IN(Max) OUT
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Over recommended operating temperature range (T
J
= – 40 °C to +125 °C), V
IN
= V
OUT(TYP)
+ 1 V; I
OUT
= 1 mA, V
EN
= 0 V,C
OUT
= 47 μF, unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS752xxQ, TPS754xxQ
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Adjustable output 1.5 V ≤V
OUT
≤5.5 V 0.98V
OUT
V
OUT
1.02V
OUT
1.5 V output 2.7 V < V
IN
< 5.5 V 1.470 1.5 1.530V
OUT
(1)
1.8 V output 2.8 V < V
IN
< 5.5 V 1.764 1.8 1.836 V2.5 V output 3.5 V < V
IN
< 5.5 V 2.450 2.5 2.5503.3 V output 4.3 V < V
IN
< 5.5 V 3.234 3.3 3.336I
GND
(2)
Ground pin current I
OUT
= 1 mA to 2 A 75 125 μA
ΔV
OUT
%/
Output voltage line regulation V
OUT
+ 1 V < V
IN
≤5 V 0.01 0.1 %/VV
OUT
(1), (2)
ΔV
OUT
%/ ΔI
OUT
Load regulation I
OUT
= 1 mA to 2 A 1 mVOutput noise voltageV
N
BW = 300 Hz to 50 V
OUT
= 1.5 V, C
OUT
= 100 μF 60 μV
RMSkHz
TPS75433QV
DO
Dropout voltage
(3)
I
OUT
= 2 A, V
IN
= 3.2 V 210 400 mVTPS75233QI
CL
Output current limit V
OUT
= 0 V 3.3 4.5 AShutdownT
SD
+150 °CtemperatureI
STBY
Standby current EN = V
IN
1 10 μAI
FB
FB input current TPS75x01Q FB = 1.5 V – 1 1 μAV
EN(HI)
High-level enable input voltage 2 VV
EN(LO)
Low-level enable input voltage 0.7 Vf = 100 Hz, C
OUT
= 100 μF,PSRR Power-supply ripple rejection
(2)
60 dBI
OUT
= 2 A, See
(1)
Minimum input voltage for valid I
OUT(RESET)
= 300 μA,
1 1.3 VRESET V
(RESET)
≤0.8 VTrip threshold voltage V
OUT
decreasing 92 98 %V
OUTRESET
Hysteresis voltage Measured at V
OUT
0.5 %V
OUT(TPS752xxQ)
Output low voltage V
IN
= 2.7 V, I
OUT(RESET)
= 1 mA 0.15 0.4 VLeakage current V
(RESET)
= 5.5 V 1 μARESET timeout delay 100 msMinimum input voltage for valid PG I
OUT(PG)
= 300 μA, V
(PG)
≤0.8 V 1.1 1.3 VTrip threshold voltage V
OUT
decreasing 80 86 %V
OUTPG
Hysteresis voltage Measured at V
OUT
0.5 %V
OUT(TPS754xxQ)
Output low voltage I
OUT(PG)
= 1mA 0.15 0.4 VLeakage current V
(PG)
= 5.5 V 1 μAEN = V
IN
– 1 1Input current ( EN) μAEN = 0 V – 1 0 1
(1) Minimum V
IN
= (V
OUT
+ 1 V) or 2.7 V, whichever is greater. Maximum V
IN
= 5.5 V.(2) If V
OUT
≤1.8 V, then V
IN(min)
= 2.7 V, V
IN(max)
= 5.5 V:
If V
OUT
≥2.5 V, then V
IN(min)
= V
OUT
+ 1 V, V
IN(max)
= 5.5 V:
(3) Input voltage equals V
OUT(Typ)
– 100 mV; TPS75x33Q input voltage must drop to 3.2 V for this test.
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FUNCTIONAL BLOCK DIAGRAMS
100 msDelay
(for Option)RESET
_
+
Vref =1.1834V
OUT
FB
EN
GND
PGor RESET
_
+
IN
Externaltothedevice
R1
R2
100 msDelay
(for Option)RESET
_
+
V =
ref 1.1834V
OUT
SENSE
EN
GND
PGor RESET
_
+
IN
R1
R2
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Adjustable Voltage Versions
Fixed-Voltage Versions
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PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND/HEATSINK
NC
IN
IN
EN
PGor RESET
OUTPUT
OUTPUT
GND/HEATSINK
GND/HEATSINK
NC
NC
GND
NC
NC
NC
NC
NC
GND/HEATSINK
FB/SENSE
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
TSSOP-20
PWP
(TOP VIEW)
Table 1. PIN DESCRIPTIONS
TPS754xxQ, TPS752xxQ
TSSOP-20 (PWP)NAME PIN NO. I/O DESCRIPTION
EN 5 I Negative polarity enable ( EN) inputAdjustable voltage version only; feedback voltage for setting output voltage ofFB/SENSE 7 I the device. Not internally connected on adjustable versions. Sense input forfixed options.GND 17 GroundGND/HEATSINK 1, 10, 11, 20 Ground/heatsinkIN 3, 4 I Input voltage2, 12, 13, 14,NC Not connected15, 16, 18, 19OUTPUT 8, 9 O Regulated output voltageTPS752xxQ devices only; open-drain RESET output.RESET/PG 6 O
TPS754xxQ devices only; open-drain power-good (PG) output.
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VIN
Vres
(1) Vres
t
t
t
VOUT
Threshold
Voltage
RESET
Output 100ms
Delay
100ms
Delay
Output
Undefined
Output
Undefined
VIT+
(2)
Lessthan5%ofthe
OutputVoltage
VIT+
(2)
VIT-
(2) VIT-
(2)
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
TPS752xxQ RESET Timing Diagram
(1) V
res
is the minimum input voltage for a valid RESET. The symbol V
res
is not currently listed within EIA or JEDECstandards for semiconductor symbology.(2) V
IT
: Trip voltage is typically 5% lower than the output voltage (95% V
OUT
). V
IT –
to V
IT+
is the hysteresis voltage.
TPS754xxQ Power Good Timing Diagram
(1) V
PG
is the minimum input voltage for a valid Power Good. The symbol V
PG
is not currently listed within EIA or JEDECstandards for semiconductor symbology.(2) V
IT
: Trip voltage is typically 17% lower than the output voltage (83% V
OUT
). V
IT –
to V
IT+
is the hysteresis voltage.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 7
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TYPICAL CHARACTERISTICS
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Table of Graphs
FIGURE NO.
vs Output Current Figure 3 ,Figure 4V
OUT
Output Voltage vs Junction Temperature Figure 5 ,Figure 6vs Time Figure 18I
GND
Ground Current vs Junction Temperature Figure 7PSRR Power-Supply Ripple Rejection vs Frequency Figure 8Output Spectral Noise Density vs Frequency Figure 9Z
OUT
Output Impedance vs Frequency Figure 10vs Input Voltage Figure 11V
DO
Dropout Voltage
vs Junction Temperature Figure 12V
IN
Input Voltage (Min) vs Output Voltage Figure 13LINE Line Transient Response Figure 14 ,Figure 16LOAD Load Transient Response Figure 15 ,Figure 17ESR Equivalent Series Resistance vs Output Current Figure 20 ,Figure 21
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TYPICAL CHARACTERISTICS
3.303
3.297
3.301
3.299
3.295
3.305
0500 1000 1500 2000
V OutputVoltage V- -
OUT
V =4.3V
T =+25 C
IN
J°
I OutputCurrent mA- -
OUT
VOUT
V =2.7V
T =+25 C
IN
J°
1.502
1.499
1.501
1.500
1.498
1.503
1.497
V OutputVoltage V- -
OUT
0500 1000 1500 2000
I OutputCurrent mA- -
OUT
VOUT
3.31
-50 0
3.33
150
3.35
3.29
50 100
3.25
3.27
3.23
3.37
V OutputVoltage V- -
OUT
T JunctionTemperature C
J- - °
1 mA
2 A
1.48
1.50
1.52
1.51
1.49
1.47
1.53
-40 10 16060 110
T JunctionTemperature C
J- - °
V OutputVoltage V- -
OUT
1 mA
2A
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Over operating temperature range (T
J
= – 40 °C to +125 °C) unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS75x33Q TPS75x15QOUTPUT VOLTAGE OUTPUT VOLTAGEvs OUTPUT CURRENT vs OUTPUT CURRENT
Figure 3. Figure 4.
TPS75x33Q TPS75x15QOUTPUT VOLTAGE OUTPUT VOLTAGEvs JUNCTION TEMPERATURE vs JUNCTION TEMPERATURE
Figure 5. Figure 6.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 9
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60
70
50
40
30
20
10
0
90
80
100
100k10k
1k10010 1M 10M
PSRR Power-SupplyRejectionRatio dB- -
f Frequency Hz- -
V =4.3V
C =100 F
1mA
T =+25
IN
OUT
J
m
I =
C
OUT
°
V =4.3V
C =100 F
2A
T =+25
IN
OUT
J
m
I =
C
OUT
°
90
70
60
80
85
75
65
55
50
V =5V
I =2A
IN
OUT
-40 10 16060 110
T JunctionTemperature C
J- - °
GroundCurrent A- m
10 100 1k 10k 50k
1.8
1.4
1.2
0.8
0.4
0
1.6
1.0
0.6
0.2
2.0
VVoltageNoise nV/- -
nHz
Ö
f Frequency Hz- -
V =4.3V
V =3.3V
F
T =+25
IN
OUT
J
C =100
C
OUT m
°
I =2A
OUT
I =1mA
OUT
100k10k
1k10010 1M 10M
f Frequency Hz- -
Z OutputImpedance-- W
OUT
101
1
10-1
10-2
C =100 F
I =2A
OUT
OUT
m
C =100 F
I =1mA
OUT
OUT
m
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C) unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS75xxxQ TPS75x33QGROUND CURRENT POWER-SUPPLY RIPPLE REJECTIONvs JUNCTION TEMPERATURE vs FREQUENCY
Figure 7. Figure 8.
TPS75x33Q TPS75x33QOUTPUT SPECTRAL NOISE DENSITY OUTPUT IMPEDANCEvs FREQUENCY vs FREQUENCY
Figure 9. Figure 10.
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0
3
200
150
100
3.52.5
50
4.5 5
250
300
350
4
V DropoutVoltage mV- -
DO
V InputVoltage V- -
IN
T =+25 C
J°
T =+125 C
J°
T = 40 C-
J°
IOUT =2A
0
200
150
100
50
250
300
VDropoutVoltage mV--
DO
-40 10 16060 110
T JunctionTemperature C
J- - °
IOUT =2A
IOUT =0.5A
IOUT =1.5A
3.0
2.7
2.01.5 1.75 2 2.25 2.5 2.75
4.0
3 3.25 3.5
T = 40 C-
A°
IOUT =2A
V InputVoltage(Min) V- -
IN
V OutputVoltage V- -
OUT
T =+25 C
A°
T =+125 C
A°
4
100
0
0
3
-100
VInputVoltage V- -
IN
D-
-
V Changein
OutputVoltage mV
OUT
t Time ms- -
0.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00.2
I =2A
C =100 F
V =1.5V
OUT
OUT
OUT
m
dV
dT =1V
sm
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C) unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS75x01Q TPS75x33QDROPOUT VOLTAGE DROPOUT VOLTAGEvs INPUT VOLTAGE vs JUNCTION TEMPERATURE
Figure 11. Figure 12.
INPUT VOLTAGE (MIN) TPS75x15Qvs OUTPUT VOLTAGE LINE TRANSIENT RESPONSE
Figure 13. Figure 14.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 11
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0
t Time ms- -
0.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.00.2
5.3
100
0
4.3
-100
VInputVoltage V- -
IN
D -
-
V Changein
OutputVoltage mV
OUT
I =2A
C =100 F(Tantalum)
V =3.3V
OUT
OUT
OUT
mdV
dT =1V
sm
0
1
2
0 1 2
0
50
-50
-100
-150
I OutputCurrent A- -
OUT
D -
-
V Changein
OutputVoltage mV
OUT
34 5 678910
t Time ms- -
I =2A
C =100 F(Tantalum)
V =1.5V
LOAD
LOAD
OUT
m
3.3
0
0
4.3
V =4.3V
T =+25 C
IN
J°
V OutputVoltage V- -
OUT
EnableVoltage V
-
0
t Time ms- -
0.4 0.6 0.8 1.00.2
0
1.5
0 1 2
0
50
-50
-100
-150
I OutputCurrent A- -
OUT
D -
-
V Changein
OutputVoltage mV
OUT
34 5 678910
t Time ms- -
I =2A
C =100 F(Tantalum)
V =3.3V
LOAD
LOAD
OUT
m
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C) unless otherwise noted. Typical values are at T
J
= +25 °C.
TPS75x15Q TPS75x33QLOAD TRANSIENT RESPONSE LINE TRANSIENT RESPONSE
Figure 15. Figure 16.
TPS75x33Q TPS75x33Q OUTPUT VOLTAGELOAD TRANSIENT RESPONSE vs TIME (AT STARTUP)
Figure 17. Figure 18.
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EN GND
ESR
ToLoad
VIN IN
OUT
COUT
+
RL
0.01
10
1
Region of Instability
0.1
Region of Stability
0.05
V =3.3V
C =100 F
4.3V
T =+25
OUT
OUT
J
m
V =
C
IN
°
ESR EquivalentSeriesResistance- - W
01.5
1.0
0.5
I OutputCurrent A- -
OUT
2.0
0.01
10
1
0.1
ESR EquivalentSeriesResistance- - W
Region of Instability
Region of Stability
V =3.3V
C =47 F
4.3V
T =+25
OUT
OUT
J
m
V =
C
IN
°
01.5
1.0
0.5
I OutputCurrent A- -
OUT
2.0
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)Over operating temperature range (T
J
= – 40 °C to +125 °C) unless otherwise noted. Typical values are at T
J
= +25 °C.
Test Circuit for Typical Regions of Stability (Figure 20 and Figure 21 ) (Fixed Output Options)
Figure 19.
TYPICAL REGION OF STABILITY TYPICAL REGION OF STABILITYEQUIVALENT SERIES RESISTANCE
(1)
EQUIVALENT SERIES RESISTANCE
(1)
vs OUTPUT CURRENT vs OUTPUT CURRENT
Figure 20. Figure 21.
(1). Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor,any series resistance added externally, and PWB trace resistance to C
OUT
.
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APPLICATION INFORMATION
Minimum Load Requirements
Pin Functions
Enable ( EN)
Power-Good (PG) — TPS754xxQ
Sense (SENSE)
Feedback (FB)
Reset ( RESET) — TPS752xxQ
GND/HEATSINK
Input Capacitor
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
The TPS752xxQ and TPS754xxQ devices include four fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V and3.3 V), and an adjustable regulator, the TPS75x01Q (adjustable from 1.5 V to 5 V).
The TPS752xxQ and TPS754xxQ families are stable even at zero load; no minimum load is required foroperation.
The EN terminal is an input that enables or shuts down the device. If EN is a logic high, the device is inshutdown mode. When EN goes to logic low, then the device is enabled.
The PG terminal is an open drain, active high output that indicates the status of V
OUT
(output of the LDO). WhenV
OUT
reaches 83% of the regulated voltage, PG goes to a high impedance state. It goes to a low-impedancestate when V
OUT
falls below 83% (that is, an overload condition) of the regulated voltage. The open drain outputof the PG terminal requires a pullup resistor.
The SENSE terminal of the fixed output options must be connected to the regulator output, and the connectionshould be as short as possible. Internally, SENSE connects to a high-impedance wide-bandwidth amplifierthrough a resistor-divider network, and noise pickup feeds through to the regulator output. It is essential to routethe SENSE connection in such a way to minimize/avoid noise pickup. Adding RC networks between the SENSEterminal and V
OUT
to filter noise is not recommended because these types of networks may cause the regulatorto oscillate.
FB is an input terminal used for the adjustable-output options and must be connected to an external feedbackresistor divider. The FB connection should be as short as possible. It is essential to route it in such a way tominimize/avoid noise pickup. Adding RC networks between FB terminal and V
OUT
to filter noise is notrecommended because these types of networks may cause the regulator to oscillate.
The RESET terminal is an open drain, active low output that indicates the status of V
OUT
. When V
OUT
reaches95% of the regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to alow-impedance state when V
OUT
is below 95% of the regulated voltage. The open-drain output of the RESETterminal requires a pullup resistor.
All GND/HEATSINK terminals are connected directly to the mount pad for thermal-enhanced operation. Theseterminals could be connected to GND or left floating.
For a typical application, an input bypass capacitor (0.22 μF to 1 μF) is recommended for device stability. Thiscapacitor should be as close to the input pins as possible. For fast transient conditions where droop at the inputof the LDO may occur because of high inrush current, it is recommended to place a larger capacitor at the inputas well. The size of this capacitor depends on the output current and response time of the main power supply, aswell as the distance to the load (LDO).
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Output Capacitor
ESR and Transient Response
C
RESR LESL
+
–
VIN
RESR
LDO
IOUT
VESR
COUT
RLOAD
VOUT
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
As with most LDO regulators, the TPS752xxQ and TPS754xxQ require an output capacitor connected betweenOUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 47 μF andthe ESR (equivalent series resistance) must be between 100 m Ωand 10 Ω. Solid tantalum electrolytic, aluminumelectrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements described inthis section. Larger capacitors provide a wider range of stability and better load transient response.
This information, along with the ESR graphs (see Figure 20 and Figure 21 ), is included to assist in selection ofsuitable capacitance for the user ’ s application. When necessary to achieve low height requirements along withhigh output current and/or high load capacitance, several higher ESR capacitors can be used in parallel to meetthese guidelines.
LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitorsare used to support the load current while the LDO amplifier is responding. In most applications, one capacitor isused to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances areresistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and theinductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of anycapacitor can therefore be drawn as shown in Figure 22 .
Figure 22. ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following applicationfocuses mainly on the parasitic resistance ESR..
Figure 23 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
Figure 23. LDO Output Stage With Parasitic Resistances ESR and ESL
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Conclusion
ESR 1
ESR 2
ESR 3
3
2
1
t1t2
IOUT
VOUT
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
In steady state operation (dc state condition), the load current is supplied by the LDO (solid arrow) and thevoltage across the capacitor is the same as the output voltage (V(C
OUT
) = V
OUT
). This condition means that nocurrent is flowing into the C
OUT
branch. If I
OUT
suddenly increases (that is, a transient condition), the followingevents occur:•The LDO is not able to supply the sudden current need because of its response time (t
1
in Figure 24 ).Therefore, capacitor C
OUT
provides the current for the new load condition (the dashed arrow). C
OUT
now actslike a battery with an internal resistance, ESR. Depending on the current demand at the output, a voltagedrop occurs at R
ESR
. This voltage is shown as V
ESR
in Figure 23 .•When C
OUT
is conducting current to the load, initial voltage at the load is V
OUT
= V(C
OUT
) – V
ESR
. As a resultof the discharge of C
OUT
, the output voltage V
OUT
drops continuously until the response time t
1
of the LDO isreached and the LDO resumes supplying the load. From this point, the output voltage starts rising again untilit reaches the regulated voltage. This period is shown as t
2
in Figure 24 .
Figure 24 also shows the impact of different ESRs on the output voltage. The left brackets show different levelsof ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From the above discussion, the following conclusions can be drawn:•The higher the ESR, the larger the droop at the beginning of load transient.•The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during theLDO response period.
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support theminimum output voltage requirement.
Figure 24. Correlation of Different ESRs and Their Influence to the Regulation of V
OUT
at a Load StepFrom Low-to-High Output Current
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Programming the TPS75x01Q Adjustable LDO Regulator
V =V ´
OUT ref
(1+)
R
R
1
2
(1)
R =( 1) R-
1 2
´
V
V
OUT
ref
(2)
IN
EN
GND
FB/SENSE
OUT
PG/
RESET PGor OutputRESET
VOUT
VIN
0.22 Fm250kW
TPS75x01Q
COUT
R1
R2
> 2.0V
< 0.7V
OUTPUTVOLTAGE
PROGRAMMINGGUIDE
R1R2UNIT
OUTPUT
VOLTAGE
2.5V
3.3V
3.6V
33.2
53.6
61.9
30.1
30.1
30.1
kW
kW
kW
NOTE:Toreducenoiseandpreventoscillation,
R andR mustbeascloseaspossibletothe
FB/SENSEterminal.
1 2
Regulator Protection
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
The output voltage of the TPS77x01Q adjustable regulator is programmed using an external resistor divider asshown in Figure 25 . The output voltage is calculated using Equation 1 :
Where:
•V
ref
= 1.1834 V typ (the internal reference voltage)
Resistors R
1
and R
2
should be chosen for approximately 40 μA divider current. Lower value resistors can beused, but offer no inherent advantage and waste more power. Higher values should be avoided as leakagecurrents at FB increase the output voltage error. The recommended design procedure is to choose R
2
= 30.1 k Ωto set the divider current at approximately 40 μA and then calculate R
1
using Equation 2 :
Figure 25. TPS75x01Q Adjustable LDO Regulator Programming
The TPS752xxQ and TPS754xxQ PMOS-pass transistors have a built-in back diode that conducts reversecurrents when the input voltage drops below the output voltage (for example, during power down). Current isconducted from the output to the input and is not internally limited. When extended reverse voltage is anticipated,external limiting may be appropriate.
The TPS752xxQ and TPS754xxQ also feature internal current limiting and thermal protection. During normaloperation, the TPS752xxQ and TPS754xxQ limit output current to approximately 3.3 A. When current limitingengages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting isdesigned to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of thepackage. If the temperature of the device exceeds +150 °C (typ), thermal-protection circuitry shuts it down. Oncethe device has cooled below +130 °C (typ), regulator operation resumes.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 17
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Power Dissipation and Junction Temperature
P =
D(Max)
T T
R
-
J(Max) A
JAq
(3)
P =(V V ) I-
D IN OUT OUT
´
(4)
THERMAL INFORMATION
Thermally-Enhanced TSSOP-20 (PWP – PowerPAD)
DIE
(a) Side View
(b) End View
(c) Bottom View
DIE
Thermal
Pad
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Specified regulator operation is assured to a junction temperature of +125 °C; the maximum junction temperatureshould be restricted to +125 °C under normal operating conditions. This restriction limits the power dissipation theregulator can handle in any given application. To ensure the junction temperature is within acceptable limits,calculate the maximum allowable dissipation, P
D(max)
, and the actual dissipation, P
D
, which must be less than orequal to P
D(max)
.
The maximum-power-dissipation limit is determined using Equation 3 :
where:
•T
J(max)
is the maximum allowable junction temperature•R
θJA
is the thermal resistance junction-to-ambient for the package; that is, 34.6 °C/W for the 20-terminal PWPwith no airflow (see Dissipation Ratings Table ).•T
A
is the ambient temperature
The regulator dissipation is calculated using Equation 4 :
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermalprotection circuit.
The thermally-enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [seeFigure 26 (c)] to provide an effective thermal contact between the IC and the printed wiring board (PWB).
Figure 26. Views of Thermally-Enhanced PWP Package
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-downTO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.These packages, however, suffer from several shortcomings: they do not address the very low profilerequirements (less than 2 mm) of many of today ’ s advanced systems, and they do not offer a pin-count highenough to accommodate increasing integration. On the other hand, traditional low-power surface-mountpackages require power dissipation derating that severely limits the usable range of many high-performanceanalog circuits.
The PWP package (a thermally-enhanced TSSOP) combines fine-pitch surface-mount technology with thermalperformance comparable to much larger power packages.
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100
75
50
25
150
0.3
Natural Convection
50 ft/min
250 ft/min
300ft/min
100 ft/min
150ft/min
200ft/min
R ThermalResistance
- -
qJA C/W
°
CopperHeatsinkArea cm-2
01 2 345678
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
The PWP package is designed to optimize the heat transfer to the PWB. Because of the very small size andlimited mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction pathsthat remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending)and manufacturing technique to provide the user with direct connection to the heat-generating IC. When this padis soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultra-thin, fine-pitch,surface-mount package can be reliably achieved.
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermalconsiderations in the PWB design. For example, simply adding a localized copper plane (heatsink surface) that iscoupled to the thermal pad enables the PWP package to dissipate 2.5 W in free air (see Figure 28 (a), 8 cm
2
ofcopper heatsink and natural convection). Increasing the heatsink size increases the power dissipation range forthe component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly(see Figure 27 and Figure 28 ). The line drawn at 0.3 cm
2
in Figure 27 and Figure 28 indicates performance atthe minimum recommended heatsink size, illustrated in Figure 30 .
The thermal pad is directly connected to the substrate of the IC, which for the TPS752xxQPWP andTPS754xxQPWP series is a secondary electrical connection to device ground. The heat-sink surface that isadded to the PWP can be a ground plane or left electrically isolated. In TO220-type surface-mount packages, thethermal connection is also the primary electrical connection for a given terminal which is not always ground. ThePWP package provides up to 16 independent leads that can be used as inputs and outputs. (Note: leads 1, 10,11, and 20 are internally connected to the thermal pad and the IC substrate.)
Figure 27. Thermal Resistance vs Copper Heatsink Area
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 19
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300 ft/min
150 ft/min
Natural Convection
(b)
300 ft/min
150ft/min
Natural Convection
(c)
1.0
0.5
3.0
0
2.0
1.5
2.5
3.5
300 ft/min
150ft/min
Natural Convection
(a)
0.3
CopperHeatsinkArea cm-2
02 4 68
P PowerDissipationLimit W
- -
D
T =+25 C
A°T =+55 C
A°
T =+105 C
A°
1.0
0.5
3.0
0
2.0
1.5
2.5
3.5
0.3
CopperHeatsinkArea cm-2
02 4 68
PPowerDissipationLimit W- -
D
0.3
CopperHeatsinkArea cm-2
02 4 68
P PowerDissipationLimit W
- -
D
1.0
0.5
3.0
0
2.0
1.5
2.5
3.5
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Figure 28. Power Ratings of the PWP Package at Ambient Temperatures of +25 °C, +55 °C, and +105 °C
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Board thickness 62 mils(0.15748cm)
Boardsize 3.2in.x3.2in.
Boardmaterial FR4
Coppertrace/heatsink 1 oz
Exposedpadmounting 63/67tin/lead(Sn/Pb)solder
Heatsink Area
1ozCopper
P =
D(Max)
T T
R
-
J(Max) A
JA (System)q
(5)
P =(V V ) I +V I-
D(total) IN OUT OUT IN Q
´ ´
(6)
P =(V V ) I-
D(total) IN OUT OUT
´
(7)
P =
D(Max)
T T
R
-
J(Max) A
JA (System)q
= =1.4W
125 -
°C°
°
C
C/W
55
50
(8)
P =(V V ) I-
D(total) IN OUT OUT
´=(5 3.3) 0.8=1.36W-´
(9)
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
Figure 29 is an example of a thermally-enhanced PWB layout for use with the new PWP package. This boardconfiguration was used in the thermal experiments that generated the power ratings shown in Figure 27 andFigure 28 . As discussed earlier, copper has been added on the PWB to conduct heat away from the device. R
θJAfor this assembly is illustrated in Figure 27 as a function of heatsink area. A family of curves is included toillustrate the effect of airflow introduced into the system.
Figure 29. PWB Layout (Including Copper Heatsink Area) for Thermally-Enhanced PWP Package
From Figure 27 , R
θJA
for a PWB assembly can be determined and used to calculate the maximumpower-dissipation limit for the component/PWB assembly, with the equation:
Where T
Jmax
is the maximum specified junction temperature (+150 °C absolute maximum limit, +125 °Crecommended operating limit) and T
A
is the ambient temperature.
P
D(max)
should then be applied to the internal power dissipated by the TPS75433QPWP regulator. The equationfor calculating total internal power dissipation of the TPS75433QPWP is:
Because the quiescent current of the TPS75433QPWP is very low, the second term is negligible, furthersimplifying the equation to:
For the case where T
A
= +55 °C, airflow = 200 ft/min, copper heat-sink area = 4 cm
2
, the maximumpower-dissipation limit can be calculated. First, from Figure 27 , we find the system R
θJA
is 50 °C/W; therefore, themaximum power-dissipation limit is:
If the system implements a TPS75433QPWP regulator, where V
IN
= 5 V and I
OUT
= 800 mA, the internal powerdissipation is:
Comparing P
D(total)
with P
D(max)
reveals that the power dissipation in this example does not exceed the calculatedlimit. When it does, one of two corrective actions should be made: either raise the power-dissipation limit byincreasing the airflow or the heat-sink area, or loweri the internal power dissipation of the regulator by reducingthe input voltage or the load current. In either case, the above calculations should be repeated with the newsystem parameters.
Copyright © 2000 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 21
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Mounting Information
Location ofExposed
ThermalPadon
PWPPackage
MinimumRecommended
HeatsinkArea
TPS752xxQ
TPS754xxQ
SLVS242C – MARCH 2000 – REVISED OCTOBER 2007
The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. Thethermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The dataincluded in Figure 27 and Figure 28 are for soldered connections with voiding between 20% and 50%. Thethermal analysis shows no significant difference resulting from the variation in voiding percentage.
Figure 30 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink areais also illustrated. This is simply a copper plane under the body extent of the package, including metal routedunder terminals 1, 10, 11, and 20.
Figure 30. PWP Package Land Pattern
22 Submit Documentation Feedback Copyright © 2000 – 2007, Texas Instruments Incorporated
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS75201QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75201QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75201QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75201QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75215QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75215QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75215QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75215QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75218QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75218QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75218QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75218QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75225QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75225QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75225QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75225QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75233QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75233QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75233QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75233QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75401QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75401QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75401QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75401QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75415QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS75415QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75415QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75415QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75418QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75418QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75418QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75418QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75425QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75425QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75425QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75425QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75433QPWP ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75433QPWPG4 ACTIVE HTSSOP PWP 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75433QPWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS75433QPWPRG4 ACTIVE HTSSOP PWP 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS75201, TPS75215, TPS75218, TPS75225, TPS75233 :
•Automotive: TPS75201-Q1,TPS75215-Q1,TPS75218-Q1,TPS75225-Q1,TPS75233-Q1
•Enhanced Product: TPS75201-EP,TPS75215-EP,TPS75218-EP,TPS75225-EP,TPS75233-EP
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS75201QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75215QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75218QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75225QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75233QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75401QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75415QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75418QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75425QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
TPS75433QPWPR HTSSOP PWP 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS75201QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75215QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75218QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75225QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75233QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75401QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75415QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75418QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75425QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
TPS75433QPWPR HTSSOP PWP 20 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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