AUIRS2181(4)S
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Features
• Floating channel designed for bootst rap operation
• Fully operatio nal to +600 V
• Tolerant to negative transient voltage, dV/dt immune
• Gate drive supply range from 10 V to 20 V
• Undervoltage l ock out for both channels
• 3.3 V and 5 V input l ogi c compatible
• Matched propagation delay for both channels
• Logic and power ground +/- 5 V offset
• Lower di/dt gat e driver for better noise immunity
• Output source/sink current capabi l i ty (typical) 1.9 A /2.3 A
• Leadfree, RoHS compliant
• Automotive qualif i ed*
Typical Applications
• Piezo/ common rail Injection
• Starter/Alternator
• Electric Power Steering
• Fan and compressor
Product Summary
Topology High and Low Side Driver
V
OFFSET
≤ 600 V
V
OUT
10 V – 20 V
I
o+
& I
o-
(typical) 1.9 A &2.3 A
tON & tOFF (typical) 160 ns & 200 ns
Package Options
Typical Connection
8-Lead SOIC 14-Lead SOIC
AUIRS2181S Narrow Body
AUIRS21814S
Vcc
HIN
LIN
COM
HO
LO
Up to 600V
Vcc
HIN
LIN
AUIRS2181
TO
LOAD
Vcc
HIN
LIN
COM
HO
LO
Up to 600V
Vcc
LIN
HIN
AUIRS21814
TO
LOAD
VssVss
(Refer to Lead Assignments for correct pin
configuration). This/These diagram(s) show
electrical connections only. Please refer to our
Application Notes and Design Tips for proper
circuit board layout.
V
B
V
S
V
B
V
S
AUIRS2181(4)S
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Ordering Informati on
Base Part Number Package Type
Standard Pack
Complete Part Number
Form
Quantity
AUIRS2181S SOIC8 Tube/Bulk 95 AUIRS2181S
Tape and Reel 2500 AUIRS2181STR
AUIRS21814S SOIC14N Tube/Bulk 55 AUIRS21814S
Tape and Reel 2500 AUIRS21814STR
AUIRS2181(4)S
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Description
The AUIRS2181(4)(S) are high voltage, high speed power MOSFET and IGBT drivers with independent high
and low-side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output,
down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the
high-side configurat ion which operates up to 600 V.
Feature Comparison: AUIRS2181/AUIRS2183/AUIRS2184
Part
Input
Logic
Cross-
Conduction
Prevention
logic
Dead-Time
Ground
Pins
Ton/Toff
2181
HIN/LIN
no
none
COM
160/200 ns
21814
VSS/COM
2183
HIN/LIN
yes
Internal 500ns
COM
160/200 ns
21834
Programmable 0.4 – 5 us
VSS/COM
2184
IN/SD
yes
Internal 500ns
COM
600/230 ns
21844
Programmabl e 0.4 – 5 us
VSS/COM
AUIRS2181(4)S
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Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All
voltage parameters are absolute voltages referenced to COM lead. Stresses beyond those listed under "
Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only;
and functional operation of the device at these or an
y other condition beyond those indicated in the
“Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-
rated conditions for
extended periods may affect device reliability. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise
specified.
Symbol
Definition
Min
Max
Units
VB High-side floati ng absolute voltage -0.3 625
V
VS
High-side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High-side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low-side and l ogi c fixed supply volt age
-0.3
20 (†)
VLO
Low-side output voltage
-0.3
VCC + 0.3
VIN
Logic input voltage (HIN &LIN)
VSS -0.3
VCC + 0.3
VSS
Logic ground (AUIRS21814(S) only)
VCC - 20
VCC + 0.3
dVS/dt
Allowable offset supply voltage transient
—
50
V/ns
PD Package power dissipation @ TA ≤ 25°C
(8 lead SOIC)
— 0.625 W
(14 lead SOIC)
— 1.0
RthJA Thermal resistance, j unction to ambient
(8 lead SOIC)
— 200 °C/W
(14 lead SOIC)
— 120
TJ
Junction temperat ure
—
150
°C
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
—
300
† All supplies are ful l y tested at 25 V and an internal 20 V clamp exi st s f or each supply.
Recommended Operating Condi t ions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used
within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15 V
differential.
†† Logic operati onal for VS of -5 V to +600 V. Logi c state held for VS of -5 V to –VBS. (Please refer t o the
Design Tip DT97-3 for mo re details).
Symbol
Definition
Min
Max
Units
VB
High-side floating supply absolute voltage
VS +10
VS +20
V
VS
High-side floating supply offset voltage
(††)
600
VHO
High-side floating output voltage
VS
VB
VCC
Low-side and l ogi c fixed supply volt age
10
20
VLO
Low-side output voltage
0
VCC
VIN
Logic input voltage
VSS
VCC
DT
Programmabl e deadtime pin voltage
VSS
VCC
VSS
Logic ground
-5
5
TA
Ambient temperature
-40
125
°C
AUIRS2181(4)S
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Dynamic Electrical Character i stics
Unless otherwise noted, these specifi cations apply for an operating junction temperature range of -40°C ≤ Tj
≤ 125°C with bias condit ion s of VBIAS (VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF.
Symbol
Definition
Min
Typ
Max
Units
Test Conditions
ton
Turn-on propagation delay
—
160
270
ns
VS = 0 V
toff
Turn-off propagati on delay
—
200
330
VS = 0 V or 600 V
MT
Delay matching, HS & LS turn-on/off
—
—
35
t r
Turn-on rise time
—
15
60
VS = 0 V
tf
Turn-off fall time
—
15
35
Static Electrical Characteristics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj
≤ 125°C with bias conditions of VBIAS (VCC, VBS) = 15 V, VSS = COM. The VIL, VIH and IIN parameters are
referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO, IO and Ron
parameters are referenced to COM and are applicable to the res pective output lead s: HO and LO.
(†) Guaranteed by design
(††) IO+ and IO- decrease with rising t em perature
Symbol Definition Min
Typ Max Units Test Conditions
VIH
Logic “1” input vol tage
2.5
—
—
V
VCC = 10 V to 20 V
VIL
Logic “0” input voltage
—
—
0.8
VCC = 10 V to 20 V
VOH
High level output voltage, VBIAS - VO
—
—
1.4
IO = 0 mA
VOL
Low level output voltage, VO
—
—
0.2
IO = 20 mA
ILK
Offset supply leakage current
—
—
50
µA
VB = VS = 600 V
IQBS
Quiescent VBS supply current
15
60
150
VIN = 0 V or 5 V
IQCC
Quiescent VCC supply current
15
120
240
IIN+
Logic “1” input bi as cu rrent
—
25
60
VIN = 5 V
IIN-
Logic “0” input bi as cu rrent
—
—
5.0
VIN = 0 V
V
CCUV+
VBSUV+
V
CC
and V
BS
supply undervolt age positive
going threshold
8.0 8.9 9.8
V
V
CCUV-
VBSUV-
V
CC
and V
BS
supply undervolt age negative
going threshold
7.4 8.2 9.0
V
CCUVH
VBSUVH
VCC and VBS supply underv ol tage Hysteresis 0.3 0.7 —
IO25+(†) Output high short circuit pulsed current 1.4 1.9 —
A
V
O
= 0V,
PW ≤ 10us,
TJ = 25°C
IO25-(†) Output low short circuit pulsed current 1.8 2.3 —
V
O
= 15V,
PW ≤ 10us,
TJ = 25°C
IO+(†)(††) Output high short circui t pulsed current 1.2 — —
V
O
= 0 V,
PW ≤ 10 us
IO-(†)(††) Output low short circuit pulsed current 1.5 — —
V
O
= 15 V,
PW ≤ 10 us
AUIRS2181(4)S
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Lead Definitions: AUIRS2181(4)S
Symbol
Description
HIN
Logic input for high-side gate driver out put (HO), in phase
LIN
Logic input for low-side driver output (LO), in phase
VSS
Logic ground (AUIRS21814 only)
VB
High-side floating supply
HO
High-side gate drive out put
VS
High-side floating supply return
VCC
Low-side and l ogi c fixed supply
LO
Low-side gate drive output
COM
Low-side retu rn
Lead Assignments: AUIRS2181(4)S
8 Lead SOIC
8
7
6
5
V
CC
V
B
HIN1
2
3
4
V
S
HO
LO
LIN
COM
14
13
12
V
CC
V
B
HIN
1
V
S
HO
LIN
COM
4
5
7
6
2
3
LO
V
SS
11
10
9
8
AUIRS2181S AUIRS21814S
14 Lead SOIC
Narrow Body
AUIRS2181(4)S
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Application Inform ation and Addi tional Details
HIN
LIN
HO
LO
50%
10%
90%
t
r
HIN
HO
90%
10%
50%
t
f
t
on
t
off
LIN
LO
50%
10%
90%
MT
LIN
LO HO
50%
HO
MT
HIN
LO
Figure 1. Input/Output Tim i ng Diagram
Figure 2. Switching Time Waveform Definitions
Figure 3. Delay Matching Waveform Definitions
AUIRS2181(4)S
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Parameter Trends vs. Temperature and vs. Supply Voltage
Figures of this chapter provide information on the experimental performanc e of the AUIRS2181(4)S HVIC.
The line plotted in each figure is generated from actual l ab data.
A large number of i ndi vidual samples were tested at three temperatures (-40 ºC, 25 º C, and 125 ºC) in order
to generate the experimental curve. The line co nsists of three data poi nts (one data point at each of the
tested temperatures) that have been connected together to illustrate t he understood trend. The indi vidual
data points on the Typ. curve were determined by cal culating the averag ed experimental value of the
parameter (fo r a given temperature).
A different set of individual samples was used to generate curves of parameter tre nds vs. supply volt age.
120
150
180
210
240
-50 -25 025 50 75 100 125
Temperat ure (oC)
Turn-on P ropagati on Del ay (ns)
Typ.
Max.
Min.
Figure 1A. Turn-On Propagation Delay vs. T em perature
Figure 1B. Turn-On Propagation Delay vs. Supply Voltage
150
190
230
270
310
-50 -25 025 50 75 100 125
Temperat ure (
o
C)
Turn-of f Propagat i on Del ay (ns)
Typ.
Max.
Min.
Figure 2A. Turn-Off Propagation Delay vs. Temper at ure
Figure 2B. Turn-Off Propagation Delay vs. Supply Voltage
AUIRS2181(4)S
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12
14
16
18
20
-50 -25 025 50 75 100 125
Temperat ure (
o
C)
Turn-Off fall T i m e (ns) -
Typ.
Max.
Min.
Figure 3A. Turn-Off Fall Time vs. Temperature
Figure 3B. Turn-Off Fall Time vs . Supply Voltage
Figure 4. Turn-On Rise Time vs. Temperature
0.3
0.6
0.9
1.2
1.5
-50 -25 025 50 75 100 125
Temperat ure (oC)
High Level O ut put (V )
Typ.
Max.
Min.
Figure 5. High Level Output Voltage vs. Temperature (Io =
0mA)
40
45
50
55
60
65
-50 -25 025 50 75 100 125
Temperat ure (
o
C)
Low Lev el Output (m V )
Typ.
Max.
Min.
Figure 6. Low Level Output vs. Temperature
Figure 7. Offset Supply Leakage Current vs. Temperature
AUIRS2181(4)S
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Figure 8A VBS Supply Current vs. Temperature
Figure 8B VBS Supply Current vs. VBS Floating Supply
Voltage
Figure 9A VCC Supply Current vs Temperature
Figure 9B VCC Supply Current vs. VCC Supply Voltage
15
20
25
30
35
-50 -25 025 50 75 100 125
Temperat ure (
o
C)
Logic " 1" Input Bias Current (uA )
Typ.
Max.
Min.
Figure 10. Log ic “1” Input Bias vs Temperature
-0.25
-0.23
-0.21
-0.19
-0.17
-0.15
-50 -25 025 50 75 100 125
Temperat ure (
o
C)
Logic "0" Input Bi as Current (uA ).
Typ.
Max.
Min.
Figure 11. Log ic “0” Input Bias vs Temperature
AUIRS2181(4)S
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Figure 12. VCC and VBS Undervoltage Threshold(+) vs
Temperature
Figure 13. VCC and VBS Undervoltage Threshold(-) vs
Temperature
Figure 14A. Output Source Current vs Temperature
Figure 14B. Output Source Current vs Supply Voltage
Figure 15A. Output Sink Current vs Temperature
Figure 15B. Output Sink Current vs Supply Voltage
AUIRS2181(4)S
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Negative Vs Safety Operating Ar ea (negVs SOA)
There could be conditions in which Vs node falls below (i.e. negative) VSS/COM nodes (e.g. because of
wrong system layout). This condition should be avoided because it could bring to uncontrolled behavior of
the driver.
The negVs SOA identifies the energy of negative Vs pulses at which the driver can withstand; pulse energy
is identified as the product of pulse duration by its amplitude. Fig. 16 shows the negVs SOA of
AUIRS2181(4)S at both ambient and over temperature conditions. Test conditions were VCC=VBS=15V
referenced to VSS=COM.
Even though the AUIRS2181(4)S has been designed and tested to handle these negative VS transient
conditions, it is highly recommended that the circuit designer always limit the negative VS transients as much
as possible by careful P CB layout and compon ent use.
Fig. 16 Negative Vs SOA of AUIRS2181(4)S.
AUIRS2181(4)S
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Tape and Reel Details: SOIC8
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
CARRIER TAPE DIMENSION FOR 8SOICN
Code Min Max Min Max
A7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C11.70 12.30 0.46 0.484
D5.45 5.55 0.214 0.218
E6.30 6.50 0.248 0.255
F5.10 5.30 0.200 0.208
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
Metric
Imperial
REEL DIMENSIONS FOR 8SOICN
Code Min Max Min Max
A329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E98.00 102.00 3.858 4.015
Fn/a 18.40 n/a 0.724
G14.50 17.10 0.570 0.673
H12.40 14.40 0.488 0.566
Metric
Imperial
AUIRS2181(4)S
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Tape and Reel Details: SOIC14N
CARRIER TAPE DIMENSION FOR 14SOICN
Code Min Max Min Max
A7.90 8.10 0.311 0.318
B 3.90 4.10 0.153 0.161
C15.70 16.30 0.618 0.641
D7.40 7.60 0.291 0.299
E6.40 6.60 0.252 0.260
F9.40 9.60 0.370 0.378
G1.50 n/a 0.059 n/a
H1.50 1.60 0.059 0.062
REEL DIMENSIONS FOR 14SOICN
Code Min Max Min Max
A329.60 330.25 12.976 13.001
B20.95 21.45 0.824 0.844
C12.80 13.20 0.503 0.519
D1.95 2.45 0.767 0.096
E98.00 102.00 3.858 4.015
Fn/a 22.40 n/a 0.881
G18.50 21.10 0.728 0.830
H16.40 18.40 0.645 0.724
Metric
Imperial
Metric
Imperial
E
F
A
C
D
G
A
B
H
NOTE : CONTROLLING
DIMENSION IN MM
LOADED TAPE FEED DIRECTION
A
H
F
E
G
D
B
C
AUIRS2181(4)S
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Part Marking Information
SOIC8:
AS2181
IR logo
AYWW ?
Part number
Date code
Pin 1
Identifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
? XXXX
MARKING CODE
Lead Free Released
Non-Lead Free Released
?
P
SOIC14N:
AUIRS21814S
IR logo
AYWW ?
Part number
Date code
Pin 1
Identifier
Lot Code
(Prod mode –
4 digit SPN code)
Assembly site code
Per SCOP 200-002
? XXXX
MARKING CODE
Lead Free Released
Non-Lead Free Released
?
P
AUIRS2181(4)S
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Qualification Informati on†
Qualification Level
Automotive
(per AEC-Q100††)
Comments: This family of ICs has passed an
Automotive qualification.
IR’s Industrial and Consumer
qualification level is granted by extension of the higher
Automotive lev el .
Moisture Sensiti vity Level SOIC8 MSL3††† 260°C
(per IPC/JEDEC J-STD-020)
SOIC14N MSL3††† 260°C
(per IPC/JEDEC J-STD-020)
ESD
Machine Model
Class M2 (Pass +/-150V)
(per AEC-Q100-003)
Human Body Model
Class H1B (Pass +/-1000V)
(per AEC-Q100-002)
Charged Device Model
Class C4 (Pass +/-1000V)
(per AEC-Q100-011)
IC Latch-Up Test
Class II, Level A††††
(per AEC-Q100-004)
RoHS Compliant
Yes
†
Qualification st andards can be found at International Rectifier’s web sit e http://www.irf.com/
††
Exceptions to AEC-Q100 requirements are noted i n the qualification report.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact
your International Rectifier sales representative for f urther information.
††††
HIN, LIN Class II Level B at 80mA per JESD78.
AUIRS2181(4)S
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IMPORTANT NOTICE
Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR)
reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and
services at any time and to discontinue any product or services without notice. Part numbers designated with the “AU”
prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance and
process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time of order
acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with
IR’s standard warranty. Testing and other quality control techniques are used to the extent IR deems necessary to
support this warranty. Except where mandated by government requirements, testing of all parameters of each product is
not necessaril y performed.
IR assumes no liability for applications assistance or customer product design. Customers are responsible for their
products and applications using IR components. To minimize the risks with customer products and applications,
customers should provide adequate design and operating safeguards.
Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration and
is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with
alterations is an unfair and deceptive business practice. IR is not responsible or liable for such altered documentation.
Information of third parties may be subject to additional restrictions.
Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that product or
service voids all express and any implied warranties for the associated IR product or service and is an unfair and
deceptive business practice. IR is not responsible or liabl e for any such statem ents.
IR products are not designed, intended, or authorized for use as components in systems intended for surgical implant into
the body, or in other applications intended to support or sustain life, or in any other application in which the failure of the
IR product could create a situation where personal injury or death may occur. Should Buyer purchase or use IR products
for any such unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that IR was negligent regarding the design or manufacture of
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IR products are neither designed nor intended for use in military/aerospace applications or environments unless the IR
products are specifically designated by IR as military-grade or “enhanced plastic.” Only products designated by IR as
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legal and regulatory requirements in connection with such use.
IR products are neither designed nor intended for use in automotive applications or environments unless the specific IR
products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the
designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in automotive
applications, I R wil l not be responsible fo r any failure to meet such requirements.
For technical support, please contac t IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
AUIRS2181(4)S
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Revision History
Date
Comment
04/29/08
Draft
5/6/08
Converted to new automotive format
9/30/08
Reviewed and updated various missing information
10/01/08
Inserted Input /Output Pin Equivalent Circuit Diagram
Feb, 10th, 2009
Typ application list and other minor changes
Feb. 11, 2009
Removed PDIP pack age versions from datas heet
Aug. 4, 2009
Updated quali fication information, characterization curves
Aug. 11, 2009
Updated plot, rem oved characterization graphs, changes package type info
Aug. 13, 2009
Updated VIH/VIL graphs
Sep 23rd, 2009
Typ appl. Secti on update; Rearranged graphs with temperature and supply cha racteristic,
updated marking detail with p/n; added ESD passing voltage; update LU test passing current
from 40mA to 80m A .
Dec. 16, 09
Changed Iqcc/I qbs m in to 15uA; added Im portant Notice page; ch anged ton typ=160ns; toff
typ=200ns; tr typ=15ns; tf typ=15ns
Feb. 24, 2010
Page 6: Added IO25+ and I O25- specification and the notes
Jul. 27, 2010
clamp diode values changed from 25V i nto 20V (in-out pin eq. cir c. diagrams)
Mar 07, 2012
Input zener clamp not e deleted in recommended op cond
Sept. 30th, 2013
Added negVs SOA
Oct. 04th, 2013
Adapted to new format
Jan. 10, 2014
Updated datasheet to display respectiv e page number on bottom left corner of every page
