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FEATURES
DPrecision Fault Threshold
DCharge Pump for Low RDS(on) High Side
Drive
DDifferential Sense Inputs
DProgrammable Average Power Limiting
DProgrammable Linear Current Control
DProgrammable Fault Time
DFault Output Indicator
DManual and Automatic Reset Modes
DShutdown Control With Programmable
Softstart
DUndervoltage Lockout
DElectronic Circuit Breaker Function
DESCRIPTION
The UCC3919 family of hot swap power
managers provide complete power management,
hot swap, and fault handling capability. The
UCC3919 features a duty ratio current limiting
technique, which provides peak load capability
while limiting the average power dissipation of the
external pass transistor during fault conditions.
The UCC3919 has two reset modes, selected with
the TTL/CMOS compatible L/R pin. In one mode,
when a fault occurs the IC repeatedly tries to reset
itself at a user defined rate, with user defined
maximum output current and pass transistor
power dissipation. In the other mode the output
latches off and stays off until either the L/R pin is
reset or the shutdown pin is toggled. The on board
charge pump circuit provides the necessary gate
voltage for an external N-channel power FET.
TYPICAL APPLICATION DIAGRAM
UDG−01068
+
VDD
GND
LINEAR
CURRENT AMP
TIMER
CT CAP
RS
IBIAS
IMAX
CSN GATE
FROM
SUPPLY
3 V TO 8 V TO LOAD
CSP
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
Copyright 2001 − 2005, Texas Instruments Incorporated
SLUS374C − JULY 1999 − REVISED NOVEMBER 2005
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AVAILABLE OPTIONS
TJ
PACKAGE DEVICES
T
JD PACKAGE N PACKAGE PW PACKAGE
0°C to 70°C UCC3919D UCC3919N UCC3919PW
−40°C to 85°C UCC2919D UCC2919N UCC2919PW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
IMAX
IBIAS
N/C
CAP
L/R
SD
FLT
CSP
VDD
CSN
GND
GATE
PL
CT
N PACKAGE
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IMAX
IBIAS
N/C
CAP
L/R
SD
N/C
FLT
CSP
VDD
CSN
GND
GATE
PL
N/C
CT
D AND PW PACKAGES
(TOP VIEW)
functional block diagram
10
7
5 6
11
8
9
2
1
12
14
4
GND
CHARGE
PUMP
DRIVER
UVLO
VDD
+
−
UVLO
+
−
+
+
−
200mV
LINEAR
CURRENT
AMPLIFIER
OVERLOAD
COMPARATOR
S
R
Q
Q
RESET
DOMINANT
SET
DOMINANT
+
−
+
−
1.5V
0.5V
1.2µA
+
+1.5v
13 VDD
36µA
50mV
VDD
CSP
CSN
IMAX
IBIAS
PL
CT
FLT
GATE
CAP
LR SD
UVBIAS
VDD
1X
OVERCURRENT
COMPARATOR
UVBIAS
S
R
Q
Q
S
R
Q
Q
FLT
SD FLT
SD
1X
NOTE: Pins shown for 14-pin package.
270K
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
VDD –0.3 V to 10 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin voltage (all pins except CAP and GATE) –0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin voltage (CAP and GATE) –0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PL current 0.5 mA to –10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IBIAS current 0 mA to 3 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Junction temperature, TJ–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature (soldering, 10sec.) 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and
considerations of package.
electrical characteristics, VDD = 5 V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the
UCC2919, all voltages are with respect to GND, TA = TJ, (unless otherwise specified)
input supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Supply current
VDD = 3 V 0.5 1 mA
Supply current VDD = 8 V 1 1.5 mA
Shutdown current SD = 0.2 V 1 7 µA
undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Minimum voltage to start 2.35 2.75 3 V
Minimum voltage after start 1.9 2.25 2.5 V
Hysteresis 0.25 0.5 0.75 V
IBIAS
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Output voltage, (0 A < IOUT < 15 A)
25°C, referred to CSP 1.47 1.5 1.53 V
Output voltage, (0 µA < IOUT < 15 µA) Over temperature range, referred to CSP 1.44 1.5 1.56 V
Maximum output current 1 2 mA
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electrical characteristics, VDD = 5 V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the
UCC2919, all voltages are with respect to GND, TA = TJ, (unless otherwise specified)
current sense
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Over current comparator offset Referred to CSP, 3 V ≤ VDD ≤ 8 V –55 –50 –45 mV
Linear current amplifier offset
VIMAX = 100 mV, referred to CSP, 3 V ≤ VDD ≤ 8 V –120 –100 –80 mV
Linear current amplifier offset VIMAX = 400 mV, referred to CSP, 3 V ≤ VDD ≤ 8 V –440 –400 –360 mV
Overload comparator offset VIMAX = 100 mV, referred to CSP, 3 V ≤ VDD ≤ 8 V –360 –300 –240 mV
CSN input common mode voltage
range Referred to VDD, 3 V ≤ VDD ≤ 8 V, See Note 1 –1.5 0.2 V
CSP input common mode voltage
range Referred to VDD, 3 V ≤ VDD ≤ 8 V, See Note 1 0 0.2 V
Input bias current CSN 1 5 µA
Input bias current CSP 100 200 µA
current fault timer
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
CT charge current VCT = 1 V –56 –35 –16 µA
CT discharge current VCT = 1 V 0.5 1.2 1.9 µA
On time duty cycle in fault IPL = 0 1.5 3 6 %
CT fault threshold 1.0 1.5 1.7 V
CT reset threshold 0.25 0.5 0.75 V
IMAX
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input bias current VIMAX = 100 mV, referred to CSP –1 0 1 µA
power limiting
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Voltage on PL
IPL = –250 µA, referred to VDD –1.0 –1.4 –1.9 V
Voltage on PL IPL = –1.5 mA, referred to VDD –0.5 –1.8 –2.2 V
On time duty cycle in fault
IPL = –250 µA 0.25 0.5 1 %
On time duty cycle in fault IPL = –1.5 mA 0.05 0.1 0.2 %
NOTES: 1. Ensured by design. Not 100% production tested.
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electrical characteristics, VDD = 5 V, TA = 0°C to 70°C for the UCC3919, –40°C to 85°C for the
UCC2919, all voltages are with respect to GND, TA = TJ, (unless otherwise specified)
SD and L/R inputs
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Input voltage low 0.8 V
Input voltage high 2 V
L/R input current 1 3 6 µA
SD internal pulldown impedance 100 270 500 kΩ
FLT output
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Output leakage current VDD = 5 V 10 µA
Output low voltage IOUT = 10 mA 1 V
FET gate driver and charge pump
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Peak output current VCAP = 15 V, VGATE = 10 V –3 –1 –0.25 mA
Peak sink current VGATE = 5 V 20 mA
Fault delay 100 300 ns
Maximum output voltage
VDD = 3 V, average IOUT = 1 µA 8 10 12 V
Maximum output voltage VDD = 8 V, average IOUT = 1 µA 12 14 16 V
Charge pump UVLO minimum voltage
VDD = 3 V 6.5 8.8 10.1 V
Charge pump UVLO minimum voltage
to start VDD = 8 V 6.5 9.9 11.5 V
Charge pump source impedance VDD = 5 V, average IOUT = 1 µA 50 100 150 kΩ
pin descriptions
CAP A capacitor is placed from this pin to ground to filter the output of the on board charge pump. A 0.01-µF to 0.1-µF
capacitor will work in most applications. Refer to TI literature number SLUA339 application note, Sizing the
UCC3919 Charge−Pump Capacitor, to determine the exact capacitance.
CSN
The negative current sense input signal.
CSP
The positive current sense input signal. Input to the duty cycle timer.
CT
Input to the duty cycle timer. A capacitor is connected from this pin to ground, setting the off time and maximum
on time of the over-current protection circuit.
FLT
Fault indicator. This open drain output will pull low under any fault condition where the output driver is disabled.
This output is disabled when the IC is in low current standby mode.
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pin descriptions (continued)
GATE
The output of the linear current amplifier. This pin drives the gate of an external N-channel MOSFET pass
transistor. The linear current amplifier control loop is internally compensated, and ensured stable for output load
(gate) capacitance between 100 pF and 0.01 µF. In applications where the GATE voltage (or charge pump
voltage) exceeds the maximum gate-to-source voltage ratings (VGS) for the external N-channel MOSFET, a
Zener clamp may be added to the gate of the MOSFET. No additional series resistance is required since the
internal charge pump has a finite output impedance of 100-kΩ typical.
GND
The ground reference for the device.
IBIAS
Output of the on board bias generator internally regulated to 1.5 V below CSP. A resistor divider between this
pin and CSP can be used to generate the IMAX voltage. The bias circuit is internally compensated, and requires
no bypass capacitance. If an external bypass is required due to a noisy environment, the circuit will be stable
with u p t o 0.001 µF of capacitance. The bypass must be to CSP, since the bias voltage is generated with respect
to CS P. Resistor R2 (Figure 5) should be greater than 50 kΩ to minimize the effect of the finite input impedance
of the IBIAS pin on the IMAX threshold.
IMAX
Used to program the maximum allowable sourcing current. The voltage on this pin is with respect to CSP. If the
voltage across the shunt resistor exceeds this voltage the linear current amplifier lowers the voltage at GATE
to limit the output current to this level. If the voltage across the shunt resistor goes more than 200 mV beyond
this voltage, the gate drive pin GATE is immediately driven low and kept low for one full off time interval.
L/R
Latch/Reset. This pin sets the reset mode. If L/R is low and a fault occurs the device will begin duty ratio current
limiting. If L/R is high and a fault occurs, GATE will go low and stay low until L/R is set low. This pin is internally
pulled low by a 3-µA nominal pulldown.
PL
Power Limit. This pin is used to control average power dissipation in the external MOSFET. If a resistor is
connected from this pin to the source of the external MOSFET, the current in the resistor will be roughly
proportional to the voltage across the FET. As the voltage across the FET increases, this current is added to
the fault timer charge current, reducing the on time duty cycle from its nominal value of 3% and limiting the
average power dissipation in the FET.
SD
Shutdown pin. If this pin is taken low, GATE will go low, and the IC will go into a low current standby mode and
CT will be discharged. This TTL compatible input must be driven high to turn on.
VDD
The power connection for the device.
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APPLICATION INFORMATION
The UCC3919 monitors the voltage drop across a high side sense resistor and compares it against three
different voltage thresholds. These are discussed below. Figure 1 shows the UCC3919 waveforms under fault
conditions.
fault threshold
The first threshold is fixed at 50 mV. If the current is high enough such that the voltage on CSN is 50 mV below
CSP, the timing capacitor CT begins to charge at about 35 µA if the PL pin is open. (Power limiting will be
discussed later). If this threshold is exceeded long enough for CT to charge to 1.5 V, a fault is declared and the
external MOSFET will be turned off. It will either be latched off (until the power to the circuit is cycled, the L/R
pin is taken low, or the SD pin is toggled), or will retry after a fixed off time (when CT has discharged to 0.5 V),
depending on whether the L/R pin is set high or low by the user. The equation for this current threshold is simply:
IFAULT +0.05
RSENSE
The first time a fault occurs, CT is at ground, and must charge to 1.5 V. Therefore:
tFAULT +tON(sec) +Ct(mF) 1.5
35
In the retry mode, the timing capacitor will already be charged to 0.5 V at the end of the off time, so all subsequent
cycles will have a shorter ton time, given by:
tFAULT ^tON(sec) +CT(mF)
35
Note that these equations for tON are without the power limiting feature (RPL pin open). The effects of power
limiting on tON will be discussed later.
The off time in the retry mode is set by CT and an internal 1.2-µA sink current. It is the time it takes CT to discharge
from 1.5 V to 0.5 V. The equation for the off time is therefore:
tOFF(sec) +CTmF
1.2
shutdown characteristics
When the SD pin is set to TTL high (above 2 V) the UCC3919 is ensured to be enabled. When SD is set to a
low TTL (below 0.8 V) the UCC3919 is ensured to be disabled, but may not be in ultra low current sleep mode.
When SD is set to 0.2 V or less, the UCC3919 is ensured to be disabled and in ultra low current sleep mode.
See Figure 1. At cold temperatures, (below 0°C), the UCC2919 shutdown supply current delays gradually over
time and may take >1 minute to drop below the 7-µA shutdown current limit. However, the gate output is driven
low immediately when the SD pin is pulled low and does not exhibit a temperature dependency.
(1)
(2)
(3)
(4)
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APPLICATION INFORMATION
Figure 1
0.0 0.25 0.50
0.01
0.1
1
10
100
1000
10,000
0.75 1.00 1.25 1.50 1.75 2.0
0
SUPPLY CURRENT
vs
SD PIN VOLTAGE
ICC − Supply Current − µA
VSD − SD Pin Voltage − V
IMAX threshold
The second threshold is programmed by the voltage on IMAX (measured with respect to the CSP pin). This
controls the maximum current, IMAX, that the UCC3919 will allow to flow into the load during the MOSFET on
time. A resistive divider connected between IBIAS and CSP generates the programming voltage. When the drop
across the sense resistor reaches this voltage, a linear amplifier reduces the voltage on GATE to control the
external MOSFET in a constant current mode.
During this time CT is charging, as described above. If this condition lasts long enough for CT to charge to 1.5 V,
a fault will be declared and the MOSFET will be turned off. The IMAX current is calculated as follows:
IMAX +VCSP *VIMAX
RSENSE
Note that if the voltage on the IMAX pin is programmed to be less than 50 mV below CSP, then the UC3919 will
control the MOSFET in a constant current mode all the time. No fault will be declared and the MOSFET will
remain on because IMAX is less than IFAULT.
(5)
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APPLICATION INFORMATION
overload threshold
There is a third threshold which, if exceeded, will declare a fault and shutdown the external MOSFET
immediately, without waiting for CT to charge. This overload threshold is 200 mV greater than the IMAX threshold
(again, this is with respect to CSP). This feature protects the circuit in the event that the external MOSFET is
on, with a load current below IMAX, and a short is quickly applied across the output. This allows hot-swapping
in cases where the UCC3919 is already powered up (on the backplane) and capacitors are added across the
output bus. In this case, the load current could rise too quickly for the linear amplifier to reduce the voltage on
GATE and limit the current to IMAX. If the overload threshold is reached, the MOSFET will be turned off quickly
and a fault declared. A latch is set so that CT can be charged, ensuring that the MOSFET will remain off for the
same period as defined above before retrying. The overload current is:
IOVERLOAD +VCSP *VIMAX )0.2
RSENSE +IMAX )0.2
RSENSE
Note that IOVERLOAD may be much greater than IMAX, depending on the value of RSENSE.
power limiting
A power limiting feature is included which allows the power dissipated in the external MOSFET to be held
relatively constant during a short, for different values of input voltage. This is accomplished by connecting a
resistor from the output (source of the external MOSFET) to PL. When the output voltage drops due to a short
or overload, an internal bias current is generated which is equal to:
IPL ^ǒVIN *VOUT *VPLǓ
RPL
This current is used to help charge the timing capacitor in the event that the load current exceeds IFAULT. (A
simplified schematic of the circuit internal to the UCC3919 is shown in Figure 2.) The result is that the on time
of the MOSFET during current limit is reduced as the input voltage is increased. This reduces the effective duty
cycle, holding the average power dissipated constant.
RPL
CT
VDD
UCC3919
POWER LIMIT
1X 1X
TO
GATE
TO
LOAD
VDD
SD
PL
FLT
IPL
UDG−98124
Figure 2. Power Limiting Circuit
(6)
(7)
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APPLICATION INFORMATION
It can be seen that power limiting will only occur when IPL is > 0 (it cannot be negative). For power limiting to
begin to occur, the voltage drop across the MOSFET must be greater than VDD−VPL or 1.4 V(typ).
VIN *VOUT w1.4 V
The on time using RPL is defined as:
tON +CT DV
IPL )35 10−6, where DV+1V
The graph in Figure 4 illustrates the effect of RPL on the average MOSFET power dissipation into a short. The
equation for the average power dissipation during a short is:
PDISS +IMAX VIN 1.2 10−6
IPL )35 10−6 ,or
PDISS +IMAX VIN tON
tON )tOFF
If PL is left unconnected, the power limiting feature will not be exercised. In the retry mode, the duty cycle during
a fault will be nominally 3%, independent of input voltage. The average power dissipation in the external
MOSFET with a shorted output will be proportional to input voltage, as shown by the equation:
PDISS +IMAX VIN 0.033
calculating CT(min) for a given load capacitance without power limiting
To ensure recovery from an overload when operating in the retry mode, there is a maximum total output
capacitance wh i c h c a n b e c h a r g e d f o r a g i v e n t ON (fault time) before causing a fault. For a worst case situation
of a constant current load below the fault threshold, CT(min) for a given output load capacitance (without power
limiting) can be calculated from:
CT(min) +VIN COUT 35 10−6
IMAX *ILOAD
A larger load capacitance or a smaller CT will cause a fault when recovering from an overload, causing the circuit
to get stuck in a continuous hiccup mode. To handle larger capacitive loads, increase the value of CT. The
equation can be easily re-written, if desired, to solve for COUT(max) for a given value of CT.
For a resistive load of value RL and an output cap COUT, CT(min) can be smaller than in the constant current case,
and can be estimated from:
CT(min) +
−COUT RL ȏnǒ1*VIN
IMAX RLǓ
28 103
Note that in the latch mode (or when first turning on in the retry mode), since the timing capacitor is not recovering
from a previous fault, it is charging from 0 V rather than 0.5 V. This allows up to 50% more load capacitance
without causing a fault.
(8)
(9)
(10)
(11)
(12)
(13)
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APPLICATION INFORMATION
estimating CT(min) when using power limiting
If power limiting is used, the calculation of CT(min) for a given COUT becomes considerably more complex,
especially with a resistive load. This is because the CT charge current becomes a function of VOUT, which is
changing with time. The amount of capacitance that can be charged (without causing a fault) when using power
limiting will be significantly reduced for the same value CT, due to the shorter tON time.
The charge current contribution from the power limiting circuit is defined as:
IPL ^ǒVIN *VOUT *VPLǓ
RPL
t0: Normal condition − Output current is nominal, output voltage is at positive rail, VCC.
t1: Fault control reached − Output current rises above the programmed fault value, CT begins to charge with 35 µA + IPL.
t2: Maximum current reached − Output current reaches the programmed maximum level and becomes a constant current with value IMAX.
t3: Fault occurs − CT has charged to 1.5 V, fault output goes low, the FET turns of f allowing no output current to flow, V OUT discharges to GND.
t4: Retry − CT has discharged to 0.5 V, but fault current is still exceeded, CT begins charging again, FET is on, VOUT increases.
t3 to t5: Illustrates < 3% duty cycle depending upon RPL selected.
t6 = t4
t7: Fault released, normal condition − return to normal operation of the circuit breaker
UDG−97073
Figure 3.
(14)
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APPLICATION INFORMATION
constant current load
For a constant current load in parallel with a load capacitor, the load capacitor will charge linearly. During that
time:
IPL(avg) ^ǒVIN *VPLǓ2
2 RPL VIN
Modifying equation (12) yields:
CT(min) ^
VIN COUT ȧ
ȧ
ȱ
Ȳ
ǒVIN*VPLǓ2
2 RPL VIN )35 10−6ȧ
ȧ
ȳ
ȴ
IMAX *ILOAD
Figure 4
12
0
0.05
0.10
0.15
0.20
0.25
0.30
3456
RPL = 24.9 k
RPL = 20.0 k
RPL = 15.0 k
RPL = 10.0 k
For IMAX
= 7 A
MOSFET AVERAGE SHORT CIRCUIT
POWER DISSIPATION
vs
INPUT VOLTAGE
Power Dissipation − W
VIN − Input Voltage − V
(15)
(16)
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APPLICATION INFORMATION
parallel R-C load
Determining CT(min) for a parallel R-C load is more complex. First, the expression for the output voltage as a
function of time is:
VOUT(t) +IMAX RLOAD
ȧ
ȧ
ȡ
Ȣ
1*e−TSTART
RLOAD COUTȧ
ȧ
ȣ
Ȥ
Solving for TSTART when VOUT = VIN yields:
TSTART +*RLOAD COUT ȏnǒ1*ǒVIN
IMAX RLOADǓǓ
Assuming that the device is operating in the retry mode, where CT is charging from 0.5 V to just below 1.5 V
in time (t), CT is defined as:
CT+ICT dt
dV +ICT dt, where
ICT +ǒIPL )35 10−6Ǔ
Substituting equation (15) into (19) yields:
CT(min) +ȧ
ȧ
ȡ
Ȣ
ǒVIN *VPLǓ2
2 RPL VIN )35 10−6ȧ
ȧ
ȣ
Ȥ
dt
This yields the following expression for CT(min) for a resistive load with power limiting. By substituting the value
calculated for TSTART in equation (18) for dt, CT(min) is determined.
CT(min) +ȧ
ȧ
ȱ
Ȳ
ǒVIN *VPLǓ2
2 RPL VIN )35 10−6ȧ
ȧ
ȳ
ȴ
TSTART
(17)
(18)
(19)
(20)
(21)
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APPLICATION INFORMATION
example
The example in Figure 5 shows the UCC3919 in a typical application. A low value sense resistor and N-channel
MOSFET minimize losses. With the values shown for R1, R2, and RS, the overcurrent fault will be 5-A nominal.
Linear current limiting (IMAX) will occur at 7.14 A and the overload comparator will trip at 27 A. The calculations
are shown below.
IFAULT +0.05
RS+0.05
0.01 +5A
IMAX +VCSP *VIMAX
RS+1.5 R1
(R1 )R2) RS+7.14 A
IOVERLOAD +IMAX )0.2
RS+7.14 A )0.2
0.01 +27.14 A
TOFF(sec) +CTmF
1.2 +0.01
1.2 +8.33 ms
With the value shown for RPL:
IPL(typ)(output shorted) +ǒVIN *VPL
RPL Ǔ+ǒ5*1.6
10 k Ǔ+340 mA
tON (shorted)+CT
IPL )35 10−6 +0.01 10−6
375 mA+27 ms
PDISS (shorted) +IMAX VIN tON
tON )tOFF +7.14 5 27 ms
27 ms)8.33 10−3 +0.12 W
For a worst case 1 Ω resistive load: COUT(max) ≅ 47 µF.
For a worst case 5 A constant current load: COUT(max) ≅ 27 µF.
With L/R grounded, the part will operate in the retry or hiccup mode. The values shown for CT and RPL will yield
a nominal duty cycle of 0.32% and an off time of 8.3 ms. With a shorted output, the average steady state power
dissipation in Q1 will be less than 100 mW over the full input voltage range.
If power limiting is disabled by opening RPL, then:
tFAULT +tON(sec) +CTmF 1
35 +287 ms
PDISS (shorted) +IMAX VIN tON
tON )tOFF +7.14 5 287 10−6
287 10−6 )8.33 10−3 +1.2 W (withVIN +5V)
For a worst case 1-Ω resistive load: COUT(max) ≅ 220 µF.
For a worst case 5 A constant current load: COUT(max) ≅ 120 µF.
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
SLUS374C − JULY 1999 − REVISED NOVEMBER 2005
15
www.ti.com
APPLICATION INFORMATION
UDG−98137
14
13
12
11
0.01 Ω
10
9
8
1 CSP
VDD
IMAX
GND
N/C
IBIAS CSN
PL RPL 10k
CT
0.01 µF
COUT RLOAD
VOUT
CIN
2
3
4
5
6
7
0.01 µF
CAP
L/R
SD
FLT
R1
4.99k
R2
100k
GATE
CT
VIN
CSS
10kΩ
BS584
Note 1
NOTES: 1. Optional FET speeds discharge of CSS during fault or shutdown
RS
Figure 5. Application Circuit
THERMAL INFORMATION
steady state conditions
In normal operation, with a steady state load current below IFAULT, the power dissipation in the external MOSFET
will be:
PDISS +RDS(on) ILOAD2
The junction temperature of the MOSFET can be calculated from:
TJ+TA)ǒPDISS qJAǓ
Where TA is the ambient temperature and θJA is the MOSFET’s thermal resistance from junction to ambient.
If the device is on a heatsink, then the following equation applies:
qJA +qJC )qCS )qSA
Where θJC is the MOSFET’s thermal resistance from junction to case, θCS is the thermal resistance from case
to sink, and θSA is the thermal resistance of the heatsink to ambient.
The calculated TJ must be lower than the MOSFET’s maximum junction temperature rating, therefore:
qJA ¦TJ(max) *TA
PDISS
(31)
(32)
(33)
(34)
SLUS374C − JULY 1999 − REVISED NOVEMBER 2005
16 www.ti.com
THERMAL INFORMATION
transient thermal impedance
During a fault condition in the retry mode, the average MOSFET power dissipation will generally be quite low
due to the low duty cycle, as defined by:
PDISS(avg) +IMAX VIN tON
tON )tOFF (with output shorted)
(In the latch mode, tOFF will be the time between a fault and the time the device is reset.)
However, the pulse power in the MOSFET during tON, with the output shorted, is:
PDISS(pulse) +IMAX VIN (with output shorted)
In choosing tON for a given VIN, IMAX, and duty cycle it is important to consult the manufacturer ’s transient
thermal impedance curves for the MOSFET to make sure the device is within its safe operating area. These
curves provide the user with the effective thermal impedance of the device for a given time duration pulse and
duty cycle. Note that some of the impedance curves are normalized to one, in which case the transient
impedance values must be multiplied by the dc (steady state) thermal resistance, θJC.
For duty cycles not shown in the manufacturer’s curves, the transient thermal impedance for any duty cycle and
tON time (given a square pulse) can be estimated from [1]:
qJC(trans) +ǒD qJCǓ)(1 *D) qSP
where D is the duty cycle: tON
tON )tOFF.
and θSP is the single pulse thermal impedance given in the transient thermal impedance curves for the time
duration of interest (tON). Note that these are absolute numbers, not normalized. If the given single pulse
impedance is normalized, it must first be multiplied by θJC before using in the equation above.
This effective transient thermal impedance, when multiplied by the pulse power, will give the transient
temperature ri se o f t h e d i e . To keep the junction temperature below the maximum rating, the following must be
true:
qJC(trans) +TJ(max) *TC
PDISS(pulse)
If necessary, the junction temperature rise can be reduced by reducing ton (using a smaller value for CT), or
by reducing the duty cycle using the power limiting feature already discussed. Note that in either case, the
amount of load capacitance, COUT, that can be charged before causing a fault, will also be reduced.
(35)
(36)
(37)
(38)
SLUS374C − JULY 1999 − REVISED NOVEMBER 2005
17
www.ti.com
THERMAL INFORMATION
safety recommendations
Although the UCC3919 is designed to provide system protection for all fault conditions, all integrated circuits
can ultimately fail short. for this reason, if the UCC3919 is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant safety device such as a fuse should be placed in series
with the device. The UCC3919 will prevent the fuse from blowing for virtually all fault conditions, increasing
system reliability and reducing maintenance cost, in addition to providing the hot swap benefits of the device.
references
1. International Rectifier, HEXFET Power MOSFET Designer’s Manual, Application Note 949B, Current
Ratings, Safe Operating Area, and High Frequency Switching Performance of Power HEXFETs,
pp.1553−1565, September 1993.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
UCC2919D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2919DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2919DTR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2919DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2919N OBSOLETE PDIP N 14 TBD Call TI Call TI
UCC2919PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC2919PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3919D ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3919DG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3919DTR ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3919DTRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3919N OBSOLETE PDIP N 14 TBD Call TI Call TI
UCC3919PW ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
UCC3919PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC2919DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
UCC3919DTR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC2919DTR SOIC D 16 2500 367.0 367.0 38.0
UCC3919DTR SOIC D 16 2500 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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