ADC122S051CIMMX - Texas Instruments High-Performance Analog

GND

CS SCLK

DOUT

DIN

IN1

VAADC122S051

IN2

ADC122S051

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ADC122S051/ADC122S051Q 2 Channel, 200 ksps to 500 ksps 12-Bit A/D Converter

Check for Samples: ADC122S051

1FEATURES DESCRIPTION

The ADC122S051/ADC122S051Q is a low-power,

2• Specified Over a Range of Sample Rates. two-channel CMOS 12-bit analog-to-digital converter

• Two Input Channels with a high-speed serial interface. Unlike the

• Variable Power Management conventional practice of specifying performance at a

single sample rate only, the

• Single Power Supply with 2.7V - 5.25V Range ADC122S051/ADC122S051Q is fully specified over a

• Tested per AEC-Q100 and Qualified for sample rate range of 200 ksps to 500 ksps. The

Automotive Applications converter is based on a successive-approximation

• Meets AEC-Q100-011 C2 CDM Classification register architecture with an internal track-and-hold

circuit. It can be configured to accept one or two input

signals at inputs IN1 and IN2.

APPLICATIONS

• Portable Systems The output serial data is straight binary, and is

compatible with several standards, such as SPI™,

• Remote Data Acquisition QSPI™, MICROWIRE, and many common DSP

• Instrumentation and Control Systems serial interfaces.

The ADC122S051/ADC122S051Q operates with a

KEY SPECIFICATIONS single supply that can range from +2.7V to +5.25V.

• DNL: +0.7 / −0.4 LSB (typ) Normal power consumption using a +3V or +5V

supply is 3.0 mW and 10 mW, respectively. The

• INL: ± 0.50 LSB (typ) power-down feature reduces the power consumption

• SNR: 72.5 dB (typ) to just 0.14 µW using a +3V supply, or 0.32 µW using

• Power Consumption: a +5V supply.

– 3V Supply: 3.0 mW (typ) The ADC122S051/ADC122S051Q is packaged in an

– 5V Supply: 10 mW (typ) 8-lead VSSOP package. Operation over the industrial

temperature range of −40°C to +85°C is specified.

Table 1. Pin-Compatible Alternatives by Resolution and Speed(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC122S021 ADC122S051 ADC122S101

10-bit ADC102S021 ADC102S051 ADC102S101

8-bit ADC082S021 ADC082S051 ADC082S101

(1) All devices are fully pin and function compatible.

Connection Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

IN1

IN2 MUX T/H

SCLK

GND

DIN

DOUT

CONTROL

LOGIC

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

GND

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Block Diagram

PIN DESCRIPTIONS and EQUIVALENT CIRCUITS

Pin No. Symbol Description

ANALOG I/O

5,4 IN1 and IN2 Analog inputs. These signals can range from 0V to VA.

DIGITAL I/O

8 SCLK Digital clock input. This clock directly controls the conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on falling edges of the

7 DOUT SCLK pin.

Digital data input. The ADC122S051/ADC122S051Q's Control Register is loaded through

6 DIN this pin on rising edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins. Conversions continue

1 CS as long as CS is held low.

POWER SUPPLY

Positive supply pin. This pin should be connected to a quiet +2.7V to +5.25V source and

2 VAbypassed to GND with a 1 µF capacitor and a 0.1 µF monolithic capacitor located within 1

cm of the power pin.

3 GND The ground return for the die.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings(1)(2)(3)

Analog Supply Voltage VA−0.3V to 6.5V

Voltage on Any Pin to GND −0.3V to VA+0.3V

Input Current at Any Pin(4) ±10 mA

Package Input Current(4) ±20 mA

Power Consumption at TA= 25°C See (5)

ESD Susceptibility(6) Human Body Model 2500V

Machine Model 250V

Charged Device Model 500V

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) All voltages are measured with respect to GND = 0V, unless otherwise specified.

(4) When the input voltage at any pin exceeds the power supply (that is, VIN < GND or VIN > VA), the current at that pin should be limited to

10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an

input current of 10 mA to two. The Absolute Maximum Rating specification does not apply to the VApin. The current into the VApin is

limited by the Analog Supply Voltage specification.

(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax −TA)/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in

a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is

reversed). Obviously, such conditions should always be avoided.

(6) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through zero ohms

Operating Ratings(1)(2)

Operating Temperature Range −40°C ≤TA≤+85°C

VASupply Voltage +2.7V to +5.25V

Digital Input Pins Voltage Range −0.3V to VA

Clock Frequency 50 kHz to 16 MHz

Analog Input Voltage 0V to VA

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

Package Thermal Resistance(1)

Package θJA

8-lead VSSOP 250°C / W

(1) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging. Reflow temperature

profiles are different for lead-free and non-lead-free packages.

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ADC122S051/ADC122S051Q Converter Electrical Characteristics(1)(2)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500

ksps, CL= 35 pF unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Limits

Symbol Parameter Conditions Typical Units

(3)

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 12 Bits

INL Integral Non-Linearity ±0.5 ±1.1 LSB (max)

+0.7 1.3 LSB (max)

DNL Differential Non-Linearity −0.4 −1.0 LSB (min)

VOFF Offset Error +0.3 ±1.3 LSB (max)

OEM Channel to Channel Offset Error Match ±0.1 ±1.0 LSB (max)

FSE Full Scale Error −0.5 ±1.5 LSB (max)

Channel to Channel Full-Scale Error

FSEM +0.01 ±1.0 LSB (max)

Match

DYNAMIC CONVERTER CHARACTERISTICS

VA= +2.7 to 5.25V

SINAD Signal-to-Noise Plus Distortion Ratio 72 69.2 dB (min)

fIN = 40.2 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

SNR Signal-to-Noise Ratio 72.5 70.6 dB (min)

fIN = 40.2 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

THD Total Harmonic Distortion −84 −75 dB (max)

fIN = 40.2 kHz, −0.02 dBFS

VA= +2.7 to 5.25V

SFDR Spurious-Free Dynamic Range 86 76 dB (min)

fIN = 40.2 kHz, −0.02 dBFS

ENOB Effective Number of Bits VA= +2.7 to 5.25V 11.7 11.2 Bits (min)

VA= +5.25V

Channel-to-Channel Crosstalk −86 dB

fIN = 40.2 kHz

Intermodulation Distortion, Second VA= +5.25V, −87 dB

Order Terms fa= 40.161 kHz, fb= 41.015 kHz

IMD Intermodulation Distortion, Third Order VA= +5.25V −88 dB

Terms fa= 40.161 kHz, fb= 41.015 kHz

VA= +5V 11 MHz

FPBW -3 dB Full Power Bandwidth VA= +3V 8 MHz

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±0.02 ±1 µA (max)

Track Mode 33 pF

CINA Input Capacitance Hold Mode 3 pF

DIGITAL INPUT CHARACTERISTICS

VA= +5.25V 2.4 V (min)

VIH Input High Voltage VA= +3.6V 2.1 V (min)

VIL Input Low Voltage 0.8 V (max)

IIN Input Current VIN = 0V or VIN = VA±0.02 ±10 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

ISOURCE = 200 µA VA−0.03 VA−0.5 V (min)

VOH Output High Voltage ISOURCE = 1 mA VA−0.10 V

ISINK = 200 µA 0.02 0.4 V (max)

VOL Output Low Voltage ISINK = 1 mA 0.1 V

(1) Min/max specification limits are specified by design, test, or statistical analysis.

(2) PPAP (Production Part Approval Process) documentation of the device technology, process and qualification is available from Texas

Instruments upon request.

(3) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

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ADC122S051/ADC122S051Q Converter Electrical Characteristics(1)(2) (continued)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500

ksps, CL= 35 pF unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Limits

Symbol Parameter Conditions Typical Units

(3)

IOZH, IOZL TRI-STATE Leakage Current 0.005 ±1 µA (max)

COUT TRI-STATE Output Capacitance 2 4pF (max)

Output Coding Straight (Natural) Binary

POWER SUPPLY CHARACTERISTICS (CL= 10 pF)

2.7 V (min)

VAAnalog Supply Voltage 5.25 V (max)

VA= +5.25V, 1.9 2.4 mA (max)

fSAMPLE = 500 ksps, fIN = 40 kHz

Supply Current, Normal Mode

(Operational, CS low) VA= +3.6V, 0.84 1.2 mA (max)

fSAMPLE = 500 ksps, fIN = 40 kHz

IAVA= +5.25V, 60 nA

fSAMPLE = 0 ksps

Supply Current, Shutdown (CS high) VA= +3.6V, 38 nA

fSAMPLE = 0 ksps

VA= +5.25V 10 12.6 mW (max)

Power Consumption, Normal Mode

(Operational, CS low) VA= +3.6V 3.0 4.3 mW (max)

PDVA= +5.25V 0.32 µW

Power Consumption, Shutdown (CS

high) VA= +3.6V 0.14 µW

AC ELECTRICAL CHARACTERISTICS

3.2 MHz (min)

fSCLK Maximum Clock Frequency See (4) 8MHz (max)

200 ksps (min)

fSSample Rate See (4) 500 ksps (max)

tCONV Conversion Time 13 SCLK cycles

30 % (min)

DC SCLK Duty Cycle fSCLK = 8 MHz 50 70 % (max)

tACQ Track/Hold Acquisition Time Full-Scale Step Input 3SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

(4) This is the frequency range over which the electrical performance is specified. The device is functional over a wider range which is

specified under Operating Ratings.

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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8

Track Hold

Power Up

Track Hold

b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0

9 10

DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB11 DB10 DB9 DB8 DB7

DIN

DOUT

Power Up

SCLK

Power Down

Control register Control register

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ADC122S051/ADC122S051Q Timing Specifications(1)

The following specifications apply for VA= +2.7V to 5.25V, GND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE = 200 ksps to 500

ksps, CL= 35 pF, Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C. Limits

Symbol Parameter Conditions Typical Units

(2)

VA= +3.0V −3.5

tCSU Setup Time SCLK High to CS Falling Edge See (3) 10 ns (min)

VA= +5.0V −0.5

VA= +3.0V +4.5

tCLH Hold time SCLK Low to CS Falling Edge See (3) 10 ns (min)

VA= +5.0V +1.5

VA= +3.0V +4

tEN Delay from CS Until DOUT active 30 ns (max)

VA= +5.0V +2

VA= +3.0V +14.5

tACC Data Access Time after SCLK Falling Edge 30 ns (max)

VA= +5.0V +13

tSU Data Setup Time Prior to SCLK Rising Edge +3 10 ns (min)

tHData Valid SCLK Hold Time +3 10 ns (min)

0.3 x

tCH SCLK High Pulse Width 0.5 x tSCLK ns (min)

tSCLK

0.3 x

tCL SCLK Low Pulse Width 0.5 x tSCLK ns (min)

tSCLK

VA= +3.0V 1.8

Output Falling VA= +5.0V 1.3

tDIS CS Rising Edge to DOUT High-Impedance 20 ns (max)

VA= +3.0V 1.0

Output Rising VA= +5.0V 1.0

(1) PPAP (Production Part Approval Process) documentation of the device technology, process and qualification is available from Texas

Instruments upon request.

(2) Tested limits are specified to TI's AOQL (Average Outgoing Quality Level).

(3) Clock may be either high or low when CS is asserted as long as setup and hold times tCSU and tCLH are strictly observed.

Timing Diagrams

Figure 1. Operational Timing Diagram

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tCSU

tCLH

SCLK

tCONVERT

tACQ

Z3 Z2 Z1 Z0 DB10

DONT DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

DB11 DB9 DB8 DB1

1687654321

DB0

DIN

DOUT

SCLK

tEN tCL tACC tDIS

tCH

tSU

IOL

200 PA

IOH

200 PA

1.6V

To Output Pin

35 pF

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Figure 2. Timing Test Circuit

Figure 3. Serial Timing Diagram

Figure 4. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold

capacitor to charge up to the input voltage.

APERTURE DELAY is the time between the fourth falling SCLK edge of a conversion and the time when the

input signal is acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

CROSSTALK is the coupling of energy from one channel into the other channel, or the amount of signal energy

from one analog input that appears at the measured analog input.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK.

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EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD −1.76) / 6.02 and says that the converter is equivalent to

a perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below

VREF+and is defined as:

VFSE = Vmax + 1.5 LSB – VREF+(1)

where Vmax is the voltage at which the transition to the maximum code occurs. FSE can be expressed in Volts,

LSB or percent of full scale range.

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF −1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in

the second and third order intermodulation products to the sum of the power in both of the original frequencies.

IMD is usually expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be

reached with any input value. The ADC122S051/ADC122S051Q is ensured not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal at the

converter output to the rms value of the sum of all other spectral components below one-half the sampling

frequency, not including d.c. or harmonics included in the THD specification.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal

amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is

any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.

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log20=THD 

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TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five

harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is

calculated as

(2)

where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the

first 5 harmonic frequencies. Accurate THD measurement requires a spectrally pure sine wave (monotone) at the

ADC input.

THROUGHPUT TIME is the minimum time required between the start of two successive conversion. It is the

acquisition time plus the conversion and read out times. In the case of the ADC122S051/ADC122S051Q, this is

16 SCLK periods.

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Typical Performance Characteristics

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

DNL - VA= 3.0V INL - VA= 3.0V

Figure 5. Figure 6.

DNL - VA= 5.0V INL - VA= 5.0V

Figure 7. Figure 8.

DNL vs. Supply INL vs. Supply

Figure 9. Figure 10.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

DNL vs. Clock Frequency INL vs. Clock Frequency

Figure 11. Figure 12.

DNL vs. Clock Duty Cycle INL vs. Clock Duty Cycle

Figure 13. Figure 14.

DNL vs. Temperature INL vs. Temperature

Figure 15. Figure 16.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

SNR vs. Supply THD vs. Supply

Figure 17. Figure 18.

SNR vs. Clock Frequency THD vs. Clock Frequency

Figure 19. Figure 20.

SNR vs. Clock Duty Cycle THD vs. Clock Duty Cycle

Figure 21. Figure 22.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

SNR vs. Input Frequency THD vs. Input Frequency

Figure 23. Figure 24.

SNR vs. Temperature THD vs. Temperature

Figure 25. Figure 26.

SFDR vs. Supply SINAD vs. Supply

Figure 27. Figure 28.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

SFDR vs. Clock Frequency SINAD vs. Clock Frequency

Figure 29. Figure 30.

SFDR vs. Clock Duty Cycle SINAD vs. Clock Duty Cycle

Figure 31. Figure 32.

SFDR vs. Input Frequency SINAD vs. Input Frequency

Figure 33. Figure 34.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

SFDR vs. Temperature SINAD vs. Temperature

Figure 35. Figure 36.

ENOB vs. Supply ENOB vs. Clock Frequency

Figure 37. Figure 38.

ENOB vs. Clock Duty Cycle ENOB vs. Input Frequency

Figure 39. Figure 40.

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Typical Performance Characteristics (continued)

TA= +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 3.2 MHz to 8 MHz, fIN = 40.2 kHz unless otherwise stated.

ENOB vs. Temperature Spectral Response - 3V, 200 ksps

Figure 41. Figure 42.

Spectral Response - 5V, 200 ksps Spectral Response - 3V, 500 ksps

Figure 43. Figure 44.

Spectral Response - 5V, 500 ksps Power Consumption vs. Throughput

Figure 45. Figure 46.

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IN1 MUX

GND

SAMPLING

CAPACITOR

SW1 -

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN2

IN1 MUX

GND

SAMPLING

CAPACITOR

SW1

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN2

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APPLICATIONS INFORMATION

ADC122S051/ADC122S051Q OPERATION

For the rest of this document, the ADC122S051/ADC122S051Q will be referred to as the ADC122S051.

The ADC122S051 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter. Simplified schematics of the ADC122S051 in both track and hold modes

are shown in Figure 47 and Figure 48, respectively. In Figure 47, the ADC122S051 is in track mode: switch SW1

connects the sampling capacitor to one of two analog input channels through the multiplexer, and SW2 balances

the comparator inputs. The ADC122S051 is in this state for the first three SCLK cycles after CS is brought low.

Figure 48 shows the ADC122S051 in hold mode: switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add fixed amounts of charge to the sampling capacitor until the comparator is

balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of

the analog input voltage. The ADC122S051 is in this state for the fourth through sixteenth SCLK cycles after CS

is brought low.

The time when CS is low is considered a serial frame. Each of these frames should contain an integer multiple of

16 SCLK cycles, during which time a conversion is performed and clocked out at the DOUT pin and data is

clocked into the DIN pin to indicate the multiplexer address for the next conversion.

Figure 47. ADC122S051 in Track Mode

Figure 48. ADC122S051 in Hold Mode

USING THE ADC122S051

An ADC122S051 timing diagram and a serial interface timing diagram for the ADC122S051 are shown in the

Timing Diagrams section. CS is chip select, which initiates conversions and frames the serial data transfers.

SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data

output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the

ADC122S051's Control Register is placed at DIN, the serial data input pin. New data is written to DIN with each

conversion.

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain

an integer multiple of 16 rising SCLK edges. The ADC output data (DOUT) is in a high impedance state when

CS is high and is active when CS is low. Thus, CS acts as an output enable. Additionally, the device goes into a

power down state when CS is high and also between continuous conversion cycles.

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During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13

SCLK cycles the conversion is accomplished and the data is clocked out, MSB first, starting on the 5th clock. If

there are more than one conversion in a frame, the ADC will re-enter the track mode on the falling edge of SCLK

after the N*16th rising edge of SCLK, and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK,

where "N" is an integer.

When CS is brought high, SCLK is internally gated off. If SCLK is stopped in the low state while CS is high, the

subsequent fall of CS will generate a falling edge of the internal version of SCLK, putting the ADC into the track

mode. This is seen by the ADC as the first falling edge of SCLK. If SCLK is stopped with SCLK high, the ADC

enters the track mode on the first falling edge of SCLK after the falling edge of CS.

During each conversion, data is clocked into the ADC at DIN on the first 8 rising edges of SCLK after the fall of

CS. For each conversion, it is necessary to clock in the data indicating the input that is selected for the

conversion after the current one. See Table 2,Table 3, and Table 4.

If CS and SCLK go low within the times defined by tCSU and tCLH, the rising edge of SCLK that begins clocking

data in at DIN may be one clock cycle later than expected. It is, therefore, best to strictly observe the minimum

tCSU and tCLH times given in the Timing Specifications.

There are no power-up delays or dummy conversions required with the ADC122S051. The ADC is able to

sample and convert an input to full conversion immediately following power up. The first conversion result after

power-up will be that of IN1.

Table 2. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

Table 3. Control Register Bit Descriptions

Bit #: Symbol: Description

7 - 6, 2 - 0 DONTC Don't care. The value of these bits do not affect the device.

3 ADD0 These three bits determine which input channel will be sampled and converted in the next

track/hold cycle. The mapping between codes and channels is shown in Table 4.

4 ADD1

5 ADD2

Table 4. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

x 0 0 IN1 (Default)

x 0 1 IN2

x 1 x Not allowed. The output signal at the DOUT pin is indeterminate if ADD1 is high.

ADC122S051 TRANSFER FUNCTION

The output format of the ADC122S051 is straight binary. Code transitions occur midway between successive

integer LSB values. The LSB width for the ADC122S051 is VA/4096. The ideal transfer characteristic is shown in

Figure 49. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a

voltage of VA/8192. Other code transitions occur at steps of one LSB.

Product Folder Links: ADC122S051

IN1

IN2

MICROPROCESSOR

DSP

SCLK

DIN

DOUT

GND

ADC122S051

LP2950 5V

1 PF

TANT 0.1 PF 0.1 PF1 PF

0V +VA - 1.5LSB

0.5LSB ANALOG INPUT

1LSB = VA/4096

ADC CODE

111...111

111...110

111...000

011...111

000...010

000...001

000...000

ADC122S051

www.ti.com

SNAS257E –NOVEMBER 2004–REVISED MARCH 2013

Figure 49. Ideal Transfer Characteristic

TYPICAL APPLICATION CIRCUIT

A typical application of the ADC122S051 is shown in Figure 50. Power is provided, in this example, by the TI

LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power

supply pin is bypassed with a capacitor network located close to the ADC122S051. Because the reference for

the ADC122S051 is the supply voltage, any noise on the supply will degrade device noise performance. To keep

noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other

circuitry to keep noise off the ADC122S051 supply pin. Because of the ADC122S051's low power requirements,

it is also possible to use a precision reference as a power supply to maximize performance. The four-wire

interface is shown connected to a microprocessor or DSP.

Figure 50. Typical Application Circuit

ANALOG INPUTS

An equivalent circuit for one of the ADC122S051's input channels is shown in Figure 51. Diodes D1 and D2

provide ESD protection for the analog inputs. At no time should any input go beyond (VA+ 300 mV) or (GND −

300 mV), as these ESD diodes will begin conducting, which could result in erratic operation. For this reason,

these ESD diodes should NOT be used to clamp the input signal.

The capacitor C1 in Figure 51 has a typical value of 3 pF, and is mainly the package pin capacitance. Resistor

R1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. Capacitor C2 is the

ADC122S051 sampling capacitor and is typically 30 pF. The ADC122S051 will deliver best performance when

driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance.

This is especially important when using the ADC122S051 to sample AC signals. Also important when sampling

dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic

performance.

Product Folder Links: ADC122S051

VIN

30 pF

3 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

ADC122S051

SNAS257E –NOVEMBER 2004–REVISED MARCH 2013

www.ti.com

Figure 51. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC122S051's digital output DOUT is limited by, and cannot exceed, the supply voltage, VA. The digital

input pins are not prone to latch-up and, and although not recommended, SCLK, CS and DIN may be asserted

before VAwithout any latch-up risk.

POWER SUPPLY CONSIDERATIONS

The ADC122S051 is fully powered-up whenever CS is low, and fully powered-down whenever CS is high, with

one exception: the ADC122S051 automatically enters power-down mode between the 16th falling edge of a

conversion and the 1st falling edge of the subsequent conversion (see Timing Diagrams).

The ADC122S051 can perform multiple conversions back to back; each conversion requires 16 SCLK cycles.

The ADC122S051 will perform conversions continuously as long as CS is held low.

The user may trade off throughput for power consumption by simply performing fewer conversions per unit time.

The Power Consumption vs. Sample Rate curve in the Typical Performance Characteristics section shows the

typical power consumption of the ADC122S051 versus throughput. To calculate the power consumption, simply

multiply the fraction of time spent in the normal mode by the normal mode power consumption , and add the

fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation.

Power Management

When the ADC122S051 is operated continuously in normal mode, the maximum throughput is fSCLK/16.

Throughput may be traded for power consumption by running fSCLK at its maximum 8 MHz and performing fewer

conversions per unit time, putting the ADC122S051 into shutdown mode between conversions. A plot of typical

power consumption versus throughput is shown in the Typical Performance Characteristics section. To calculate

the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the

normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the

shutdown mode power consumption. Generally, the user will put the part into normal mode and then put the part

back into shutdown mode. Note that the curve of power consumption vs. throughput is nearly linear. This is

because the power consumption in the shutdown mode is so small that it can be ignored for all practical

purposes.

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the power supply, VA. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the supply. If these

variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore,

discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current

into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the

substrate that will degrade noise performance if that current is large enough. The larger is the output

capacitance, the more current flows through the die substrate and the greater is the noise coupled into the

analog channel, degrading noise performance.

To keep noise out of the power supply, keep the output load capacitance as small as practical. If the load

capacitance is greater than 35 pF, use a 100 Ωseries resistor at the ADC output, located as close to the ADC

output pin as practical. This will limit the charge and discharge current of the output capacitance and improve

noise performance.

Product Folder Links: ADC122S051

ADC122S051

www.ti.com

SNAS257E –NOVEMBER 2004–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision D (March 2013) to Revision E Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 20

Product Folder Links: ADC122S051

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC122S051CIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X06C

ADC122S051CIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X06C

ADC122S051QIMM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X06Q

ADC122S051QIMMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 X06Q

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

PACKAGE OPTION ADDENDUM

www.ti.com 7-Oct-2013

Addendum-Page 2

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC122S051CIMM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

ADC122S051CIMMX/NOP

BVSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

ADC122S051QIMM/NOP

BVSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

ADC122S051QIMMX/NO

PB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC122S051CIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

ADC122S051CIMMX/NOP

BVSSOP DGK 8 3500 367.0 367.0 35.0

ADC122S051QIMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

ADC122S051QIMMX/NOP

BVSSOP DGK 8 3500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 23-Sep-2013

Pack Materials-Page 2

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