SST28SF040A-90-4C-EHE - Microchip Technology, Inc.

S71077-05-000 3/03 310

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

SSF is a trademark of Silicon Storage Technology, Inc.

These specifications are subject to change without notice.

Data Sheet

4 Mbit (512K x8) SuperFlash EEPROM

SST28SF040A / SST28VF040A

FEATURES:

• Single Voltage Read and Write Operations

– 4.5-5.5V-only for SST28SF 040A

– 2.7-3.6V for SST28VF040A

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Memory Organization: 512K x8

• Sector-Erase Capability: 256 Bytes per Sector

• Low Power Consumption

– Active Current: 15 mA (typical) for 5.0V and

10 mA (typic al) for 2.7-3.6V

– Standby Current: 5 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Byte-Program Time: 35 µs (typical)

– Sector-Erase Time: 2 ms (typical)

– Complete Memory Rewrite: 20 sec (typical)

• Fast Read Access Time

– 4.5-5.5V-only operation: 90 and 120 ns

– 2.7-3.6V operation: 150 and 200 ns

• Latched Address and Data

• Hardware and Software Data Pr otection

– 7-Read-Cycle-Sequence Software Data

Protection

• End-of-Write Detection

– Toggle Bit

– Data# Polling

• TTL I/O Compatibility

• JEDEC Standard

– Flash EE PROM Pino uts

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 20mm )

– 32-pin PDIP

PRODUCT DESCRIPTION

The SST28SF/VF040A are 512K x8 bit CMOS Sector-

Erase, Byte-Program EEPROMs. The SST28SF/VF040A

are manufactured using SST’s proprietary, high perfor-

mance CMOS SuperFlash EEPROM Technology. The

split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with

alternative approac hes. T h e SST 2 8S F/V F040A erase and

program with a single power supply. The SST28SF/

VF04 0A co nform to JEDE C st an da rd pi no u ts for b yt e wi de

memories and are compatible with existing industry stan-

dard flash EEPROM pinouts.

Featuring high performance programming, the SST28SF/

VF040A typically Byte-Program in 35 µs. The SST28SF/

VF040A typically Sector-Erase in 2 ms. Both Program and

Erase times can be optimized using interf ace features such

as Toggle bi t or Da ta# Pollin g to ind ic at e th e c omp le tion of

the W rit e c ycle. To protect ag ai ns t an in ad verten t wri te , t he

SST28SF/VF040A have on chip hardware and Software

Data Protection schemes. Designed, manufactured, and

tested for a wide spectrum of applications, the SST28SF/

VF040A are off ered with a guaranteed sector endurance of

10,000 cycles. Data retention is rated greater than 100

years.

The SST28SF/VF040A are best suited f or applications that

require re-programma bl e nonvolatile m ass storage of pro-

gram, configuration, or data memory. For all system appli-

cations, the SST28SF/VF040A significantly improve

per formanc e and reliab ility, whil e low ering pow er consu mp-

tion when compared with floppy diskettes or EPROM

approaches. Flash EEPROM technology makes possible

convenient and economical updating of codes and control

programs on-line. The SST28SF/VF040A improve flexibil-

ity, while lowering the cost of program and configuration

storage application.

The functional block diagram shows the functional blocks of

the SST28SF/VF040A. Figures 1, 2, and 3 show the pin

assignments f or the 32-lead PLCC , 32-lead TSOP, and 32-

pin PDIP packages. Pin descriptions and operation modes

are described in Tab les 2 through 5.

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. Commands are written to the device

using standard microprocessor write sequences. A com-

mand is written by asse rtin g WE# low while keepi ng CE#

low. The address bus is latched on the falling edge of WE#

or CE#, whichever oc curs l ast. The data bus is latc hed o n

the rising edge of WE# or CE#, whichever occurs first.

Note, during the Software Data Protection sequence the

addres ses are latche d on the ris ing edge of OE # or CE#,

whiche v er occurs first.

SST28SF / VF040A4Mb (x8)

Byte-Program, Small Erase Sector flash memories

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

Command Definitions

Table 4 contains a command list and a brief summary of

the commands. The following is a detailed description of

the operations initiated by each command.

Sector-Erase

The Sector-Erase operation erases all bytes within a sector

and is i niti ate d by a s etu p command and an execute co m-

mand. A sec tor co nta in s 25 6 B y tes. Th is s ec to r erasa bi li ty

enhances the flexibility and usefulness of the SST28SF/

VF040A, since most applications only need to change a

small n umber of bytes or sectors, not the entire chip.

The setup command is perfor med by writing 20H to the

device. The execute command is performed by writing

D0H to th e device. The Erase operation begins with the

rising edge of the WE# or CE#, whichever occurs first

and terminates automatically by using an internal timer.

The E n d- of-Erase c a n be de t ermin ed using ei t he r D at a#

Polling, Toggle Bit, or Successive Reads detection meth-

ods . See Figur e 9 f or tim ing w a v ef orms.

The two-step sequence of a setup command followed by

an execute command ensures that only memory contents

within the addressed sector are erased a nd other sectors

are not inadv ertently erased.

Sector-Erase Flowchart Description

Fas t and reliable eras ing of the mem ory contents w ithin a

sector is accomplished by following the Sector-Erase flow-

chart as shown in Figure 18. The entire procedure consists

of the ex ecution of two commands. The Sector-Erase oper-

atio n will terminat e after a maximum of 4 ms. A Re set com-

mand can be executed to terminate the Sector-Erase

operation; however, if the Erase operation is terminated

prior to the 4 ms time-out, the sector may not be fully

erased. A Sector-Erase command can be reissued as

many times as necessary to complete the Erase operation.

The S ST28S F/VF04 0A cann ot be o v er-er ased .

Chip-Erase

The Chip-Erase operation is initiated by a setup command

(30H) and an execute command (30H). The Chip-Erase

operatio n allows the en tire array of the SST28SF/ VF040A

to be e r a sed i n on e op er a t io n, as op pose d t o 2 0 48 Se ct o r-

Erase operations. Using the Chip-Erase operation will mini-

mize the time to rewrite the entire memory array. The Chip-

Erase oper ation will terminate after a maximum of 20 ms. A

Reset command can be executed to terminate the Erase

operation; however, if the Chip-Erase operation is termi-

nated prior to the 20 ms time-out, the chip may not be com-

pletely erased. If an erase error occurs a Chip-Erase

comma nd can be reissu ed as many times as necess ary to

complete the Chip-Erase operation. The SST28SF/

VF04 0A cann ot be o v er-e rased . (See F igure 8)

Byte-Program

The Byte-Program operation is initiated by writing the

setup command (10H). Once the program setup is per-

formed, programming is executed by the next WE#

pulse. See Figures 5 and 6 for timing waveforms. The

address bus is latched on the falling edge of WE# or

CE#, whichever occurs last. The data bus is latched on

the rising edge of WE# or CE#, whichever occurs first,

and begins the Program operation. The Program opera-

tion is terminated automatically by an internal timer. See

Figur e 16 f or th e progr ammin g flo wchart.

The two-step sequence of a setup command followed by

an execute command ensures that only the addressed

byte is programme d and oth er bytes a re not inadver tent ly

programmed.

The Byte-Program Flowchart Description

Programming data into the SST28SF/VF040A is accom-

plished by following the Byte-Program flowchart shown in

Figure 16. The Byte-Program command sets up the byte

for programming. The address bus is latched on the falling

edge of WE# or CE#, whichever occurs last. The data bus

is latched on the rising edge of WE# or CE#, whichever

occurs fi rs t a nd b egi ns the P r ogram o pera ti on. Th e end of

program can be detected using either the Data# Polling,

Toggle bi t, or Succe ssiv e reads .

Reset

The Reset command is provided as a means to safely

abort the Erase or Program command sequences. Follow-

ing eithe r set up co m ma nd (Era s e or Pr ogram) with a write

of FFH will saf ely abort the operation. Memory contents will

not be altered. After the Reset command, the device

retur ns to the Read m ode. The Res et comma nd do es no t

enable Software Data Protection. See Figure 7 for timing

waveforms.

Read

The Read operation is initiated by setting CE#, and OE# to

logic l ow and s etti ng WE # to log ic hi gh (See Table 3). Se e

Figure 4 f or Read cycle timing wavef orm. The Read opera-

tion from the host retrieves data from the array. The device

remain s enabled for Read until an other ope ration mod e is

access ed. Du ring init ial po wer- up , th e de vic e is in t he Read

mode and is Software Data protected. The device must be

unprotected to ex ecute a Write command.

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

The Read operation of the SST28SF/VF040A are con-

trolled by OE# and CE# at logic low. When CE # is high,

the chip is deselected and only standby power will be con-

sumed. O E # i s the out put co ntr o l a nd i s used to gate data

from the output pins. The data bus is in high impedance

state when CE# or O E# are high.

Read-ID

The Read-ID operation is initiated by writing a single com-

mand (90H). A read of address 0000H will output the man-

ufacturer’s ID (BFH). A read of address 0001H will outpu t

the device ID (04H). Any other valid command will termi-

nate this operation.

Data Protection

In order t o protec t the integr ity of nonvolatile da ta storage,

the SST28SF/VF040A provide both

hardware and software features to prevent inadvertent

writes to the device, for example, during system power-up

or power-do wn. Such provisions are described below.

Hardware Data Protection

The SST28SF/VF040A are designed with hardware fea-

tures t o prevent inadver tent wr ites. This i s done in the fol-

lo wing w a ys:

1. Write Cycle Inhibit Mode: OE# low, CE#, or WE#

high will inhibit the Write operation.

2. Noise/Glitch Protection: A WE# pulse width of less

than 5 ns will not initiate a Write cycle.

3. VDD Power Up/Down Detection: The Write opera-

tion is inhibited when VDD is less than 2.0V.

4. After power-up, the device is in the Read mode

and the device is in the Software Data Protect

state.

Software Data Protection (SDP)

The SST28SF/VF040A have software methods to fur ther

prevent inadvertent writes. In order to pe rform an Era se or

Program operation, a two-step command sequence con-

sisti ng of a set -up com mand followed by an exe cute co m-

mand avoids inadvertent erasing and programming of the

device.

The SST28SF/VF040A will default to Software Data Pro-

tection after power up. A sequence of seven consecutive

reads at specific addresses will unprotect the device The

address sequence is 1823H, 1820H, 1822H, 0418H,

041BH, 0419H, 041AH. The address bus is latched on the

rising edge of OE# or CE#, whiche ver occurs firs t. A similar

seven read sequence of 1823H, 1820H, 1822H, 0418H,

041BH, 0419H, 040AH will protect the device . Also refer to

Figu res 10 and 11 f o r the 7 R ead cyc le sequen ce Soft ware

Data Protec tion . The I /O pins c an be in any stat e (i.e ., h igh,

lo w , or tri-stat e).

Write Opera ti on Status De te ct ion

The SST2 8SF/VF040 A provide thre e means to de tect the

completion of a Write operation, in order to optimize the

system Write operation. The end of a Write operation

(Erase or Program) can be detected by three means: 1)

monitoring the Data# Polling bit, 2) monitoring the Toggle

bit, or 3) by two succe ss ive reads of the sa me da ta. These

three detection mechanisms are described belo w .

The actual completion of the non v olatile Write is asynchro-

nous with the system; therefore, either a Data# Polling or

Toggle Bit read may be simultaneou s with the completion

of the Write cycle. If this occurs, the system may possibly

get an erroneous result, i.e., valid data ma y appear to con-

flict with the DQ used. In order to prevent spurious rejec-

tion, if an erroneous result occurs, the software routine

should include a loop to read the accessed location an

additional two (2) times. If both Reads are valid, then the

device has completed the Write cycle, otherwise the rejec-

tion is valid.

Data# Polling (DQ7)

The SST28SF/VF040A feature Data# Polling to indi-

cate the Wr ite operation status. Duri ng a Write op era-

tion, any attempt to read the last byte loaded during

the byte-load cy cle will recei ve the complem ent of the

true data on DQ7. Once the Write cycle is completed,

DQ7 will show true data. Note that even though DQ7

may have valid data immediately following the comple-

tion of an inter nal Wr ite operat ion, the re maining data

outputs may still be invalid: valid data on the entire

data bus will appear in subsequent successive Read

cycles after an interval of 1 µs. See Figure 12 for

Data# Polling timing waveforms. In order for Data#

Polli ng to function co rrec tl y, the byte being polle d must

be erased prior to programming.

Toggle Bit (DQ6)

An alternative means for determining the Write operation

status is by monitoring the Toggle Bit, DQ6. During a Write

operation, consecutive attempts to read data from the

device will result in DQ6 toggling betw een logic 0 (low) and

logic 1 (h igh). Wh en the Wri te cycl e is compl eted, the tog-

gling will stop. The device is then ready for the next opera-

tion. See Figure 13 f or Toggle Bit timing wavef orms .

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

Successive Reads

An Alternative means for determining an end of a Write

operation is by reading the same address for two consecu-

tive data matc hes.

Product Identifica tion

The Product Identification mode identifies the device

as SST28SF/VF040A and the manufacturer as SST.

This mode may be accessed by hardware and soft-

ware operations. The hardware operation is typically

used by an exter nal programmer to identify the corr ect

algorithm for the SST28SF/VF040A. Users may wish

to use the software operation to identify the device

(i.e., using the device ID). For details see Table 3 for

the hardware operation an d Fig ure 19 for the sof tware

operation. The manufacturer’s and device IDs are the

same for both operatio ns.

FIGURE 1: PIN ASSIGNMENTS FOR 32- LEAD PLCC

TABLE 1: PRODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST28SF/VF040A 0001H 04H

T1.1 310

Y-Decoder

I/O Buffers and Data Latches

310 ILL B1.1

Address Buffer & Latches

X-Decoder

DQ7 - DQ0

A18 - A0

WE#

OE#

CE#

SuperFlash

Memory

Control Logic

FUNCTIONAL BLOCK DIAGRAM

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

4 3 2 1 32 31 30

A12

A15

A16

A18

VDD

WE#

A17

32-lead PLCC

Top View

310 ILL F02.3

14 15 16 17 18 19 20

DQ1

DQ2

VSS

DQ3

DQ4

DQ5

DQ6

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 2: PIN ASSIGNMENTS FOR 32- LEAD TSOP

FIGURE 3: PIN ASSIGNMENTS FOR 32- PIN P DIP

A11

A13

A14

A17

WE#

VDD

A18

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

310 ILL F01.2

Standard Pinout

Top View

Die Up

32-pin

PDIP

Top View

310 ILL F19.0

A18

A16

A15

A12

DQ0

DQ1

DQ2

VSS

VDD

WE#

A17

A14

A13

A11

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

TABLE 2: PIN DESCRIPTION

Symbol Pin Name Functions

A18-A8Row Address Inputs To provide memory addresses. Row addresses define a sector.

A7-A0Column Address Inputs Selects the byte within the sector

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

CE# Chip Enable To activate the device when CE# is low.1

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.1

VDD Power Supply To provide: 5.0V supply (4.5-5.5V) for SST28SF040A

2.7V supply (2.7-3.6V) for SST28VF040A

VSS Ground

T2.2 310

1. This pin has an internal pull-up resistor.

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

TABLE 3: OPERATION MODES SELECTION

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Byte-Program VIL VIH VIL DIN AIN, See Table 4

Sector-Erase VIL VIH VIL DIN AIN, See Table 4

Standby VIH X1X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Softw are Chip -Er ase VIL VIH VIL DIN See Table 4

Product Identification

Hardw are Mode VIL VIL VIH Manufacturer’s ID (BFH)

Device ID (04H) A18-A1=VIL, A9=VH, A0=VIL

A18-A1=VIL, A9=VH, A0=VIH

Softw are Mode VIL VIL VIH See Table 4

SDP Enable & Disable Mode VIL VIL VIH See Table 4

Reset VIL VIH VIL See Table 4

T3.4 310

1. X can be VIL or VIH, but no other value.

TABLE 4: SOFTWARE COMMAND SUMMARY

Command Summary

Required Setup Command Cycle Execute Command Cycle

Cycle(s) Type1

1. Type definition: W = Write, R = Read, X can be VIL or VIH, but no other value.

Addr2,3

2. Addr (Address) definition: SA = Sector Address = A18-A8, sector size = 256 Bytes; A7-A0 = X for this command.

3. Addr (Address) definition: PA = Program Address = A18-A0.

Data4

4. Data definition: PD = Program Data, H = number in hex.

Type1Addr2,3 Data4SDP5

5. SDP = Soft ware Data Protect mode using 7 Read Cycle Sequence.

a) Y = the operation can be ex ecuted with protection enabled

b) N = the operation cannot be ex ecuted with protection enabled

Sector-Erase 2 W X 20H W SA D0H N

Byte-Program 2 W X 10H W PA PD N

Chip-Erase6

6. The Chip-Erase function is not supported on industrial temperature parts.

2 W X 30H W X 30H N

Reset 1 W X FFH Y

Read-ID 2 W X 90H R 7

7. Address 0000H retrieves the Manufacturer’s ID of BFH and address 0001H retrieve s the Device ID of 04H.

Softw are Data Prote ct 7 R 8

8. Ref er to Figure 11 for the 7 Read Cycl e sequence for Software-Data-Protect.

Softw are Data Unpro t ect 7 R 9

9. Ref er to Figure 10 for the 7 Read Cycle sequence for Software-Data-Unprot ect.

T4.4 310

TABLE 5: MEMORY ARRAY DETAIL

Sector Select B yt e Select

A18 - A8A7 - A0

T5.0 310

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum

Stress Ratings” may caus e per manent d amage to the device. This is a stres s rating only and funct ional operat ion

of the device at these conditions or conditions greater than those defined in the operational sections of this data

sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)

Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V

Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14.0V

Package Po wer Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W

Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C

Output Short Circuit Cur rent1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

OPERATING RANGE FOR SST28S F040A

Range Ambient Temp VDD

Commercial 0°C to +70°C 4.5-5.5V

Industrial -40°C to +85°C 4.5-5.5V

OPERATING RANGE FOR SST28V F040A

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

AC CONDITIONS OF TEST

Input Rise/Fall Time . . . . . . . . . . . . . . 10 ns

Output Load . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate andCL = 100 pF for SST28SF040A

CL = 100 pF for SST28VF040A

See Figures 14 and 15

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

TABLE 6: DC OPERATING CHARACTERISTICS FOR SST2 8SF040A

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max

Read 32 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Program and Erase 40 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB1 Standby VDD Current

(TTL input) 3mACE#=V

IH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input) 20 µA CE#=VDD-0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=2.1 mA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-400 µA, VDD=VDD Min

VHSupervoltage for A911.6 12.4 V CE#=OE#=VIL, WE#=VIH

IHSupervoltag e Current for A9200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max

T6.5 310

TABLE 7: DC OPERATING CHARACTERISTICS FOR SST2 8VF040A

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT, at f=1/TRC Min,

VDD=VDD Max

Read 10 mA CE#=OE#=VIL, WE#=VIH, all I/Os open

Program and Erase 25 mA CE#=WE#=VIL, OE#=VIH, VDD=VDD Max

ISB2 Standby VDD Current

(CMOS input) 20 µA CE#=OE#=WE#=VDD-0.3V, VDD=VDD Max

ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max

ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VIH Input High Voltage 2.0 V VDD=VDD Max

VOL Output Low Voltage 0.4 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage 2.4 V IOH=-100 µA, VDD=VDD Min

VHSupervoltage for A911.6 12.4 V CE#=OE#=VIL, WE#=VIH

IHSupervoltag e Current for A9200 µA CE#=OE#=VIL, WE#=VIH, A9=VH Max

T7.5 310

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

TABLE 8: RECOMMENDED SYSTEM POWER-UP TIMINGS

Symbol Parameter Minimum Units

TPU-READ1Power-up to Read Operation 10 ms

TPU-WRITE1Power-up to Write Operation 10 ms

T8.4 310

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

TABLE 9: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

I/O Pin Capacitance VI/O = 0V 12 pF

CIN1Input Capacitance VIN = 0V 6 pF

T9.0 310

TABLE 10: RELIABILITY CHARACTERISTICS

Symbol Parameter Minimum Specification Units Test Method

NEND1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T10.7 310

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

AC CHARACTERISTICS

TABLE 11: READ CYCLE TIMING PARAMETERS FOR SST28SF040A

IEEE

Symbol Industry

Symbol Parameter

SST28SF040A-90 SST28SF040A-120

UnitsMin Max Min Max

tAVAV TRC Read Cyc le Tim e 90 120 ns

tAVQV TAA A ddress Access Time 90 120 ns

tELQV TCE Chip Enable Access Time 90 120 ns

tGLQV TOE Output Enable Access Time 45 50 ns

tEHQZ TCLZ1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

CE# Low to Active Output 0 0 ns

tGHQZ TOLZ1OE# Low to Active Output 0 0 ns

tELQX TCHZ1CE# High to High-Z Output 20 30 ns

tGLQX TOHZ1OE# High to High-Z Output 20 30 ns

tAXQX TOH1Output Hold from Address Change 0 0 ns

T11.6 310

TABLE 12: READ CYCLE TIMING PARAMETERS FOR SST28VF040A

IEEE

Symbol Industry

Symbol Parameter

SST28VF040A-150 SST28VF040A-200

UnitsMin Max Min Max

tAVAV TRC Read Cycle Time 150 200 ns

tAVQV TAA Address Access Tim e 150 200 ns

tELQV TCE Chip Enable Access Time 150 200 ns

tGLQV TOE Output Enable Access Time 75 100 ns

tEHQZ TCLZ1

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

CE# Low to Active Output 0 0 ns

tGHQZ TOLZ1OE# Low to Active Output 0 0 ns

tELQX TCHZ1CE# High to High-Z Output 40 60 ns

tGLQX TOHZ1OE# High to High-Z Output 40 60 ns

tAXQX TOH1Output Hold from Address Change 0 0 ns

T12.5 310

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

TABLE 13: ERASE/PROGRAM CYCLE TIMING PARAMETERS

IEEE

Symbol Industry

Symbol Parameter

SST28SF040A SST28VF040A

UnitsMin Max Min Max

tAVA TBP Byte-Program Cycle Time 40 40 µs

tWLWH TWP Write Pulse Width (WE#) 90 100 ns

tAVWL TAS Address Setup Time 10 10 ns

tWLAX TAH Address Hold T ime 50 100 ns

tELWL TCS CE# Setup Time 0 0 ns

tWHEX TCH CE# Hold Time 0 0 ns

tGHWL TOES OE# High Setup Time 10 20 ns

tWGL TOEH OE# High Hold Time 10 20 ns

tWLEH TCP Write Pulse Width (CE#) 90 100 ns

tDVWH TDS Data Setup Time 50 100 ns

tWHDX TDH Data Hold Time 10 20 ns

tWHWL2 TSE Sector-Erase Cycle Time 4 4 ms

TRST1Reset Command Recovery Time 4 4 µs

tWHWL3 TSCE Software Chip-Erase Cycle Time 20 20 ms

tEHEL TCPH CE# High Pulse Width 50 50 ns

tWHWL1 TWPH WE# High Pulse Width 50 50 ns

TPCP1Protect CE# or OE# Pulse Width 50 50 ns

TPCH1Protect CE# or OE# High Time 50 50 ns

TPAS1Protect Address Setup Time 40 40 ns

TPAH1Protect Address Hold Time 0 0 ns

T13.6 310

1. This parameter is measured only for initial qualification and after a design or proces s change that could affect this parameter.

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 4: READ CYCLE TIMING DIAGRAM

FIGURE 5: WE# CONTROLLED BYTE-PROGRAM CYCLE TIMING DIAGRAM

310 ILL F03.2

CE#

ADDRESS A18-0

OE#

WE#

DQ 7-0

TCLZ TOH

DATA VALIDDATA VALID

TOLZ

TOE

TCE TCHZ

TOHZ

TRC TAA

310 ILL F04.1

CE#

OE#

WE#

TDH

TDS

TOES

TCS

TAS TAH

TWP TWPH

TOEH

TCH

TDS

TDH

TBP

ADDRESS A18-0

DQ 7-0

BYTE-PROGRAM SETUP COMMAND

I0H DATA VALID

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 6: CE# CONTROLLED BYTE-PROGRAM CYCLE TIMING DIAGRAM

FIGURE 7: RESET COMMAND TIMING DIAGRAM

310 ILL F05.1

CE#

OE#

WE#

TDH

TDS

TOES

TCPH

TAS TAH

TCS TCH

TOEH

TCP

TDS

TDH

TBP

ADDRESS A18-0

DQ 7-0

BYTE-PROGRAM SETUP COMMAND

I0H DATA VALID

310 ILL F06.0

CE#

OE#

WE#

TDS

TDH TRST

ADDRESS A18-0

DQ 7-0 FFH

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 8: CHIP-ERASE TIMING DIAGRAM

FIGURE 9: SECTOR-ERASE TIMING DIAGRAM

310 ILL F07.0

CE#

OE#

WE# TDH

TDS TDH

TSCE

TDS

ADDRESS A18-0

DQ 7-0 30H

SETUP

COMMAND EXECUTE

COMMAND

30H

310 ILL F08.0

CE#

OE#

WE# TDH

TAH

TAS

AIN

TDS TDH

TSE

TDS

ADDRESS A18-0

DQ 7-0 20H

SETUP

COMMAND EXECUTE

COMMAND

D0H

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 10: SOFTWARE DATA UNPROTECT DISABLE TIMING DIAGRAM

FIGURE 11: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM

310 ILL F09.4

OE#

CE#

WE#

ADDRESS TPAH

TPAS

TPCH

TPCP

NOTE: A. ADDRESSES ARE LATCHED INTERNALLY ON THE RISING EDGE OF:

1.OE# IF CE# IS KEPT AT LOW ALL TIME.

2.CE# IF OE# IS KEPT AT LOW ALL TIME.

3.THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED.

B. ABOVE ADDRESS VALUES ARE IN HEX.

C. ADDRESSES > A12 ARE "DON'T CARE"

1823 1820 1822 0418 041B 0419 041A

310 ILL F10.4

OE#

CE#

WE#

ADDRESS TPAH

TPAS

TPCH

TPCP

NOTE: A. ADDRESSES ARE LATCHED INTERNALLY ON THE RISING EDGE OF:

1.OE# IF CE# IS KEPT AT LOW ALL TIME.

2.CE# IF OE# IS KEPT AT LOW ALL TIME.

3.THE FIRST PIN TO GO HIGH IF BOTH ARE TOGGLED.

B. ABOVE ADDRESS VALUES ARE IN HEX.

C. ADDRESSES > A12 ARE "DON'T CARE"

1823 1820 1822 0418 041B 0419 040A

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 12: DATA# POLLING TIMING DIAGRAM

FIGURE 13: TOGGLE BIT TIMING DIAGRAM

310 ILL F11.0

CE#

OE#

WE#

NOTE

TOE

TOEH

TCE

TOES

D# D

ADDRESS A18-0

DQ 7-0

NOTE: THIS TIME INTERVAL SIGNAL CAN BE TSE or TBP DEPENDING UPON THE SELECTED OPERATION MODE.

310 ILL F12.0

CE#

OE#

WE#

NOTE

TWO READ CYCLES

WITH SAME OUTPUTS

TOEH

TOE TOE

TOES

TCE TCE

ADDRESS A18-0

DQ6

NOTE: THIS TIME INTERVAL SIGNAL CAN BE TSE or TBP DEPENDING UPON THE SELECTED OPERATION MODE.

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS

FIGURE 15: A TEST LOAD EXAMPLE

310 ILL F13.1

REFERENCE POINTS OUTPUTINPUT

VHT

VLT

VHT

VLT

VIHT

VILT

AC test inpu ts ar e dri ven at VIHT (2.4V) for a logic “1” and VILT (0.4 V ) for a logic “0”. Me asur emen t reference point s for

inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Input rise and fall times (10% ↔ 90%) are <10 ns .

Note: VHT - VHIGH Test

VLT - VLOW Test

VIHT - VINPUT HIGH Test

VILT - VINPUT LOW Test

310 ILL F14.2

T O TESTER

TO DUT

CLRL LOW

RL HIGH

VDD

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 16: BYTE-PROGRAM FLOWCHART

310 ILL F15.3

Yes

Last

Address

Read

End-of-Write

Detection

Yes

Data

Verifies?

Yes

Programming

Completed?

Programming

Completed

Address Programming

Failure

Load Address

and Data &

Start

Programming

Execute Byte-

Program Setup

Command

Initialize

Address

Start

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 17: WRITE WAIT OPTIONS

310 ILL F16.2

Read byte

Yes

Does DQ6

match?

Program/Erase

Completed

Read same

byte

Program/Erase

Initiated

Toggle Bit

W ait TBP or

TSE

Program/Erase

Completed

Program/Erase

Initiated

Internal Timer

Read DQ7

Is DQ7 =

true data?

Program/Erase

Completed

Program/Erase

Initiated

Data# Polling

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 18: SECTOR-ERASE FLOWCHARTS

310 ILL F17.5

Yes

Last

Sector?

Verify

FFH

Erase

completed?

Last

Address?

Device

Erased

Ex ecute Two Step

Sector-Erase

Command

Increment

Byte

Address

Next Sector

Address

End-of-Write

Detection

Read FFH from

Selected Byte

Address

Initialize

Sector Address

Start

Sector-Erase

Completed Erase Error

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

FIGURE 19: SOFTWARE PRODUCT ID FLOW

Execute Read ID

Command (90H) to

Enter Read-ID mode

Read Address 0000H

MFG's ID =

SST (BFH)

Read Address 0001H

Device ID =

28SF040 (04H)

Execute Reset

Command (FFH) to

Exit from

Read-ID mode

310 ILL F18.5

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

PRODUCT ORDERING INFORMATION

Valid combinations for SST28SF040A

SST28SF040A-90-4C-NH SST28SF040A-90-4C-EH SST28SF040A-90-4C-PH

SST28SF040A-120-4C-NH SST28SF040A-120-4C-EH

SST28SF040A-120-4I-NH‡SST28SF040A-120-4I-EH‡

Valid combinations for SST28VF040A

SST28VF040A-150-4C-NH SST28VF040A-150-4C-EH

SST28VF040A-200-4C-NH* SST28VF040A-200-4C-EH*

SST28VF040A-200-4I-NH*‡SST28VF040A-200-4I-EH*‡

Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

*Not recommended for new designs.

‡The software Chip-Erase function is not supported by the industrial temperature part.

Please contact SST if you require this function for an industrial temperature part.

Non-Pb:Several devices in this data sheet are also offered in non-Pb (no lead added) packages.

The non-Pb part number is simply the standard part number with the letter “E” added to the end of the pack age code.

The non-Pb package codes corresponding to the packages listed above are NHE and EHE.

Device Speed Suffix1 Suffix2

SST28xF040A - XXX -XX-XX

Package Mo d ifie r

H = 32 leads or pins

Package Ty pe

E = TSOP (type 1, die up, 8mm x 20mm)

N = PLCC

P = PDIP

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

200 = 200 ns

150 = 150 ns

120 = 120 ns

90 = 90 ns

Function

F = Chip- or Sector-Erase

Byte- or Word-Program

Voltage

S = 4.5-5.5 V

V = 2.7-3.6 V

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

PACKAGING DIAGRAMS

32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC)

SST PACKAGE CODE: NH

.040

.030

.021

.013 .530

.490

.095

.075

.140

.125

.032

.026

.032

.026

.029

.023

.453

.447

.553

.547

.595

.585

.495

.485 .112

.106

.042

.048

.042

.015 Min.

T OP VIEW SIDE VIEW BO TT OM VIEW

1232

.400

BSC

32-plcc-NH-3

Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.

4. Coplanarity: 4 mils.

.050

BSC

.050

BSC

Optional

Pin #1

Identifier .020 R.

MAX. R.

x 30˚

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 20MM

SST PACKAGE CODE: EH

0.15

0.05

20.20

19.80

18.50

18.30

0.70

0.50

8.10

7.90 0.27

0.17

1.05

0.95

32-tsop-EH-7

Note: 1.Complies with JEDEC publication 95 MO-142 BD dimensions,

although some dimensions may be more stringent.

2.All linear dimensions are in millimeters (max/min).

3.Coplanarity: 0.1 mm

4.Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25mm between leads.

Pin # 1 Identifier

0.50

BSC

1mm

1.20

max.

DETAIL

0.70

0.50

0˚- 5˚

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

32-PIN PLASTIC DUAL IN-LINE PINS (PDIP)

SST PACKAGE CODE: PH

TABLE 14: REVISION HISTORY

Number Description Date

04 •2002 Data Book May 2002

05 •Removed WH package

•Part number changes - see page 22 for additional information

•Clarified the Test Conditions for VDD Read Current parameter in Table 6 and

Table 7 on page 8

– Addre ss input = VILT/VIHT

Mar 2003

32-pdip-PH-3

Pin #1 Identifier

Base

Plane

Seating

Plane

Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.

2. All linear dimensions are in inches (max/min).

3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.

.200

.170

7˚

4 PLCS.

.600 BSC

.100 BSC .150

.120

.022

.016

.065

.045

.080

.070

.050

.015

.075

.065 1.655

1.645

.012

.008

0˚

15˚

.625

.600

.550

.530

Data Sheet

4 Mbit SuperFlash EEPROM

SST28SF040A / SST28VF040A

Silicon Stor age Technol ogy, In c. • 117 1 Sonor a C ourt • Sunnyvale, CA 94086 • Teleph one 408-73 5-91 10 • Fax 408-735 -90 36