MOTOROLA SEMICONDUCTOR TECHNICAL Order this document by MTD15N06VUD DATA E DesignerkTMData Sheet -- TMOS VTM Power Field Effect Wansistor DPAK for Surface Mount N-Channel Enhancement-Mode Silicon Gate TMOS V is a new technology designed to achieve an on-resistance area product about one-half that of standard MOSFETS. This new technology more than doubles the present cell density of our 50 and 60 volt TMOS devices. Just as with our TMOS E-FET designs, TMOS V is designed to withstand high energy in the avalanche and commutation modes. Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls, these devices are pa~cuiarly well suited for bfidge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ,. ~,i~ i:,d~l" .:!,'. .,> :++~+:;, .\.,,,.,..:& ,~,,! *::<$.*".,:,+,?$> D -+., ,,~\t, ,,:..< ,. $$\tL:!,Ji':*,,t.. ,.JI$.sr>::\,, ... {' ~. Y(\ ..!. .,.,, , New Features of TMOS V On-resistance Area Product about On&half that of Standard `$*:' "'*4 MOSFETS with New Low Voltage, Low RDS(on) Technology .,.i$~, .,. ..,, s,y:, Faster Switching than E-FET Predecessors .>..,,;~~i .'.-:. + .$?' .J$. \\., .t :::. ~.~.)., ./\-.:t ~,,,.$ &.$*. ~., ~ Features Common to TMOS V and TMOS E-FETS f${:kqp> ~,.:.:< Avalanche Energy Specified ~+ -- CASE 369A-13, Style 2 DPAK Surface Mount s " * . [DSS and VDS(on) Specified at Elevated Tempe~atur~ " Static Parameters are the Same for both TMO$i~ and TMOS E-FET Surface Mount Package Available in 16 mrn3~~Ti*/2500 Unit Tape& Reel, ~, ,~j;:.>:$:\.: Add T4 Sufix to Part Number .-~~b ~. >,,,, .+*;,,? ,>* ,>.;i.le "!*.:,,:,: .$$\-.. noted) MAXIMUM RATINGS (Tc = 25C unle~,wse *,++ .,..,, \\. "'~~~kHating Drain-t&Source Voltage Drain-tMate $:fr >*1+$ Voltage (RG@%+$%&~) Gat+ttiource Voltag&%'@nuous ~~>+on-repetitive (tps 10 ms) Drain Current -.,~~tinu~~s *:WMUOUS To@lP@&r Dissipation VDSS 60 Vdc 60 Vdc VGS VGSM * 15 + 25 Vdc Vpk ID 15 12 53 Adc Apk 60 0.4 2.1 Watts W/"c Watts PD @ 25C(l ) and Storage Temperature Range TJ, Tstg *,' ?j%gle Pulse Drain-t&Source Avalanche Energy -- Stating TJ = 25C ` .:*L' "'`-<' (vDD = 25 Vdc, VGS = 5.o Vdc, Peak IL = 15 Apk, L = 1.0 mH, RG = 25 ~) ,~,, Thermal Resistance -- Junction to Case -- Junction to Ambient -- Junction to Ambient(l ) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Unit VDGR IDM 10 KS) Total Po&'%sipation DW&&8&e 25C $~~~%ng Value iD @ 1Oo"c >Y+*~~lnQle pulse (tps Symbol -55to 175 "c EAS 113 mJ R8JC ROJA ReJA 2.5 100 71.4 `cm TL 260 `c (1) When surface mounted to an FR4 board using the minimum recommended pad size. Designer's Dsts for "Worst Csse" Conditions -- The Designer's Date Sheet permits the design of most circuits entirely from the information presented. SOA Mmit curves -- repreaenfing boundaries on device characteristics -- are given to facihtate %orat case" design. E-FET, Designer's, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark Thermal Clad is a trademark of the Bergquist Company. of Motorola, Inc. REV 2 @ Motorola, MOTOROLA Inc. 1997 @ MTD15N06VL ELECTRICAL CHARACTERISTICS ~J = 25C unless otherwise noted) Characteristic Symbol Min Typ Max V(BR)DSS Go -- -- -- 66 -- -- -- -- -- 10 100 -- -- 100 Unit OFF CHARACTERISTICS (Cpk 2 2.0) (3) Drain-t&Source Breakdown Voltage (VGS = O Vdc, ID = 0.25 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = O Vdc) (VDS = 60 Vdc, VGS = O Vdc, TJ = 150C) IDSS Gat*Body iGSS Leakage Current (VGS = f 15 Vdc, VDS = O Vdc) ON CHARACTERISTICS ,,,:... ~,t~:..,, ,,<<.:,:<' `~,:,., .\*,.. *,.;, ,., ,, (Cpk 2 2.0) (3) Static Drain-t&Source On-Resistance (VGS = 5.0 Vdc, ID = 7.5 Adc) (Cpk 2 2.0) (3) 1.0 -- RDS(on) 9FS ~:'q:$c,\\\,8:b ,~~, .;>... :x), `~~>,. ,* .,**,:,,,> ... .,~ .J,k. .~? `.\?).. ~.. },.\. .,,... .~, ~. ?,. *Y,, cl~. `.~:.\!. (2) Delay Time (VDD = 30 Vdc, IQ+ 15&dc, Rise Tme 10 -- mhos `F td(on) -- 11 50 tr -- 150 210 td(off) -- 27 160 tf -- 70 140 QT -- 12 20 Q1 -- 3.0 -- Q2 -- 7.0 -- QS -- 11 -- -- -- 0.96 0.85 1.6 -- trr -- 63 - ta -- 42 -- tb -- 21 -- QRR -- 0.140 -- -- -- 3.5 4.5 -- -- -- 7,5 -- -- -- Delay ~me ,,.$!~ >$, Fall Tme Gate Charge ~i%:;:" ? ,&, *. s.>::!,, *,J ,$:**$\ tv. ~J SOURCE-DRAIN DIODE CH~%:@@lSTICS Forward On-Voltage (1),, `J'%l~$ ,+ `~$" ~~i, : ,.,i<.': .,,*,> .$. ~.>.., $ `$'.:$, \.\>%,~,~ Reverse Reco~$~% .3 tih, .+.~*..>,+ .i~,.,..,it ~,,. ,...;$..~.~~ ~> ~ *: ~ `Q' .~,i ?>., ,i$$:,? ,,,, .}Re$@Recove~ l@~AL Ohm `vDs=''%''=ovdc' - Reverse Transfer Capacitance Turn-ff mV/oC Vdc VDS(on) DYNAMIC CHARACTERISTICS Turn-n 1.5 4,0<+$$ ,."?~~,g ,,<., :~,. ,,, -- (VDS = 8.0 Vdc, ID = 7.5 Adc) CHARACTERISTICS .... *). ,.*f:., ,,, ,.:,,s:,. ., :,<, Vdc <;&@,~.'? VGS(th) Drain-t&Source On-Voltage (VGS = 5.0 Vdc, ID = 15 Adc) (VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150"C) Forward Transconductance mV/oC @dc (1) Gate Threshold Voltage (VDS = VGS, ID= 250 pAdc) Temperature Coefficient (Negative) SWITCHING Vdc (IS =15 Adc, VGS = O Vdc) (1s = 15 Adc, VGS = O Vdc, TJ = 150C) ([S =15 Adc, VGS = O Vdc, dl~dt = 100 WW) Stored Charge Vdc VSD ns WC PACWGE INDUCTANCE Infernal Drain Inductance (Measured from contact screw on tab to center of die) (Measured from the drain lead 0.2Y from package to center of die) LD Internal Source Inductance (Measured from the source lead 0.25" from package to source bond pad) LS nH nH (1) Pulse Test Pulse Widths 300 W, DUV Cycles 270. (2) Switching characteristics are independent of operating junction temperature. Max limit - Typ (3) Reflects typical values. Cpk= 2 3 x SIGMA Motorola TMOS Power MOSFET Transistor Device Data MTD15N06VL WPICAL ELECTRICAL CHARACTERISTICS 50 vGs = 10V TJ = 25C gv 8d 45 40 35 5V 30 25 20 15 10 5 0 `01234567 8glo vDs, DRAIN-TWOURCEVOLTAGE Figure 1. On-Region (VOLTS) Characteristics 1 iD, DRAIN CURRENT (AMPS) Figure 3. On-Resistanc&~~e~@'us Drain Current and T&p~%$ure Figure 4. On-Resistance versus Drain Current and Gate Voltage 100 10 -.- -50 -25 0 25 50 75 100 TJ, JUNCTION TEMPERATURE 125 150 ~C) Figure 5. On-Resistance Variation with Temperature Motorola TMOS Power MOSFET Transistor Device Data 175 0 `O 5 10 15 20 vDs, DRAIN-TGSOURCE 25 30 35 40 45 VOLTAGE (VOLTS) Figure 6. Drain-To-Source Leakage Current versus Voltage 3 MTD15N06VL POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (At) are determined by how fast the FET input capacitance can be charged by current from the generator. The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the td(off). on-state when Calculating The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used, In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimental analysis of the drive circuit so that At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring whieg is common to both the drain and gate current paths, prowvoltage at the source which reduces the gate dti~ `Wwnt. The voltage is determined by Ldi/dt, but sincedt~~~ha function of drain current, the mathematical sO~,u@;#ComPlex. The MOSFET output capacitance alqQ,$$~t~flicates the mathematics. And finally, MOSFETs+~V~~%lle internal gate resistance which effectively adds to~'~~ resistance of the driving source, but the internal, ~@~tance is difficult to measure and, consequently, is q,st~xtfled. The resistive switchin~'~,@&,,$ariation versus gate resis- t = alG(Av) During the rise and fall time interval when switching a resistive load, VGS remains vitiually constant at a level known as the plateau voltage, VSGp. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RGNGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSp are read from the gate charge curve. During the turn-on and turn+ff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG ciss In ~GG/(VGG 4 - VGSP)] ,.!, tance (Figure 9) show~~~~fiical switching performance is .,,.:,:,s+. affected by the p~Qsit&:?:&lrcuit elements. If the parasitic were not presen<~&$#lope of the cuwes would maintain a >. >{[c: ~~ value of uni~~~~@less of the switching speed. The circuit used to o~@I,m;&&,$data is constructed to minimize common inductani~~f$ the drain and gate circuit loops and is believed rea~~achi&able with board mounted components. Most p~~~ ~ctronic loads are inductive; the data in the figure is ,i~t~e~tiith a resistive load, which approximates an optimally .+~!~$ti~bed inductive load. Power MOSFETS may be safely op"J'crated into an inductive load: however. snubbina reduces *} *. switching losses. Motorola TMOS Power MOSFET Transistor Device Data MTD15N06VL 10 30 I \, 9 * / QT ~ T 8 24 ~ VGS 7 21 ~ \ 6 ? 18 g / -- Q2 \* 4 15 : ./ 12 g / 3 g= \ , / 2 1 Q3 o I o UC 27P 5 TJ = 25C ID=15A VDS - 6! - 3P Od 10 15 20 25 30 35 RG, GATE RE~~&i@HMS) <.:i,' ,... Qg, TOTAL GATE CHARGE (nC) . *,\.\>.~.,~ Figure 9. Re)~tlv&:$witching Time Variatioq$~.p~,s Gate Resistance ,,,~,.$. *f.>i*.&. ,.,,. ,., Figure 8. Gat+To-Source and Drain-To-Source Voltage versus Total Charge s,u:,.<:~' The Forward .~f~$ed~afe Operating Area curves define the maximum ~~~$~'neous drain-to-source voltage and drain curreq~h{:q transistor can handle safely when it is forward bias'~<:~urves are based upon maximum peak junction t~~[abre and a case temperature (Tc) of 25C. Peak rep~tlvq: flulsed power limits are determined by using the ~~$M~Fresponse data in conjunction with the procedures ~~kd~,ussed in AN569, `Transient Thermal Resistancffieneral ~~~~hta and Its Use." `V Switching between the off+tate and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 vs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(M~) - Tc)/(ReJc). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reli- Motorola TMOS Power MOSFET Transistor Device Data able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain- to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with indust~ custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated. 5 MTD15N06VL SAFEOPERATING AREA 100 n -- = -- 0.1 0.1 ------ `--- I t RDS(On)LIMIT THERMAL LIMIT PACWGE LIMIT I I I 11111 1 I I VDS, DRAIN-T&SOURCE 100 10 1 VOLTAGE (VOLTS) Figure 11. Maximum Rated Forward Biased Safe Operating Area -- \i.\,.:* `.:..*, ~,::$ *,: .. `" Figure 13. Thermal Response TIME Figure 14. Diode Reverse Recovery Waveform 6 Motorola TMOS Power MOSFET Transistor Device Data MTD15N06VL INFORMATION FOR USING THE DPAK SURFACE MOUNT PACWGE RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS -- Surface mount board layout is a cfitical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geomet~, the packages will self align when subjected to a solder reflow process. .~,.,.*,, ~ POWER DISSIPATION FOR &,~$~~ACE MOUNT DEVICE -- The power dissipation for a surface mount device is q,, S,~%,,~ `?he surface mount packages. One is to increase the area of the function of the drain pad size, These can vary from ~a~~t$ `s' drain pad. By increasing the area of the drain pad, the power minimum pad size for soldering to a pad size given f$~..,'"* dissipation can be increased. Although one can almost double maximum power dissipation. Power dissipation for ~ su~ce the power dissipation with this method, one will be giving up mount device is determined by TJ(m~), the m~ti~ rated area on the printed circuit board which can defeat the purpose a graph of junction temperature of the die, R9JA, the ther~#~KgsRtance of using surface mount technology, For example, from the device junction to ambient, a,~~~~~~perating HeJA versus drain pad area is shown in Figure 15, temperature, TA. Using the values provid-,t~e"data sheet, *(:~. .,,.x\ `>~ z 100 PD can be calculated as follows: ,~3~,*.+ -g\bkYp 0 Board MateHal = 0.0625" .'. `;&?,y\},{\ `!::+, ..,1. F .,.., o G-1 OFR4, 2 oz Copper 1 1 z ~ The values for the ~~@~$ are found in the maximum ratings table on the dah,s~et. Substituting these values into the equation for ~+~pbi~~t temperature TA of 25C, one can calculate the p~~~+@sipation of the device. For a DPAK device, PD ~k+yl~ted as follows. .\."$>) .>,i:* . `L ~~ +m+ /' TA = 25C I fi~60 mm $2 Zo u+ u ~L 1.75 Watts / g~60 / / 3.0 Watis I An I , !" / / 5.0 Watts I I 3 u 20 o I 2 4 I 6 6 10 A, AREA (SQUARE INCHES) `board to achieve a power dissipation of 2.1 WaW. There are other alternatives to achieving higher power dissipation from Motorola TMOS Power MOSFET Transistor Device Data Figure 15. Thermal Resistance versus Drain Pad Area for the DPAK Package @ypicai) 7 MTD15N06VL SOLDER STENCIL GUIDELINES Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. Solder stencils are used to screen the optimum amount. These stencils are typically 0,008 inches thick and may be made of brass or stainless steel. For packages such as the SG59, SC-70/SOT-323, SOD-1 23, SOT-23, SOT-1 43, SOT-223, S&8, SO-1 4, SO-16, and SMB/SMC diode packages, the stencil opening should be the same as the pad size or a 1:1 registration. This is not the case with the DPAK and D2PAK packages. If one uses a 1:1 opening to screen solder onto the drain pad, misalignment and/or `Yombstoning" may occur due to an excess of solder. For these two packages, the opening in the stencil for the paste should be approximately 50% of the tab area, The opening for the leads is still a 1:1 registration. Figure 16 shows a typical stencil for the DPAK and D2PAK packages. The pattern of the opening in the stencil for the drain pad is nOt critical as long as it allOWS approximately 50% of the pad to be covered with paste. N N" N N~ ,%:?*V N SOLDER PASTE OPENINGS ,,,,i \'.:$ ,.:)$\\,:, ., ,;;$:4, <'tt..$~~ SOLDERING The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. Always preheat the device, ~r,~ ~*.t... ".~j+ ~ \~ . When shiftinq ~@tpreheating to soldering, the maximum temperatu:#~$&ent shall be 5C or less. After s~$;ti$fias been completed, the device should be allo~~e~~$o cool naturally for at least three minutes. coolingshould be used as the use of forced q~al j$qllm will increase the temperature gradient and result ~. ~t,~n$atent failure due to mechanical stress. ". "~~? ) .,,\. `$~.&~Mechanical stress or shock should not be applied during the preheat and soldering `"$ cooling. .:~<,: ... .. The delta temperature be~een should be 10OC or less.* When preheating and soldering, the temperaturq,,$$~e leads and the case must not exceed the -U'rn temperature ratings as shown on the data #~~,.~hen using infrared heating with the reflow sok$$~~tiethod, the difference shall be a maximum of ~ti~$~~~~"' b PRECAUTIONS The soldering temperature and ti~e'~%{~ not exceed * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device, Due to shadowing and the inability to set the wave height to incorporate other surface mount components, the D2PAK is not recommended for wave soldering; 8 Motorola TMOS Power MOSFET Transistor Device Data - MTD15N06VL TYPICALSOLDER HEATING PROFILE For any given circuit board, there will be a group of control setiings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the nefi. Figure 17 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, andthetype of board or substrate material being used. This profile shows temperature versus time. The STEP1 STEP2 STEP3 PREHEAT VENT HEATING ZONE1 "SOAR ZONES2 &5 "~Mp , "RAMP II I 2orc - - DESIRED iURV; FOR HIGH line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The ~o profiles are based on a high density and a low density board. The Wtronics SMD31 O convectionAnfrared reflow soldering system was used to generate this profile. The type of solder used was 6236/2 Tin Lead Silver with a melting point between 177-189C. When this type of furnace is used for solder reflow work, the circuit ~rds and solder joints tend to heat first. The components}: &~Yboard are then heated by conduction. The circuit b$~r~~~cause it has a large surface area, absorbs the the~~$,~tiergy more efficiently, then distributes this energ~~~$~i~~a components. Because of this effect, the main bod~8~a@~ponent may be up to 30 degrees cooler than the,l~#~$~t solder joints. .. &\ . ,+. ,.s,. ~;] ,t~ ,:~t., .}. .*, **? ZON<S 3&!# ZONES 4&7 :j@AW `p" "SPIKP ,,,,., ~:J}::4\$,,.34. 170"C ~~ - 205 TO 219C PEAK AT SOLDER JOINT 150c 1500c - - 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBL~ loo"c - - DESIRED CURVE FOR LOW MASS ASSEMBLIES +: ,,<.. y~ ~ ` TIME (3 TO 7 MINUTES TOTAL) Motorola TMOS Power MOSFET Transistor Device Data - TM~ 9 PACWGE DIMENSIONS NOTES 1, DIMENSIONING Y14.5M, 1982, 2. ~NTROLLING ANO TOLERANCING OIMENSION PER ANSI INCH. F s SME 2 PIN 1. GATE 2. OWIN 10 u 0.020 P*J50,3 O.* I "Wl v .&8&2.. `k i ` ---" ` 0.51 0.51 --" I 1.27 I ` -- `-- Motorola TMOS Power MOSFET Transistor Device Data MTD15N06VL NOTES . Motorola TMOS Power MOSFET Transistor Device Data 11 MTD15N06VL ~.)?,> ~ ~ .:~~<3:\>J$yt\ .YF .\. "$.;,,, .\ `{*:it:'. ,** ,, `t::$>.@~:@* .'s~'}: . ~.. .*$, .?:,:,:;:?,,l.tt~ `.$>.k, $,,:. j?,, .:.* `**":$,"$*. .,. ":::~!:t,,.,:r~ r .,:C!$.?. ~ij> \i. " r:,+ , *;ttti*\$?/ .ij..>'.'~.,:., ~1. ,>., . . .. `.. ,T$$\..:~i+,i. ..\J< ~.1,. y:;, ,,,] :,.,. "'.$% s ,,~> $.,/>s.?< ,Q$., ,1:> ~.~:t,,l<, \ ,*J$, .&\!,\* ,$ .?{(: .:~. `..,, ~h'?$s.it.y,$ Motorola resew~~~~g~tt omakechangesw ithoutfutihern oticetoa nyproductaherein. Motorola makes nowsrran~, representation orguarantee regardng the suitabili~~j~s~oducts for any particular purpose, nor does Motorola assume any Iiatihty ariaing out of the application or use of any product or circuit, and specificauy~aws any and all liabili~, including without limitation consequential or incidental damagea. Typicay parameter which may be provided in Motorola data she~~ anworspecificafions can and do vary indifferent applications and actual petiormance may vary overtime. All operating parameters, including `Typicals" mu:~@~v&ti~ed foreach cuatomerapplication bycustomer's technical expetie. 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Motorola, Inc. is an Equal Opportunity/Afirmative Action Employer. I Mfax is a trademark of Motorola, Inc. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Dstrtbution; P.O. Box 5405, Denver, Colorado 80217. 30~7%2140 or 1+OW1 -2447 MfaxTM: RMFAXO@email,aps.mot.com - TOUCHTONE 602-2W609 - US& Canada ONLY 1+0-77+1 JAPAN Nippon Motorola Ltd.; Tatsum%PWLDC, 6F Seibti@su@enter, >142 Tateumi Kottiu, Tokyo 135, Japan. 81+3521+315 848 ASMIPACIFIC Motorola Semiconductors H.K, Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-2~29298 fNTERNET: http://www.mot.cotiSPS/ MOTOROLA o MTD15N06VUD