MTD15N06VLT4 - Motorola / Freescale Semiconductor

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA Order this document

by MTD15N06VUD

DesignerkTMData Sheet

TMOS VTM—Power Field Effect Wansistor

DPAK for Surface Mount

N-Channel Enhancement-Mode Silicon Gate

TMOS Vis anew technology designed to achieve an on–resis-

tance area product about one–half that of standard MOSFETS. This

new technology more than doubles the present cell density of our

50 and 60 volt TMOS devices. Just as with our TMOS E–FET

designs, TMOS Vis designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high

speed switching applications in power supplies, converters and

power motor controls, these devices are pa~cuiarly well suited for d~l”,. ~,i~

i:,.:!,’.

bfidge circuits where diode speed and commutating safe operating .,>

~+:;,:++ ,.,..:&

.\.,, ,~,,!

areas are critical and offer additional safety margin against *::<$.*”.,:,+,?$>

D-+. ~+

unexpected voltage transients. ,,~\t, ,

,,:..<,.

$$\tL:!,Ji’:*,,t..

,.JI$.sr>::\,,...

New Features of TMOS V~.

{’

Y(\

..!..,.,,,

●On–resistance Area Product about On&half that of Standard ‘$*:’ “’*4

MOSFETS with New Low Voltage, Low RDS(on) Technology .,.i$~, CASE 369A-13, Style 2

.,.

●Faster Switching than E–FET Predecessors DPAK Surface Mount

..,, s,y:,

.>..,,;~~i .’.-:.

.$?’ .J$.s

\\.,.t :::.

Features Common to TMOS Vand TMOS E-FETS ~.~.).,./\-.:t~,,,.$

&.$*.~.,~

f${:kqp>

●Avalanche Energy Specified ~,.:.:<

“[DSS and VDS(on) Specified at Elevated Tempe~atur~ “

*Static Parameters are the Same for both TMO$i~ and TMOS E-FET

—.Surface Mount Package Available in 16 mrn3~~Ti*/2500 Unit Tape& Reel,

Add T4 Sufix to Part Number ~, ,~j;:.>:$:\.:

.-~~b~. >,,,,

.+*;,,? ,>*

“!*.:,,:,:.$$\-..,>.;i.le

MAXIMUM RATINGS (Tc =25°C unle~,wse noted)

*,++ .,..,,

“’~~~kHating

\\. Symbol Value Unit

Drain-t&Source Voltage $:fr >*1+$ VDSS 60 Vdc

Drain-tMate Voltage (RG@%+$%&~) VDGR 60 Vdc

Gat+ttiource Voltag&%’@nuous VGS *15 Vdc

~~>+on-repetitive (tps 10 ms) VGSM +25 Vpk

Drain Current -.,~~tinu~~s ID 15 Adc

*:WMUOUS @1Oo”c

>Y+*~~lnQle pulse (tps 10 KS) iD 12

IDM 53 Apk

Total Po&’%sipation PD 60 Watts

DW&&8&e 25°C 0.4

To@lP@&r Dissipation @25°C(l )W/”c

2.1 Watts

$~~~%ng and Storage Temperature Range TJ, Tstg –55to 175 “c

*,’ ?j%gle Pulse Drain-t&Source Avalanche Energy —Stating TJ =25°C EAS 113

‘“’‘-<’ (vDD =25 Vdc, VGS =5.o Vdc, Peak IL =15 Apk, L=1.0 mH, RG =25 ~) mJ

.:*L’

,~,, Thermal Resistance —Junction to Case R8JC 2.5 ‘cm

—Junction to Ambient ROJA 100

—Junction to Ambient(l )ReJA 71.4

Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds TL 260 ‘c

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer’s Dsts for “WorstCsse” Conditions—The Designer’s Date Sheet permits the design of most circuits entirely from the information presented. SOA Mmit

curves —repreaenfing boundaries on device characteristics —are given to facihtate %orat case” design.

E-FET, Designer’s, and TMOS Vare trademarks of Motorola, Inc. TMOS is aregistered trademark of Motorola, Inc.

Thermal Clad is atrademark of the Bergquist Company.

REV2

@MOTOROLA

@Motorola, Inc. 1997

MTD15N06VL

ELECTRICAL CHARACTERISTICS ~J =25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

OFF CHARACTERISTICS

Drain-t&Source Breakdown Voltage (Cpk 22.0) (3) V(BR)DSS Go Vdc

(VGS =OVdc, ID =0.25 mAdc) — —

Temperature Coefficient (Positive) —66 —mV/oC

Zero Gate Voltage Drain Current IDSS @dc

(VDS =60 Vdc, VGS =OVdc) ——10

(VDS =60 Vdc, VGS =OVdc, TJ =150°C) 100

——

Gat*Body Leakage Current (VGS =f15 Vdc, VDS =OVdc) iGSS — — 100

ON CHARACTERISTICS (1) ,,,:...

~,t~:..,,,,<<.:,:<’

‘~,:,.,.\*,..

*,.;,,.,,,

Gate Threshold Voltage (Cpk 22.0) (3) ....

*). ,.*f:.,

VGS(th) ,,,,.:,,s:,.., :,<, Vdc

(VDS =VGS, ID= 250 pAdc) 1.0 1.5 <;&@,~.’?

Temperature Coefficient (Negative) —4,0<+$$,.”?~~,g mV/oC

,,<.,

Static Drain–t&Source On-Resistance

:~,.

(Cpk 22.0) (3) RDS(on) ,,, Ohm

(VGS =5.0 Vdc, ID =7.5 Adc) —

Drain-t&Source On-Voltage VDS(on) Vdc

(VGS =5.0 Vdc, ID =15 Adc)

(VGS =5.0 Vdc, ID =7.5 Adc, TJ =150”C)

Forward Transconductance (VDS =8.0 Vdc, ID =7.5 Adc) 9FS ~:’q:$c,\\\,8:b 10 —mhos

DYNAMIC CHARACTERISTICS ,~~,.;>...:x),‘~~>,.

.,**,:,,,>

,* ...

-‘vDs=’’%’’=ovdc’

Reverse Transfer Capacitance .,~ ‘F

SWITCHING CHARACTERISTICS (2) .J,k..~?

‘.\?)..~..},.\.

.,,...

Turn-n Delay Time .~.?,.*Y,,

~,cl~. td(on) —11 50

‘.~:.\!.

Rise Tme (VDD =30 Vdc, IQ+ 15&dc, tr —150 210

Turn-ff Delay ~me td(off) —27 160

Fall Tme ,,.$!~

>$, tf —70 140

Gate Charge QT —12 20

Q1 —3.0 —

~i%:;:”?Q2 —7.0 —

,&, *.

s.>::!,,*,J

,$:**$\tv.~JQS —11 —

—

SOURCE-DRAIN DIODE CH~%:@@lSTICS

Forward On-Voltage (1),, ‘J’%l~$ (IS =15 Adc, VGS =OVdc) VSD Vdc

‘~$”~~i,

,.,i<.’: (1s =15 Adc, VGS =OVdc, TJ =150°C) —0.96 1.6

: .,,*,> .$.

~.>..,‘$’.:$,

$\.\>%,~,~ —0.85 —

Reverse Reco~$~% trr —63 – ns

.3 tih,

.+.~*..>,+

.i~,.,..,it~,,. ([S =15 Adc, VGS =OVdc, ta

,...;$..~.~~~>~ —42 —

*: ~‘Q’

.?>., dl~dt =100 WW)

,i$$:,?~,i,,,,.}- tb —21 —

Re$@Recove~ Stored Charge QRR —0.140 —WC

l@~AL PACWGE INDUCTANCE

Infernal Drain Inductance LD nH

(Measured from contact screw on tab to center of die) —3.5 —

(Measured from the drain lead 0.2Y from package to center of die) —4.5 —

Internal Source Inductance LS nH

(Measured from the source lead 0.25” from package to source bond pad) —7,5 —

(1) Pulse Test Pulse Widths 300 W, DUV Cycles 270.

(2) Switching characteristics are independent of operating junction temperature.

(3) Reflects typical values. Cpk= Max limit -Typ

3xSIGMA

2Motorola TMOS Power MOSFET Transistor Device Data

MTD15N06VL

WPICAL ELECTRICAL CHARACTERISTICS

50 TJ =25°C vGs =10V gv 8d

35 5V

‘01234567 8glo

vDs, DRAIN-TWOURCEVOLTAGE (VOLTS)

Figure 1. On-Region Characteristics

Figure 3. On-Resistanc&~~e~@’us Drain Current

and T&p~%$ure

-.-

-50 -25 0 25 50 75 100 125 150 175

TJ, JUNCTION TEMPERATURE ~C)

Figure 5. On-Resistance Variation with

Temperature

iD, DRAIN CURRENT (AMPS)

Figure 4. On-Resistance versus Drain Current

and Gate Voltage

100

‘O 5 10 15 20 25 30 35 40 45

vDs, DRAIN-TGSOURCE VOLTAGE (VOLTS)

Figure 6. Drain-To-Source Leakage

Current versus Voltage

Motorola TMOS Power MOSFET Transistor Device Data 3

MTD15N06VL

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.

The lengths of various switching intervals (At) are deter-

mined by how fast the FET input capacitance can be charged

by current from the generator.

The published capacitance data is difficult to use for calculat-

ing rise and fall because drain–gate capacitance varies

greatly with applied voltage. Accordingly, gate charge data is

used, In most cases, asatisfactory estimate of average input

current (IG(AV)) can be made from arudimental analysis of

the drive circuit so that

t=alG(Av)

During the rise and fall time interval when switching aresis-

tive load, VGS remains vitiually constant at alevel known as

the plateau voltage, VSGp. Therefore, rise and fall times may

be approximated by the following:

tr =Q2 xRG/(VGG –VGSP)

tf =Q2 xRGNGSP

where

VGG =the gate drive voltage, which varies from zero to VGG

RG =the gate drive resistance

and Q2 and VGSp are read from the gate charge curve.

During the turn–on and turn+ff delay times, gate current is

not constant. The simplest calculation uses appropriate val-

ues from the capacitance curves in astandard equation for

voltage change in an RC network. The equations are:

The capacitance (Ciss) is read from the capacitance curve at

avoltage corresponding to the off-state condition when cal-

culating td(on) and is read at avoltage corresponding to the

on–state when Calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source

lead, inside the package and in the circuit wiring whieg is

common to both the drain and gate current paths, prow-

voltage at the source which reduces the gate dti~ ‘Wwnt.

The voltage is determined by Ldi/dt, but sincedt~~~ha func-

tion of drain current, the mathematical sO~,u@;#ComPlex.

The MOSFET output capacitance alqQ,$$~t~flicates the

mathematics. And finally, MOSFETs+~V~~%lle internal gate

resistance which effectively adds to~’~~ resistance of the

driving source, but the internal, ~@~tance is difficult to mea-

sure and, consequently, is q,st~xtfled.

The resistive switchin~’~,@&,,$ariation versus gate resis-

tance (Figure 9) show~~~~fiical switching performance is

.,,.:,:,s+.

affected by the p~Qsit&:?:&lrcuit elements. If the parasitic

were not presen<~&$#lope of the cuwes would maintain a

>.>{[c:~~

value of uni~~~~@less of the switching speed. The circuit

used to o~@I,m;&&,$data is constructed to minimize common

inductani~~f$ the drain and gate circuit loops and is believed

rea~~achi&able with board mounted components. Most

p~~~ ~ctronic loads are inductive; the data in the figure is

,i~t~e~tiith aresistive load, which approximates an optimally

.+~!~$ti~bed inductive load. Power MOSFETS may be safely op-

“J’crated into an inductive load: however. snubbina reduces

td(on)=RG ciss In ~GG/(VGG –VGSP)] *}

,.!, *. switching losses.

4Motorola TMOS Power MOSFET Transistor Device Data

MTD15N06VL

10 \, I30

QT UC

9*/~27P

824 ~T

7VGS 21 ~

6\?

18 g

—Q2 /15 :

4\* ./ 12 g

3/\ , g=

2TJ =25°C -6!

1Q3 VDS ID=15A -3P

o5Od

10 15 20 25 30 35

Qg, TOTAL GATE CHARGE (nC) RG, GATE RE~~&i@HMS)

<.:i,’ ,...

Figure 8. Gat+To-Source and Drain-To-Source .*,\.\>.~.,~

Figure 9. Re)~tlv&:$witching Time

Voltage versus Total Charge Variatioq$~.p~,s Gate Resistance

,,,~,.$.

*f.>i*.&.

,.,,.,.,

s,u:,.<:~’

The Forward .~f~$ed~afe Operating Area curves define

the maximum ~~~$~’neous drain–to–source voltage and

drain curreq~h{:q transistor can handle safely when it is for-

ward bias’~<:~urves are based upon maximum peak junc-

tion t~~[abre and a case temperature (Tc) of 25°C. Peak

rep~tlvq: flulsed power limits are determined by using the

~~$M~Fresponse data in conjunction with the procedures

~~kd~,ussed in AN569, ‘Transient Thermal Resistancffieneral

~~~~hta and Its Use.”

‘V Switching between the off+tate and the on–state may tra-

verse any load line provided neither rated peak current (IDM)

nor rated voltage (VDSS) is exceeded and the transition time

(tr,tf) do not exceed 10 vs. In addition the total power aver-

aged over acomplete switching cycle must not exceed

(TJ(M~) -Tc)/(ReJc).

APower MOSFET designated E–FET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-

sipated in the transistor while in avalanche must be less than

the rated limit and adjusted for operating conditions differing

from those specified. Although industry practice is to rate in

terms of energy, avalanche energy capability is not a

constant. The energy rating decreases non–linearly with an

increase of peak current in avalanche and peak junction tem-

perature.

Although many E–FETs can withstand the stress of drain–

to–source avalanche at currents up to rated pulsed current

(IDM), the energy rating is specified at rated continuous cur-

rent (ID), in accordance with indust~ custom. The energy rat-

ing must be derated for temperature as shown in the

accompanying graph (Figure 12). Maximum energy at cur-

rents below rated continuous ID can safely be assumed to

equal the values indicated.

Motorola TMOS Power MOSFET Transistor Device Data 5

MTD15N06VL

SAFEOPERATING AREA

100

—=--—- RDS(On)LIMIT

— — THERMAL LIMIT

‘-— PACWGE LIMIT

0.1 II I I 11111 1 II

0.1 110 100

VDS, DRAIN-T&SOURCE VOLTAGE (VOLTS)

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

\i.\,.:*‘.:..*,~,::$

*,: ‘“ Figure 13. Thermal Response

...

TIME

Figure 14. Diode Reverse Recovery Waveform

—

6Motorola TMOS Power MOSFET Transistor Device Data

—

INFORMATION FOR USING THE DPAK SURFACE MOUNT

MTD15N06VL

PACWGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is acfitical portion of the total between the board and the package. With the correct pad

design. The footprint for the semiconductor packages must be geomet~, the packages will self align when subjected to a

the correct size to ensure proper solder connection interface solder reflow process.

.~,.,.*,,~

POWER DISSIPATION FOR &,~$~~ACE MOUNT DEVICE

The power dissipation for asurface mount device is q,, ,~%,,~

S‘?he surface mount packages. One isto increase the area of the

function of the drain pad size, These can vary from ~a~~t$ ‘s’ drain pad. By increasing the area of the drain pad, the power

minimum pad size for soldering to a pad size given f$~..,’”*

—maximum power dissipation. Power dissipation for ~su~ce

mount device is determined by TJ(m~), the m~ti~ rated

junction temperature of the die, R9JA, the ther~#~KgsRtance

from the device junction to ambient, a,~~~~~~perating

temperature, TA. Using the values provid-,t~e”data sheet,

PD can be calculated as follows: *(:~.

.,,.x\ ‘>~

,~3~,*.+-g\bkYp

.’. ‘;&?,y\},{\

‘!::+,..,1.

.,..,

The values for the ~~@~$ are found in the maximum

ratings table on the dah,s~et. Substituting these values into

the equation for ~+~pbi~~t temperature TA of 25°C, one can

calculate the p~~~+@sipation of the device. For aDPAK

device, PD ~k+yl~ted as follows.

.\.“$>)i:* .

.>,

‘board to achieve apower dissipation of 2.1 WaW. There are

other alternatives to achieving higher power dissipation from

dissipation can be increased. Although one can almost double

the power dissipation with this method, one will be giving up

area on the printed circuit board which can defeat the purpose

of using surface mount technology, For example, agraph of

HeJA versus drain pad area is shown in Figure 15,

z100

0Board MateHal =0.0625”

o11G-1 OFR4, 2oz Copper

~/1.75 Watts

g~60 ‘L /’ TA =25°C

fi~60 I

mm /3.0 Watis

Zo /

~An I I

L!“ ,

/5.0 Watts

3/I I

u20 II

o2 4 6610

A, AREA (SQUARE INCHES)

Figure 15. Thermal Resistance versus Drain Pad

Area for the DPAK Package @ypicai)

Motorola TMOS Power MOSFET Transistor Device Data 7

MTD15N06VL

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto aprinted

circuit board, solder paste must be applied to the pads. Solder

stencils are used to screen the optimum amount. These

stencils are typically 0,008 inches thick and may be made of

brass or stainless steel. For packages such as the SG59,

SC–70/SOT–323, SOD-1 23, SOT–23, SOT-1 43, SOT-223,

S&8, SO–1 4, SO–16, and SMB/SMC diode packages, the

stencil opening should be the same as the pad size or a1:1

registration. This is not the case with the DPAK and D2PAK

packages. If one uses a1:1 opening to screen solder onto the

drain pad, misalignment and/or ‘Yombstoning” may occur due

to an excess of solder. For these two packages, the opening

in the stencil for the paste should be approximately 50% of the

tab area, The opening for the leads is still a1:1 registration.

Figure 16 shows atypical stencil for the DPAK and D2PAK

packages. The pattern of the opening in the stencil for the

drain pad is nOt critical as long as it allOWS approximately 50%

of the pad to be covered with paste.

NN“

NN~ NSOLDERPASTE

OPENINGS

,%:?*V ,,,,i

,.:)$\\,:,

\’.:$ .,

<’tt..$~~

,;;$:4,

SOLDERING PRECAUTIONS ~*.t...

“.~j+~

~r,~ \~

The melting temperature of solder is higher than the rated .When shiftinq ~@tpreheating to soldering, the maximum

temperature of the device. When the entire device is heated temperatu:#~$&ent shall be 5°C or less.

to ahigh temperature, failure to complete soldering within a●After s~$;ti$fias been completed, the device should be

short time could result in device failure. Therefore, the allo~~e~~$o cool naturally for at least three minutes.

following items should always be observed in order to q~al coolingshould be used as the use of forced

minimize the thermal stress to which the devices are j$qllm will increase the temperature gradient and result

subjected. ~.~t,~n$atent failure due to mechanical stress.

●

Always preheat the device, .,,\.“.

“~~?)

‘$~.&~Mechanical stress or shock should not be applied during

The delta temperature be~een the preheat and soldering ‘“$ cooling.

should be 10O°C or less.* .:~<,:

... ..

When preheating and soldering, the temperaturq,,$$~e *Soldering adevice without preheating can cause excessive -

leads and the case must not exceed the -U’rn thermal shock and stress which can result in damage to the

temperature ratings as shown on the data #~~,.~hen device,

using infrared heating with the reflow sok$$~~tiethod,

the difference shall be a maximum of ~ti~$~~~~”’ ●Due to shadowing and the inability to set the wave height to

The soldering temperature and ti~e’~%{~ not exceed incorporate other surface mount components, the D2PAK is

not recommended for wave soldering;

●

8Motorola TMOS Power MOSFET Transistor Device Data

MTD15N06VL

TYPICALSOLDER

For any given circuit board, there will be a group of control

setiings that will give the desired heat pattern. The operator

must set temperatures for several heating zones, and a figure

for belt speed. Taken together, these control settings make up

aheating “profile” for that particular circuit board. On

machines controlled by acomputer, the computer remembers

these profiles from one operating session to the nefi. Figure

17 shows atypical heating profile for use when soldering a

surface mount device to aprinted circuit board. This profile will

vary among soldering systems but it is a good starting point.

Factors that can affect the profile include the type of soldering

system in use, density and types of components on the board,

type of solder used, andthetype of board or substrate material

being used. This profile shows temperature versus time. The

STEP1STEP2STEP3

PREHEAT VENT HEATING

ZONE1“SOAR ZONES2&5

,“RAMP “~Mp

II I

HEATING PROFILE

line on the graph shows the actual temperature that might be

experienced on the surface of atest board at or near acentral

solder joint. The ~o profiles are based on a high density and

alow density board. The Wtronics SMD31 OconvectionAn-

frared reflow soldering system was used to generate this

profile. The type of solder used was 6236/2 Tin Lead Silver

with amelting point between 177–189°C. When this type of

furnace is used for solder reflow work, the circuit ~rds and

solder joints tend to heat first. The components}: &~Yboard

are then heated by conduction. The circuit b$~r~~~cause it

has alarge surface area, absorbs the the~~$,~tiergy more

efficiently, then distributes this energ~~~$~i~~acomponents.

Because of this effect, the main bod~8~a@~ponent may be

up to 30 degrees cooler than the,l~#~$~t solder joints.

.. &\ .

,+.

,.s,. ~;]

,:~t.,.}.

,t~

.*, **?

ZON<S 3&!# ZONES 4&7

:j@AW ‘p” “SPIKP 205° TO 219°C

-PEAK AT

,,,,.,

2orc –-~:J}::4\$,,

DESIRED iURV; FOR HIGH .34. 170”C

~~ SOLDER JOINT

150°c

1500c – –

40 TO 80 SECONDS

(DEPENDING ON

loo”c – – MASS OF ASSEMBL~

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

,,<..

y~ ~‘TIME (3 TO 7MINUTES TOTAL) -TM~

Motorola TMOS Power MOSFET Transistor Device Data 9

PACWGE DIMENSIONS

NOTES

1, DIMENSIONING ANO TOLERANCING PER ANSI

Y14.5M, 1982,

2. ~NTROLLING OIMENSION INCH.

SME 2

PIN 1. GATE

2. OWIN

s0.020 P*J50,3 0.51 I1.27

uO.* I“Wl 0.51 I—

v.&8&- ‘---” ‘--” ‘‘--

2.. ‘k i

10 Motorola TMOS Power MOSFET Transistor Device Data

MTD15N06VL

NOTES

Motorola TMOS Power MOSFET Transistor Device Data 11

MTD15N06VL

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MOTOROLA oMTD15N06VUD