SUPPLY VOLTAGE (V)
SUPPLY CURRENT (nA)
800
700
600
500
400
300
200
100
0
123456
125°C
85°C
25°C
-40°C
VCM = VS ± 0.3V
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LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
LPV521 NanoPower, 1.8-V, RRIO, CMOS Input, Operational Amplifier
1 Features 3 Description
The LPV521 is a single nanopower 552-nW amplifier
1• For VS= 5 V, Typical Unless Otherwise Noted designed for ultra long life battery applications. The
– Supply Current at VCM = 0.3 V 400 nA (Max) operating voltage range of 1.6 V to 5.5 V coupled
– Operating Voltage Range 1.6 V to 5.5 V with typically 351 nA of supply current make it well
suited for RFID readers and remote sensor
– Low TCVOS 3.5 µV/°C (Max) nanopower applications. The device has input
– VOS 1 mV (Max) common mode voltage 0.1 V over the rails,
– Input Bias Current 40 fA guaranteed TCVOS and voltage swing to the rail
output performance. The LPV521 has a carefully
– PSRR 109 dB designed CMOS input stage that outperforms
– CMRR 102 dB competitors with typically 40 fA IBIAS currents. This
– Open-Loop Gain 132 dB low input current significantly reduces IBIAS and IOS
errors introduced in megohm resistance, high
– Gain Bandwidth Product 6.2 kHz impedance photodiode, and charge sense situations.
– Slew Rate 2.4 V/ms The LPV521 is a member of the PowerWise™ family
– Input Voltage Noise at f = 100 Hz 255 nV/√Hz and has an exceptional power-to-performance ratio.
– Temperature Range −40°C to 125°C The wide input common mode voltage range,
guaranteed 1 mV VOS and 3.5 µV/°C TCVOS enables
2 Applications accurate and stable measurement for both high-side
and low-side current sensing.
• Wireless Remote Sensors
• Powerline Monitoring EMI protection was designed into the device to
reduce sensitivity to unwanted RF signals from cell
• Power Meters phones or other RFID readers.
• Battery Powered Industrial Sensors The LPV521 is offered in the 5-pin SC70 package.
• Micropower Oxygen sensor and Gas Sensor
• Active RFID Readers Device Information(1)
• Zigbee Based Sensors for HVAC Control PART NUMBER PACKAGE BODY SIZE (NOM)
• Sensor Network Powered by Energy Scavenging LPV521 SC70 (5) 2.00 mm x 1.25 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Nanopower Supply Current
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Table of Contents
7.1 Overview................................................................. 19
1 Features.................................................................. 17.2 Functional Block Diagram....................................... 19
2 Applications ........................................................... 17.3 Feature Description................................................. 19
3 Description............................................................. 17.4 Device Functional Modes........................................ 19
4 Revision History..................................................... 28 Applications and Implementation ...................... 20
5 Pin Configuration and Functions......................... 38.1 Application Information............................................ 20
6 Specifications......................................................... 38.2 Typical Applications ................................................ 21
6.1 Absolute Maximum Ratings ...................................... 39 Power Supply Recommendations...................... 25
6.2 ESD Ratings.............................................................. 310 Layout................................................................... 26
6.3 Recommended Operating Conditions....................... 410.1 Layout Guidelines ................................................. 26
6.4 Thermal Information.................................................. 410.2 Layout Example .................................................... 26
6.5 1.8-V DC Electrical Characteristics........................... 411 Device and Documentation Support................. 27
6.6 1.8-V AC Electrical Characteristics........................... 511.1 Device Support .................................................... 27
6.7 3.3-V DC Electrical Characteristics........................... 611.2 Documentation Support ........................................ 27
6.8 3.3-V AC Electrical Characteristics........................... 711.3 Trademarks........................................................... 27
6.9 5-V DC Electrical Characteristics.............................. 711.4 Electrostatic Discharge Caution............................ 27
6.10 5-V AC Electrical Characteristics............................ 811.5 Glossary................................................................ 27
6.11 Typical Characteristics............................................ 912 Mechanical, Packaging, and Orderable
7 Detailed Description............................................ 19 Information........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (Feburary 2013) to Revision D Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes,Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5
4
1
3
2
+ -
OUT
V-
IN+
V+
IN-
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
5 Pin Configuration and Functions
SC70-5 Top View
Pin Functions
PIN TYPE DESCRIPTION
NO. NAME
1 OUT O Output
2 V- P Negative Power Supply
3 IN+ I Noninverting Input
4 IN- I Inverting Input
5 V+ P Positive Power Supply
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN MAX UNIT
Any pin relative to V-−0.3 6 V
IN+, IN-, OUT Pins V–– 0.3 V V++ 0.3 V V
V+, V-, OUT Pins 40 mA
Differential Input Voltage (VIN+ - VIN-) –300 300 mV
Junction Temperature(2) –40 150 °C
Mounting Temperature Infrared or Convection (30 sec.) 260 °C
Wave Soldering Lead Temp. (4 sec.) 260 °C
Storage temperature, Tstg −65 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.2 ESD Ratings VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
Charged-device model (CDM), per JEDEC specification JESD22- ±1000
V(ESD) Electrostatic discharge V
C101(2)
Machine Model ±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions(1)
MIN MAX UNIT
Temperature Range(2) −40 125 °C
Supply Voltage (VS= V+- V−) 1.6 5.5 V
(1) Absolute Maximum Ratings indicate limits beyond which damage may occur. Recommended Operating Conditions indicate conditions
for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test
conditions, see Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.4 Thermal Information DCK
THERMAL METRIC(1) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance (2) 456 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature
is PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
6.5 1.8-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA= 25°C, V+= 1.8 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOS Input Offset Voltage VCM = 0.3 V –1 0.1 1
Temperature extremes –1.23 1.23 mV
VCM = 1.5 V –1 0.1 1
Temperature extremes –1.23 1.23
TCVOS Input Offset Voltage Drift(2) ±0.4 μV/°C
Temperature extremes –3 3
IBIAS Input Bias Current –1 0.01 1 pA
Temperature extremes –50 50
IOS Input Offset Current 10 fA
CMRR Common Mode Rejection Ratio 0 V ≤VCM ≤1.8 V 66 92
Temperature extremes 60
0 V ≤VCM ≤0.7 V 75 101 dB
Temperature extremes 74
1.2 V ≤VCM ≤1.8 V 75 120
Temperature extremes 53
PSRR Power Supply Rejection Ratio 1.6 V ≤V+≤5.5 V dB
VCM = 0.3 V 85 109
Temperature extremes 76
CMRR ≥67 dB 0 V
CMRR ≥60 dB 0 1.8
CMVR Common Mode Voltage Range Temperature extremes 1.8
VO= 0.5 V to 1.3 V 125 dB
74
RL= 100 kΩto V+/2
AVOL Large Signal Voltage Gain Temperature extremes 73
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
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1.8-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits for TA= 25°C, V+= 1.8 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOOutput Swing High RL= 100 kΩto V+/2 2 50
VIN(diff) = 100 mV
Temperature extremes 50 mV from
either rail
Output Swing Low RL= 100 kΩto V+/2 2 50
VIN(diff) = −100 mV
Temperature extremes 50
IOSourcing, VOto V–3
1
VIN(diff) = 100 mV
Temperature extremes 0.5
Output Current(3) mA
Sinking, VOto V+3
1
VIN(diff) = −100 mV
Temperature extremes 0.5
ISSupply Current VCM = 0.3 V 345 400
Temperature extremes 580 nA
VCM = 1.5 V 472 600
Temperature extremes 850
(3) The short circuit test is a momentary open-loop test.
6.6 1.8-V AC Electrical Characteristics
Unless otherwise specified, all limits for TA= 25°C, V+= 1.8 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GBW Gain-Bandwidth Product CL= 20 pF, RL= 100 kΩ6.1 kHz
SR Slew Rate AV= +1, Falling Edge 2.9 V/ms
VIN = 0V to 1.8V Rising Edge 2.3
θmPhase Margin CL= 20 pF, RL= 100 kΩ72 deg
GmGain Margin CL= 20 pF, RL= 100 kΩ19 dB
enInput-Referred Voltage Noise Density f = 100 Hz 265 nV/√Hz
Input-Referred Voltage Noise 0.1 Hz to 10 Hz 24 μVPP
InInput-Referred Current Noise f = 100 Hz 100 fA/√Hz
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
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6.7 3.3-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOS Input Offset Voltage VCM = 0.3 V –1 0.1 1
Temperature extremes –1.23 1.23 mV
VCM = 3 V –1 0.1 1
Temperature extremes –1.23 1.23
TCVOS Input Offset Voltage Drift(2) ±0.4 μV/°C
Temperature extremes –3 3
IBIAS Input Bias Current –1 0.01 1 pA
Temperature extremes –50 50
IOS Input Offset Current 20 fA
CMRR Common Mode Rejection Ratio 0 V ≤VCM ≤3.3 V 72 97
Temperature extremes 70
0 V ≤VCM ≤2.2 V 78 106 dB
Temperature extremes 75
2.7 V ≤VCM ≤3.3 V 77 121
Temperature extremes 76
PSRR Power Supply Rejection Ratio 1.6 V ≤V+≤5.5 V 109
85
VCM = 0.3 V dB
Temperature extremes 76
CMRR ≥72 dB −0.1 3.4
CMRR ≥70 dB
CMVR Common Mode Voltage Range V
Temperature extremes 0 3.3
VO= 0.5 V to 2.8 V 120
82
RL= 100 kΩto V+/2
AVOL Large Signal Voltage Gain dB
Temperature extremes 76
VOOutput Swing High RL= 100 kΩto V+/2 3 50
VIN(diff) = 100 mV mV
Temperature extremes 50 from either
Output Swing Low RL= 100 kΩto V+/2 2 rail
50
VIN(diff) = −100 mV
Temperature extremes 50
IOOutput Current(3) Sourcing, VOto V–11
5
VIN(diff) = 100 mV
Temperature extremes 4 mA
Sinking, VOto V+12
5
VIN(diff) = −100 mV
Temperature extremes 4
ISSupply Current VCM = 0.3 V 346 400
Temperature extremes 600 nA
VCM = 3 V 471 600
Temperature extremes 860
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
(3) The short circuit test is a momentary open-loop test.
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
6.8 3.3-V AC Electrical Characteristics
Unless otherwise is specified, all limits for TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GBW Gain-Bandwidth Product CL= 20 pF, RL= 100 kΩ6.2 kHz
SR Slew Rate AV= +1, Falling Edge 2.9 V/ms
VIN = 0V to 3.3V Rising Edge 2.5
θmPhase Margin CL= 20 pF, RL= 10 kΩ73 deg
GmGain Margin CL= 20 pF, RL= 10 kΩ19 dB
enInput-Referred Voltage Noise Density f = 100 Hz 259 nV/√Hz
Input-Referred Voltage Noise 0.1 Hz to 10 Hz 22 μVPP
InInput-Referred Current Noise f = 100 Hz 100 fA/√Hz
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
6.9 5-V DC Electrical Characteristics
Unless otherwise specified, all limits for TA= 25°C, V+= 5 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOS Input Offset Voltage VCM = 0.3 V 0.1 ±1
Temperature extremes –1.23 1.23 mV
VCM = 4.7 V 0.1 ±1
Temperature extremes –1.23 1.23
TCVOS Input Offset Voltage Drift(2) ±0.4 μV/°C
Temperature extremes –3.5 3.5
IBIAS Input Bias Current 0.04 ±1 pA
Temperature extremes –50 50
IOS Input Offset Current 60 fA
CMRR Common Mode Rejection Ratio 0 V ≤VCM ≤5.0 V 75 102
Temperature extremes 74
0 V ≤VCM ≤3.9 V 84 108 dB
Temperature extremes 80
77 115
Temperature extremes 76
PSRR Power Supply Rejection Ratio 1.6 V ≤V+≤5.5 V 85 109
VCM = 0.3 V dB
Temperature extremes 76
CMVR Common Mode Voltage Range CMRR ≥75 dB −0.1 5.1
CMRR ≥74 dB V
Temperature extremes 0 5
AVOL Large Signal Voltage Gain VO= 0.5 V to 4.5 V 84 132 dB
RL= 100 kΩto V+/2
Temperature extremes 76
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) The offset voltage average drift is determined by dividing the change in VOS at the temperature extremes by the total temperature
change.
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5-V DC Electrical Characteristics (continued)
Unless otherwise specified, all limits for TA= 25°C, V+= 5 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOOutput Swing High RL= 100 kΩto V+/2 3 50
VIN(diff) = 100 mV
Temperature extremes 50 mV from
either rail
Output Swing Low RL= 100 kΩto V+/2 3 50
VIN (diff) = −100 mV
Temperature extremes 50
IOOutput Current Sourcing, VOto V−15 23
VIN(diff) = 100 mV
Temperature extremes 8 mA
Sinking, VOto V+15 22
VIN(diff) = −100 mV
Temperature extremes 8
ISSupply Current VCM = 0.3 V 351 400
Temperature extremes 620 nA
VCM = 4.7 V 475 600
Temperature extremes 870
6.10 5-V AC Electrical Characteristics(1)
Unless otherwise specified, all limits for TA= 25°C, V+= 5 V, V−= 0 V, VCM = VO= V+/2, and RL> 1 MΩ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(2) (3) (2)
GBW Gain-Bandwidth Product CL= 20 pF, RL= 100 kΩ6.2 kHz
SR Slew Rate AV= +1, Falling Edge 1.1 2.7
VIN = 0 V to 5 V Temperature 1.2
extremes V/ms
Rising Edge 1.1 2.4
Temperature 1.2
extremes
θmPhase Margin CL= 20 pF, RL= 100 kΩ73 deg
GmGain Margin CL= 20 pF, RL= 100 kΩ20 dB
enInput-Referred Voltage Noise Density f = 100 Hz 255 nV/√Hz
Input-Referred Voltage Noise 0.1 Hz to 10 Hz 22 μVPP
InInput-Referred Current Noise f = 100 Hz 100 fA/√Hz
EMIRR EMI Rejection Ratio, IN+ and IN−(4) VRF_PEAK = 100 mVP(−20 dBP), 121
f = 400 MHz
VRF_PEAK = 100 mVP(−20 dBP), 121
f = 900 MHz dB
VRF_PEAK = 100 mVP(−20 dBP), 124
f = 1800 MHz
VRF_PEAK = 100 mVP(−20 dBP), 142
f = 2400 MHz
(1) Electrical Characteristics values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the
device may be permanently degraded, either mechanically or electrically.
(2) All limits are guaranteed by testing, statistical analysis or design.
(3) Typical values represent the most likely parametric norm at the time of characterization. Actual typical values may vary over time and
will also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production
material.
(4) The EMI Rejection Ratio is defined as EMIRR = 20log (VRF_PEAK/ΔVOS).
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PERCENTAGE (%)
-3.0
TCVOS (PV/C)
30
25
20
15
10
5
0
VS= 3.3V
-40oC d TAd 125oC
VCM = VS/2
-2.0 -1.0 0.0 1.0 2.0 3.0
0
2
4
6
8
10
12
14
16
18
20
PERCENTAGE (%)
VS = 3.3V
TA = 25oC
VCM = VS/2
-1.0
VOS (mV)
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
0
5
10
15
20
25
PERCENTAGE (%)
VS = 1.8V
TA = 25oC
VCM = VS/2
-1.0
VOS (mV)
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
PERCENTAGE (%)
TCVOS (PV/C)
30
25
20
15
10
5
0
VS = 1.8V
-40oC = TA = 125oC
VCM = VS/2
-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (nA)
800
700
600
500
400
300
200
100
0
123456
125°C
85°C
25°C
-40°C VCM = 0.3V
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (nA)
800
700
600
500
400
300
200
100
0
123456
125°C
85°C
25°C
-40°C
VCM = VS ± 0.3V
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
6.11 Typical Characteristics
At TJ= 25°C, unless otherwise specified.
Figure 1. Supply Current vs. Supply Voltage Figure 2. Supply Current vs. Supply Voltage
Figure 3. Offset Voltage Distribution Figure 4. TcvOS Distribution
Figure 5. Offset Voltage Distribution Figure 6. TcvOS Distribution
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VCM (V)
VOS (éV)
150
100
50
0
-50
-100
-150
-0.50.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VS = 5V
125°C
85°C
25°C
-40°C
VS (V)
VOS (éV)
150
100
50
0
-50
-100
-150
123456
VCM = 0.3V
125°C
85°C
25°C
-40°C
VCM (V)
VOS (éV)
300
200
100
0
-100
-200
-300
0.0 0.3 0.6 0.9 1.2 1.5 1.8
VS = 1.8V
125°C 85°C
25°C -40°C
VCM (V)
VOS (éV)
150
100
50
0
-50
-100
-150
-0.1 0.4 0.9 1.4 1.9 2.4 2.9 3.4
VS = 3.3V
125°C
85°C
25°C
-40°C
PERCENTAGE (%)
TCVOS (PV/C)
30
25
20
15
10
5
0
VS = 5V
-40oC d TA d 125oC
VCM = VS/2
-3.0 -2.0 -1.0 0.0 1.0 2.0 3.0
-1.0
0
5
10
15
20
25
PERCENTAGE (%)
VOS (mV)
-0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0
VS = 5V
TA = 25oC
VCM = VS/2
LPV521
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Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 7. Offset Voltage Distribution Figure 8. TcvOS Distribution
Figure 9. Input Offset Voltage vs. Input Common Mode Figure 10. Input Offset Voltage vs. Input Common Mode
Figure 11. Input Offset Voltage vs. Input Common Mode Figure 12. Input Offset Voltage vs. Supply Voltage
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ISOURCE (mA)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 1.8V
125°C
85°C
25°C
-40°C
ISOURCE (mA)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 3.3V
125°C
85°C
25°C
-40°C
VOUT (V)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VS = 3.3V
125°C
85°C
25°C
-40°C
VOUT (V)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 1.0 2.0 3.0 4.0 5.0
VS = 5V
125°C
85°C
25°C
-40°C
VS (V)
VOS (éV)
150
100
50
0
-50
-100
-150
123456
VCM = VS - 0.3V
125°C
85°C
25°C -40°C
VOUT (V)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 1.8V
125°C
85°C
25°C
-40°C
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Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 13. Input Offset Voltage vs. Supply Voltage Figure 14. Input Offset Voltage vs. Output Voltage
Figure 15. Input Offset Voltage vs. Output Voltage Figure 16. Input Offset Voltage vs. Output Voltage
Figure 17. Input Offset Voltage vs. Sourcing Current Figure 18. Input Offset Voltage vs. Sourcing Current
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: LPV521
OUTPUT VOLTAGE REFERENCED TO V+ (V)
ISOURCE (mA)
5
4
3
2
1
0
0.0 0.5 1.0 1.5 2.0
VS = 1.8V
125°C
85°C
25°C
-40°C
OUTPUT VOLTAGE REFERENCED TO V- (V)
ISINK (mA)
5
4
3
2
1
0
0.0 0.5 1.0 1.5 2.0
VS = 1.8V
125°C
85°C
25°C
-40°C
ISOURCE (mA)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 3.3V
125°C
85°C
25°C
-40°C
ISOURCE (mA)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 5V
125°C
85°C
25°C
-40°C
ISOURCE (mA)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 5V
125°C
85°C
25°C
-40°C
ISOURCE (mA)
VOS (éV)
150
100
50
0
-50
-100
-150
0.0 0.5 1.0 1.5 2.0
VS = 1.8V
125°C
85°C
25°C
-40°C
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 19. Input Offset Voltage vs. Sourcing Current Figure 20. Input Offset Voltage vs. Sinking Current
Figure 21. Input Offset Voltage vs. Sinking Current Figure 22. Input Offset Voltage vs. Sinking Current
Figure 23. Sourcing Current vs. Output Voltage Figure 24. Sinking Current vs. Output Voltage
12 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: LPV521
VS (V)
ISOURCE (mA)
40
30
20
10
0123456
VCM = VS/2
125°C
85°C
25°C
-40°C
VS (V)
ISINK (mA)
40
30
20
10
0123456
VCM = VS/2
125°C
85°C
25°C
-40°C
OUTPUT VOLTAGE REFERENCED TO V+ (V)
ISOURCE (mA)
30
25
20
15
10
5
0012345
VS = 5V
125°C
85°C
25°C
-40°C
OUTPUT VOLTAGE REFERENCED TO V- (V)
ISINK (mA)
30
25
20
15
10
5
0012345
VS = 5V
125°C
85°C
25°C
-40°C
OUTPUT VOLTAGE REFERENCED TO V+ (V)
ISOURCE (mA)
16
12
8
4
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VS = 3.3V
125°C
85°C
25°C
-40°C
OUTPUT VOLTAGE REFERENCED TO V- (V)
ISINK (mA)
16
12
8
4
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
VS = 3.3V
125°C
85°C
25°C
-40°C
LPV521
www.ti.com
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 25. Sourcing Current vs. Output Voltage Figure 26. Sinking Current vs. Output Voltage
Figure 27. Sourcing Current vs. Output Voltage Figure 28. Sinking Current vs. Output Voltage
Figure 29. Sourcing Current vs. Supply Voltage Figure 30. Sinking Current vs. Supply Voltage
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LPV521
VCM (V)
IBIAS (fA)
50
40
30
20
10
0
-10
-20
-30
-40
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-40°C
25°C
VS = 3.3V
VCM (V)
IBIAS (pA)
15
10
5
0
-5
-10
-15
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
85°C
125°C
VS = 3.3V
VCM (V)
IBIAS (fA)
15
10
5
0
-5
-10
-15
0.0 0.5 1.0 1.5 2.0
-40°C
25°C
VS = 1.8V
VCM (V)
IBIAS (pA)
15
10
5
0
-5
-10
-15
0.0 0.5 1.0 1.5 2.0
85°C
125°C
VS = 1.8V
VS (V)
VOUT FROM RAIL (mV)
5
4
3
2
1
0
123456
RL = 100 k:
125°C
85°C
25°C
-40°C
VS (V)
VOUT FROM RAIL (mV)
5
4
3
2
123456
RL = 100 k:
125°C
85°C
25°C
-40°C
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 31. Output Swing High vs. Supply Voltage Figure 32. Output Swing Low vs. Supply Voltage
Figure 33. Input Bias Current vs. Common Mode Voltage Figure 34. Input Bias Current vs. Common Mode Voltage
Figure 35. Input Bias Current vs. Common Mode Voltage Figure 36. Input Bias Current vs. Common Mode Voltage
14 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: LPV521
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 1.8V
CL = 20 pF
RL = 1 M:
PHASE
GAIN
-40°C
125°C
25°C
85°C
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 3.3V
CL = 20 pF
RL = 1 M:
PHASE
GAIN
-40°C
125°C
25°C
85°C
FREQUENCY (Hz)
PSRR (dB)
100
80
60
40
20
0
VS = 1.8V, 3.3V, 5V
VS = 5V
VS = 3.3V
VS = 1.8V +PSRR
-PSRR
10 100 1k 10k 100k
FREQUENCY (Hz)
CMRR (dB)
100
90
80
70
60
50
40
1e1 1e2 1e3 1e4 1e5
10 100 1k 10k 100k
VS = 5V
VS = 1.8V
VS = 1.8V, 3.3V, 5V
VCM (V)
IBIAS (fA)
400
300
200
100
0
-100
-200
-300012345
-40°C
25°C
VS = 5V
VCM (V)
IBIAS (pA)
30
25
20
15
10
5
0
-5
-10
-15
-20012345
85°C
125°C
VS = 5V
LPV521
www.ti.com
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 37. Input Bias Current vs. Common Mode Voltage Figure 38. Input Bias Current vs. Common Mode Voltage
Figure 39. PSRR vs. Frequency Figure 40. CMRR vs. Frequency
Figure 41. Frequency Response vs. Temperature Figure 42. Frequency Response vs. Temperature
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PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 1.8V
RL = 10 M:
CL = 200 pF
PHASE
GAIN
CL = 20 pF
CL = 100 pF
CL = 50 pF
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 3.3V
RL = 10 M:
CL = 200 pF
PHASE
GAIN
CL = 20 pF
CL = 100 pF
CL = 50 pF
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 3.3V
CL = 20 pF
RL = 1 M:
PHASE
RL = 10 M:
RL = 10 k:
RL = 100 k:
60
40
20
0
-20
GAIN
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 5V
CL = 20 pF
RL = 1 M:
PHASE
GAIN
RL = 10 M:
RL = 10 k:
RL = 100 k:
60
40
20
0
-20
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 5V
CL = 20 pF
RL = 1 M:
PHASE
GAIN
-40°C
125°C
25°C
85°C
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 1.8V
CL = 20 pF
RL = 1 M:
PHASE
GAIN
RL = 10 M:
RL = 10 k:
RL = 100 k:
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 43. Frequency Response vs. Temperature Figure 44. Frequency Response vs. RL
Figure 45. Frequency Response vs. RLFigure 46. Frequency Response vs. RL
Figure 47. Frequency Response vs. CLFigure 48. Frequency Response vs. CL
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Product Folder Links: LPV521
1s/DIV
5 PV/DIV
15
10
5
0
-5
-10
-15
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
VS = 3.3V
VCM = VS/2
1s/DIV
5 PV/DIV
15
10
5
0
-5
-10
-15
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
VS = 5V
VCM = VS/2
FREQUENCY (Hz)
VOLTAGE NOISE (nV/íHz)
VS = 5V
110 100 1k 10k
100
1000
1s/DIV
5 PV/DIV
15
10
5
0
-5
-10
-15
-2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5
VS = 1.8V
VCM = VS/2
PHASE (°)
FREQUENCY (Hz)
GAIN (dB)
60
40
20
0
-20
130
110
90
70
50
30
10
-10
-30
100 1k 10k 100k
VS = 5V
RL = 10 M:
CL = 200 pF
PHASE
GAIN
CL = 20 pF
CL = 100 pF
CL = 50 pF
SUPPLY VOLTAGE (V)
SLEW RATE (V/ms)
3.3
3.0
2.7
2.4
2.1
1.8
1.5 2.3 3.1 3.9 4.7 5.5
FALLING EDGE
RISING EDGE
AV = +1
VOUT = VS
LPV521
www.ti.com
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 49. Frequency Response vs. CLFigure 50. Slew Rate vs. Supply Voltage
Figure 51. Voltage Noise vs. Frequency Figure 52. 0.1 to 10 Hz Time Domain Voltage Noise
Figure 53. 0.1 to 10 Hz Time Domain Voltage Noise Figure 54. 0.1 to 10 Hz Time Domain Voltage Noise
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
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FREQUENCY (MHz)
EMIRRV_PEAK (dB)
1.0e-1 1.0 1.0e1 1.0e2 1.0e3 1.0e4
0.1 1 10 100 1000 10000
170
150
130
110
90
70
50
30
10 VS = 5V
VPEAK = -20 dBVp
1V/DIV
2 ms/DIV
V+= +2.5V
V- = -2.5V
4
3
2
1
0
-1
-2
-3
-4
INPUT OUTPUT
VS = 5V
RL = 100 k:
500 mV/DIV
200 Ps/DIV
INPUT
OUTPUT
VS = 1.8V
RL = 100 k:
500 mV/DIV
200 Ps/DIV
OUTPUT
INPUT
VS = 5V
RL = 100 k:
50 mV/DIV
200 Ps/DIV
INPUT
OUTPUT
VS = 1.8V
RL = 100 k:
50 mV/DIV
200 Ps/DIV
INPUT
OUTPUT
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Typical Characteristics (continued)
At TJ= 25°C, unless otherwise specified.
Figure 55. Small Signal Pulse Response Figure 56. Small Signal Pulse Response
Figure 57. Large Signal Pulse Response Figure 58. Large Signal Pulse Response
Figure 59. Overload Recovery Waveform Figure 60. EMIRR vs. Frequency
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LPV521
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
7 Detailed Description
7.1 Overview
The LPV521 is fabricated with Texas Instruments' state-of-the-art VIP50 process. This proprietary process
dramatically improves the performance of Texas Instruments' low-power and low-voltage operational amplifiers.
The following sections showcase the advantages of the VIP50 process and highlight circuits which enable ultra-
low power consumption.
7.2 Functional Block Diagram
Figure 61. Block Diagram
7.3 Feature Description
The amplifier's differential inputs consist of a noninverting input (+IN) and an inverting input (–IN). The amplifier
amplifies only the difference in voltage between the two inputs, which is called the differential input voltage. The
output voltage of the op-amp Vout is given by Equation 1:
VOUT = AOL (IN+- IN-) (1)
where AOL is the open-loop gain of the amplifier, typically around 100 dB (100,000x, or 10uV per Volt).
7.4 Device Functional Modes
7.4.1 Input Stage
The LPV521 has a rail-to-rail input which provides more flexibility for the system designer. Rail-to-rail input is
achieved by using in parallel, one PMOS differential pair and one NMOS differential pair. When the common
mode input voltage (VCM) is near V+, the NMOS pair is on and the PMOS pair is off. When VCM is near V−, the
NMOS pair is off and the PMOS pair is on. When VCM is between V+ and V−, internal logic decides how much
current each differential pair will get. This special logic ensures stable and low distortion amplifier operation
within the entire common mode voltage range.
Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LPV521
becomes a function of VCM. VOS has a crossover point at 1.0 V below V+. Refer to the ’VOS vs. VCM’ curve in the
Typical Performance Characteristics section. Caution should be taken in situations where the input signal
amplitude is comparable to the VOS value and/or the design requires high accuracy. In these situations, it is
necessary for the input signal to avoid the crossover point. In addition, parameters such as PSRR and CMRR
which involve the input offset voltage will also be affected by changes in VCM across the differential pair transition
region.
7.4.2 Output Stage
The LPV521 output voltage swings 3 mV from rails at 3.3-V supply, which provides the maximum possible
dynamic range at the output. This is particularly important when operating on low supply voltages.
The LPV521 Maximum Output Voltage Swing defines the maximum swing possible under a particular output
load. The LPV521 output swings 50 mV from the rail at 5-V supply with an output load of 100 kΩ.
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LPV521
+
-
VIN
RISO
VOUT
CL
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
8 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LPV521is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.25 V). Many of the specifications apply
from –40°C to 125°C. The LMV521 features rail to rail input and rail-to-rail output swings while consuming only
nanowatts of power. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
8.1.1 Driving Capacitive Load
The LPV521 is internally compensated for stable unity gain operation, with a 6.2-kHz, typical gain bandwidth.
However, the unity gain follower is the most sensitive configuration to capacitive load. The combination of a
capacitive load placed at the output of an amplifier along with the amplifier’s output impedance creates a phase
lag, which reduces the phase margin of the amplifier. If the phase margin is significantly reduced, the response
will be under damped which causes peaking in the transfer and, when there is too much peaking, the op amp
might start oscillating.
Figure 62. Resistive Isolation of Capacitive Load
In order to drive heavy capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 62. By
using this isolation resistor, the capacitive load is isolated from the amplifier’s output. The larger the value of
RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback loop will be
stable, independent of the value of CL. However, larger values of RISO result in reduced output swing and
reduced output current drive.
Recommended minimum values for RISO are given in the following table, for 5-V supply. Figure 63 shows the
typical response obtained with the CL= 50 pF and RISO = 154 kΩ. The other values of RISO in the table were
chosen to achieve similar dampening at their respective capacitive loads. Notice that for the LPV521 with larger
CLa smaller RISO can be used for stability. However, for a given CLa larger RISO will provide a more damped
response. For capacitive loads of 20 pF and below no isolation resistor is needed.
CLRISO
0 – 20 pF not needed
50 pF 154 kΩ
100 pF 118 kΩ
500 pF 52.3 kΩ
1 nF 33.2 kΩ
5 nF 17.4 kΩ
10 nF 13.3 kΩ
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Product Folder Links: LPV521
10 M:
-
+VOUT
10 M:
10 M:
VIN
10 M:
10 M:
270 pF 270 pF
270 pF
CR2032 Coin Cell
225 mAh = 5 circuits @ 9.5 yrs.
60 Hz Twin T Notch Filter
AV = 2 V/V
10 M:
270 pF
VBATT
VBATT = 3V o2V @ end of life
Remote Sensor
Signal
+
60 Hz
To ADC
Signal × 2
(No 60 Hz)
20 mV/DIV
200 Ps/DIV
VOUT
VIN
VS = 5V
LPV521
www.ti.com
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Figure 63. Step Response
8.1.2 EMI Suppression
The near-ubiquity of cellular, Bluetooth, and Wi-Fi signals and the rapid rise of sensing systems incorporating
wireless radios make electromagnetic interference (EMI) an evermore important design consideration for
precision signal paths. Though RF signals lie outside the op amp band, RF carrier switching can modulate the
DC offset of the op amp. Also some common RF modulation schemes can induce down-converted components.
The added DC offset and the induced signals are amplified with the signal of interest and thus corrupt the
measurement. The LPV521 uses on chip filters to reject these unwanted RF signals at the inputs and power
supply pins; thereby preserving the integrity of the precision signal path.
Twisted pair cabling and the active front-end’s common-mode rejection provide immunity against low-frequency
noise (i.e. 60-Hz or 50-Hz mains) but are ineffective against RF interference. Even a few centimeters of PCB
trace and wiring for sensors located close to the amplifier can pick up significant 1 GHz RF. The integrated EMI
filters of the LPV521 reduce or eliminate external shielding and filtering requirements, thereby increasing system
robustness. A larger EMIRR means more rejection of the RF interference. For more information on EMIRR,
please refer to AN-1698.
8.2 Typical Applications
8.2.1 60-Hz Twin T-Notch Filter
Figure 64. 60-Hz Notch Filter
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Typical Applications (continued)
8.2.1.1 Design Requirements
Small signals from transducers in remote and distributed sensing applications commonly suffer strong 60-Hz
interference from AC power lines. The circuit of Figure 64 notches out the 60 Hz and provides a gain AV= 2 for
the sensor signal represented by a 1-kHz sine wave. Similar stages may be cascaded to remove 2nd and 3rd
harmonics of 60 Hz. Thanks to the nA power consumption of the LPV521, even 5 such circuits can run for 9.5
years from a small CR2032 lithium cell. These batteries have a nominal voltage of 3 V and an end of life voltage
of 2 V. With an operating voltage from 1.6 V to 5.5 V the LPV521 can function over this voltage range.
8.2.1.2 Detailed Design Procedure
The notch frequency is set by F0=1/2πRC. To achieve a 60-Hz notch use R = 10 MΩand C = 270 pF. If
eliminating 50-Hz noise, which is common in European systems, use R = 11.8 MΩand C = 270 pF.
The Twin T Notch Filter works by having two separate paths from VIN to the amplifier’s input. A low frequency
path through the resistors R - R and another separate high frequency path through the capacitors C - C.
However, at frequencies around the notch frequency, the two paths have opposing phase angles and the two
signals will tend to cancel at the amplifier’s input.
To ensure that the target center frequency is achieved and to maximize the notch depth (Q factor) the filter
needs to be as balanced as possible. To obtain circuit balance, while overcoming limitations of available
standard resistor and capacitor values, use passives in parallel to achieve the 2C and R/2 circuit requirements
for the filter components that connect to ground.
To make sure passive component values stay as expected clean board with alcohol, rinse with deionized water,
and air dry. Make sure board remains in a relatively low humidity environment to minimize moisture which may
increase the conductivity of board components. Also large resistors come with considerable parasitic stray
capacitance which effects can be reduced by cutting out the ground plane below components of concern.
Large resistors are used in the feedback network to minimize battery drain. When designing with large resistors,
resistor thermal noise, op amp current noise, as well as op amp voltage noise, must be considered in the noise
analysis of the circuit. The noise analysis for the circuit in Figure 64 can be done over a bandwidth of 5 kHz,
which takes the conservative approach of overestimating the bandwidth (LPV521 typical GBW/AVis lower). The
total noise at the output is approximately 800 µVpp, which is excellent considering the total consumption of the
circuit is only 540 nA. The dominant noise terms are op amp voltage noise (550 µVpp), current noise through the
feedback network (430 µVpp), and current noise through the notch filter network (280 µVpp). Thus the total
circuit's noise is below ½ LSB of a 10 bit system with a 2-V reference, which is 1 mV.
8.2.1.3 Application Curve
Figure 65. 60-Hz Notch Filter Waveform
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-
+VOUT
V
-
V+
100 M:
1 M:
RL
OXYGEN SENSOR
LPV521
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SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Typical Applications (continued)
8.2.2 Portable Gas Detection Sensor
Figure 66. Precision Oxygen Sensor
8.2.2.1 Design Requirements
Gas sensors are used in many different industrial and medical applications. They generate a current which is
proportional to the percentage of a particular gas sensed in an air sample. This current goes through a load
resistor and the resulting voltage drop is measured. The LPV521 makes an excellent choice for this application
as it only draws 345 nA of current and operates on supply voltages down to 1.6V. Depending on the sensed gas
and sensitivity of the sensor, the output current can be in the order of tens of microamperes to a few
milliamperes. Gas sensor datasheets often specify a recommended load resistor value or they suggest a range
of load resistors to choose from.
Oxygen sensors are used when air quality or oxygen delivered to a patient needs to be monitored. Fresh air
contains 20.9% oxygen. Air samples containing less than 18% oxygen are considered dangerous. This
application detects oxygen in air. Oxygen sensors are also used in industrial applications where the environment
must lack oxygen. An example is when food is vacuum packed. There are two main categories of oxygen
sensors, those which sense oxygen when it is abundantly present (i.e. in air or near an oxygen tank) and those
which detect traces of oxygen in ppm.
8.2.2.2 Detailed Design Procedure
Figure 66 shows a typical circuit used to amplify the output of an oxygen detector. The oxygen sensor outputs a
known current through the load resistor. This value changes with the amount of oxygen present in the air sample.
Oxygen sensors usually recommend a particular load resistor value or specify a range of acceptable values for
the load resistor. The use of the nanopower LPV521 means minimal power usage by the op amp and it
enhances the battery life. With the components shown in Figure 66 the circuit can consume less than 0.5 µA of
current ensuring that even batteries used in compact portable electronics, with low mAh charge ratings, could
last beyond the life of the oxygen sensor. The precision specifications of the LPV521, such as its very low offset
voltage, low TCVOS , low input bias current, high CMRR, and high PSRR are other factors which make the
LPV521 a great choice for this application.
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LPV521
+
-
10:
VOUT
-+
LOAD
Q1
2N2907
RSENSE
R1
24.9 k:
R2
24.9 k:
R3
10 M:
ICHARGE V+
V+
VOUT = X ICHARGE
RSENSE X R3
R1
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 10 20 30 40 50
VOUT (V)
VSENSOR (mV)
C001
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
Typical Applications (continued)
8.2.2.3 Application Curve
Figure 67. Calculated Oxygen Sensor Circuit Output (Single 5V Supply)
8.2.3 High-Side Battery Current Sensing
Figure 68. High-Side Current Sensing
8.2.3.1 Design Requirements
The rail-to-rail common mode input range and the very low quiescent current make the LPV521 ideal to use in
high-side and low-side battery current sensing applications. The high-side current sensing circuit in Figure 68 is
commonly used in a battery charger to monitor the charging current in order to prevent over charging. A sense
resistor RSENSE is connected in series with the battery.
8.2.3.2 Detailed Design Procedure
The theoretical output voltage of the circuit is VOUT =[®SENSE × R3)/R1] × ICHARGE. In reality, however, due to
the finite Current Gain, β, of the transistor the current that travels through R3will not be ICHARGE, but instead, will
be α× ICHARGE or β/( β+1) × ICHARGE. A Darlington pair can be used to increase the βand performance of the
measuring circuit.
Using the components shown in Figure 68 will result in VOUT ≈4000 Ω× ICHARGE. This is ideal to amplify a 1 mA
ICHARGE to near full scale of an ADC with VREF at 4.1 V. A resistor, R2 is used at the noninverting input of the
amplifier, with the same value as R1 to minimize offset voltage.
24 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: LPV521
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 0.25 0.5 0.75 1 1.25 1.5
VOUT (V)
ICHARGE (mA)
C001
LPV521
www.ti.com
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
Typical Applications (continued)
Selecting values per Figure 68 will limit the current traveling through the R1– Q1 – R3leg of the circuit to under 1
µA which is on the same order as the LPV521 supply current. Increasing resistors R1, R2, and R3will decrease
the measuring circuit supply current and extend battery life.
Decreasing RSENSE will minimize error due to resistor tolerance, however, this will also decrease VSENSE =
ICHARGE × RSENSE, and in turn the amplifier offset voltage will have a more significant contribution to the total error
of the circuit. With the components shown in Figure 68 the measurement circuit supply current can be kept below
1.5 µA and measure 100 µA to 1 mA.
8.2.3.3 Application Curve
Figure 69. Calculated High-Side Current Sense Circuit Output
9 Power Supply Recommendations
The LPV521 is specified for operation from 1.6 V to 5.5 V (±0.8 V to ±2.75 V) over a –40°C to 125°C
temperature range. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CAUTION
Supply voltages larger than 6 V can permanently damage the device.
Low bandwidth nanopower devices do not have good high frequency (>1KHz) AC PSRR rejection against high-
frequency switching supplies and other kHz and above noise sources, so extra supply filtering is recommended if
kHz range noise is expected on the power supply lines.
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LPV521
LPV521
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
www.ti.com
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply
applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques,SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular
as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Layout Example, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
10.2 Layout Example
Figure 70. Noninverting Layout Example
26 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated
Product Folder Links: LPV521
LPV521
www.ti.com
SNOSB14D –AUGUST 2009–REVISED DECEMBER 2014
11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LPV521 PSPICE Model, SNOM024
TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti
TI Filterpro Software, http://www.ti.com/tool/filterpro
DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm
TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm
Evaluation board for 5-pin, north-facing amplifiers in the SC70 package, SNOA487.
Manual for LMH730268 Evaluation board 551012922-001
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• Feedback Plots Define Op Amp AC Performance, SBOA015 (AB-028)
• Circuit Board Layout Techniques, SLOA089
• Op Amps for Everyone, SLOD006
• AN-1698 A Specification for EMI Hardened Operational Amplifiers, SNOA497
• EMI Rejection Ratio of Operational Amplifiers, SBOA128
• Capacitive Load Drive Solution using an Isolation Resistor, TIPD128
• Handbook of Operational Amplifier Applications, SBOA092
11.3 Trademarks
PowerWise is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2009–2014, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: LPV521
PACKAGE OPTION ADDENDUM
www.ti.com 3-Oct-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LPV521MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AHA
LPV521MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AHA
LPV521MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AHA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 3-Oct-2014
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LPV521MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LPV521MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LPV521MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Jul-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LPV521MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LPV521MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0
LPV521MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Jul-2016
Pack Materials-Page 2
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