7
· the number of clock cycles
inserted before REQ# is asserted
(1 to 65535)
· the number of clock cycles before
REQ# is de-asserted (1 to 2047)
· the number of address steps ( 2 to
6)
· how often the current transfer
attributes are used (repeat value 1
to 256)
· disconnect at n-th ADB (2 to 63)
Target latencies
The initial latencies can be
programmed with the completer
target behavior attributes. Depending
on the selected decode speed and
address phases, the test card
automatically adds the needed
number of wait states to achieve the
defined initial latency. A minimum of
one wait cycles is always added when
using decode speed B, C, minimum
two wait cycles are needed with
decode speed A.
In case the subsequent target access
is a 'read from target' and the most
recent event was a 'write to target',
'read from other target address',
'master write' or 'master read', the
minimum initial latency is 15 clock
cycles.
Data memory
The E2922B features a 1MB (128K x 2
dwords) programmable read/write
data memory. Master / requester and
target/ completer share the memory.
The address decoders can selectively
address it. The data memory can:
· store data from read/write
transfers
· be mapped to any PCI-X address
space
Data generator
Instead of using the data memory, the
on-board data generator can be used.
Without initial latencies, the
generator can generate a data
pattern, deterministically linked to
the data address. Combined with a
second exerciser card and the real-
time data compare feature, long-time
load stressing on any PCI-X to PCI-X
data path can be performed while
errors are detected in real-time
(figure 5).
The generator features the following
patterns:
· walking ones or zeros
· ground bounce
· count up (unique data)
· pseudo random pattern (unique
data)
The count up and pseudo random
pattern are unique up to the length of
1M quad words (4Mb). The data
uniqueness is derived out of the lower
bit 2 to 22 of the bus address.
Real-time data compare
Real-time data compare can be
performed either on:
· Memory:
when data is written to the
memory it is compared against the
actual memory content
· Data Generator :
based on the data address, the
generator calculates the expected
data and compares it with
incoming data.
C-API / PPR
The E2922B comes with a C-
Application Programming Interface
(C-API) which provides a
programming interface for setting up
and controlling the master target
card.
The test program must run on the
system-under-test itself. The PCI-X
interface itself is used to control the
card.
The library functions are divided into
groups, which allow you to set up and
control the various capabilities of the
Agilent E2922B.
Recommended development
environment: MS Visual C++ V. 6.0 or
higher.
Protocol Permutation and
Randomization (PPR)
The PPR library extends the C-API by
offering dedicated functions to setup
PCI-X protocol permutation in a
pseudo random sequence. It allows
easy to set up transfers of contiguous
blocks of data with as many protocol
variations as possible. Therefore, the
PPR software calculates which
variations are covered, and after how
many data transfers, by permutating
the possible protocol variations. It
determines whether the coverage,
within programmed constraints, can
be achieved under given test
circumstances, and calculates the test
time required to perform the data
transfers.
Generating permutations
By specifying lists of protocol
variations, which must occur, the
user-defined protocol constraints can
be easily set. For example, which
different burst lengths, wait cycles,
memory read/write commands, etc.
Then, PPR automatically moves
simultaneously through the lists. With
each step, that is, with each
permutation, the next value in this
list is combined with the next values
in the other lists. The hardware based
permutation proceeds in this way
until each value of each list is
combined with all values of the other
list, and thus all combinations are
covered. In this way, the repetition or
omission of combinations is avoided.
Documented test coverage
A printable report tells you to which
protocol variation the device has
exposed. It explicitly reports which
protocol attributes are permutated
against which other protocol
attributes, and after how many data
transfers.