1. General description
The 74LV14 is a low-voltage Si-g ate CMOS device that is pin and function comp atible with
74HC14 and 74HCT14.
The 74LV14 provides six inverting buffers with Schmitt-trigger input. It is capable of
transforming slowly-changing input signals into sharply defined, jitter-free output signals.
The input s switch at differ ent points fo r positive and negative-going si gnals. The difference
between the po sit ive vo ltage VT+ and the negative voltage VT is defined as the input
hysteresis voltage VH.
2. Features and benefits
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
Typical HIGH-level output vo ltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Applications
Wave and pulse shapers for highly noisy environments
Astable multivibrators
Monostable multivibrators
74LV14
Hex inverting Schmitt trigger
Rev. 6 — 12 December 2011 Product data sheet
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 2 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LV14N 40 Cto+125C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV14D 40 Cto+125C SO14 plastic small outline package; 14 leads;
body width 3.9 mm SOT108-1
74LV14DB 40 Cto+125C SSOP14 plastic shrink small outline package; 14 leads;
body width 5.3 mm SOT337-1
74LV14PW 40 Cto+125C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm SOT402-1
74LV14BQ 40 Cto+125C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 30.85 mm
SOT762-1
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram for one
Schmitt trigger
mna204
1A 1Y
12
2A 2Y
34
3A 3Y
56
4A 4Y
98
5A 5Y
11 10
6A 6Y
13 12
8
9
10
11
001aac497
12
13
2
1
4
3
6
5
mna025
AY
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 3 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It can not be
used as a supply pin or input.
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14
74LV14
1A VCC
1Y 6A
2A 6Y
2Y 5A
3A 5Y
3Y 4A
GND 4Y
001aah095
1
2
3
4
5
6
78
10
9
12
11
14
13
001aah096
74LV14
Transparent top view
VCC(1)
3Y 4A
3A 5Y
2Y 5A
2A 6Y
1Y 6A
GND
4Y
1A
VCC
6 9
5 10
4 11
3 12
2 13
7
8
1
14
terminal 1
index area
Table 2. Pin description
Symbol Pin Description
1A 1 data input
1Y 2 data output
2A 3 data input
2Y 4 data output
3A 5 data input
3Y 6 data output
GND 7 ground (0 V)
4Y 8 data output
4A 9 data input
5Y 10 data output
5A 11 data input
6Y 12 data output
6A 13 data input
VCC 14 supply voltage
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 4 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
7. Functional description
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Ptot derates linearly with 12 mW/K above 70 C.
[3] Ptot derates linearly with 8 mW/K above 70 C.
[4] Ptot derates linearly with 5.5 mW/K above 60 C.
[5] Ptot derates linearly with 4.5 mW/K above 60 C.
9. Recommended operating conditions
[1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
Table 3. Function table
H = HIGH voltage level; L = LOW voltage level.
Input nA Output nY
LH
HL
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5V [1] -20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V [1] -50 mA
IOoutput curren t VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - 50 mA
IGND ground current 50 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb = 40 C to +125 C
DIP14 package [2] - 750 mW
SO14 package [3] - 500 mW
(T)SSOP14 pack age [4] - 500 mW
DHVQFN14 package [5] - 500 mW
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage [1] 1.03.35.5V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 5 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
10. Static characteristics
[1] Typical values are measured at Tamb = 25 C.
Table 6. Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C
to +125 CUnit
Min Typ[1] Max Min Max
VOH HIGH-level output voltage VI= VT+ or VT
IO = 100 A; VCC = 1.2 V - 1.2 - - - V
IO = 100 A; VCC = 2.0 V 1.8 2.0 - 1.8 - V
IO = 100 A; VCC = 2.7 V 2.5 2.7 - 2.5 - V
IO = 100 A; VCC = 3.0 V 2.8 3.0 - 2.8 - V
IO = 100 A; VCC = 4.5 V 4.3 4.5 - 4.3 - V
IO = 6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V
IO = 12 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V
VOL LOW-level output voltage VI= VT+ or VT
IO = 100 A; VCC = 1.2 V - 0 - - - V
IO = 100 A; VCC = 2.0 V - 0 0.2 - 0.2 V
IO = 100 A; VCC = 2.7 V - 0 0.2 - 0.2 V
IO = 100 A; VCC = 3.0 V - 0 0.2 - 0.2 V
IO = 100 A; VCC = 4.5 V - 0 0.2 - 0.2 V
IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V
IO = 12 mA; VCC = 4.5 V - 0.35 0.5 5 - 0.65 V
IIinput leakage current VI=V
CC or GND;
VCC =5.5V - - 1.0 - 1.0 A
ICC supply current VI = VCC or GND; IO = 0 A;
VCC =5.5V - - 20.0 - 40 A
ICC additional supply current per input; VI = VCC 0.6 V;
VCC = 2.7 V to 3.6 V --500-850A
CIinput capacitance - 3.5 - - - pF
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 6 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
11. Dynamic characteristics
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
[3] Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz, fo= output frequency in MHz
CL= output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
(CLVCC2fo) = sum of the outputs.
12. Waveforms
Table 7. Dynam ic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter Conditions Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay nA to nY; see Figure 6 [2]
VCC = 1.2 V - 80 - - - ns
VCC = 2.0 V - 27 37 - 48 ns
VCC = 2.7 V - 20 28 - 35 ns
VCC = 3.0 V to 3.6 V; CL=15pF [3] -13- - -ns
VCC = 3.0 V to 3.6 V [3] - 15 22 - 28 ns
VCC = 4.5 V to 5.5 V - - 18 - 23 ns
CPD power dissipation
capacitance CL=50pF; f
i = 1 MHz;
VI=GNDtoV
CC
[4] -15- - -pF
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input (nA) to output (nY) propagat ion de la ys
mna344
t
PHL
t
PLH
V
M
V
M
V
M
V
M
nA input
nY output
GND
V
I
V
OH
V
OL
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 7 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
13. Transfer characteristics
Table 8. Measurement points
Supply voltage Input Output
VCC VMVM
< 2.7 V 0.5VCC 0.5VCC
2.7 V to 3.6 V 1.5 V 1.5 V
4.5 V 0.5VCC 0.5VCC
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
VCC
VIVO
001aaa663
DUT CL
50 pF
RTRL
1 kΩ
PULSE
GENERATOR
Table 9. Test data
Supply voltage Input
VCC VItr, tf
< 2.7 V VCC 2.5 ns
2.7 V to 3.6 V 2.7 V 2.5 ns
4.5 V VCC 2.5 ns
Table 10. Transfer characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 8 and Figure 9.
Symbol Parameter Conditions Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ[1] Max Min Max
VT+ positive-going
threshold vo ltage VCC = 1.2 V - 0.70 - - - V
VCC = 2.0 V 0.8 1.10 1.4 0.8 1.4 V
VCC = 2.7 V 1.0 1.45 2.0 1.0 2.0 V
VCC = 3.0 V 1.2 1.60 2.2 1.2 2.2 V
VCC = 3.6 V 1.5 1.95 2.4 1.5 2.4 V
VCC = 4.5 V 1.7 2.50 3.15 1.7 3.15 V
VCC = 5.5 V 2.1 3.00 3.85 2.1 3.85 V
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 8 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
[1] All typical values are measured at Tamb =25C.
14. Waveforms transfer characteristics
VTnegative-going
threshold vo ltage VCC = 1.2 V - 0.34 - - - V
VCC = 2.0 V 0.3 0.65 0.9 0.3 0.9 V
VCC = 2.7 V 0.4 0.90 1.4 0.4 1.4 V
VCC = 3.0 V 0.6 1.05 1.5 0.6 1.5 V
VCC = 3.6 V 0.8 1.30 1.8 0.8 1.8 V
VCC = 4.5 V 0.9 1.60 2.0 0.9 2.0 V
VCC = 5.5 V 1.1 2.00 2.6 1.1 2.6 V
VHhysteresis voltage VCC = 1.2 V - 0.3 - - - V
VCC = 2.0 V 0.2 0.55 0.8 0.2 0.8 V
VCC = 2.7 V 0.3 0.60 1.1 0.3 1.1 V
VCC = 3.0 V 0.4 0.65 1.2 0.4 1.2 V
VCC = 3.6 V 0.4 0.70 1.2 0.4 1.2 V
VCC = 4.5 V 0.4 0.80 1.4 0.4 1.4 V
VCC = 5.5 V 0.6 1.00 1.5 0.6 1.5 V
Table 10. Transfer characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); see Figure 8 and Figure 9.
Symbol Parameter Conditions Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ[1] Max Min Max
VT+ and VT limits at 70 % and 20 %.
Fig 8. Transfer characteristic Fig 9. Defin ition of VT+, VT and VH
mna207
VO
VI
VHVT+
VT−
mna208
V
O
V
I
V
H
V
T+
V
T−
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 9 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
VCC = 1.2 V. VCC = 2.0 V.
Fig 10. Typical 74LV14 transfer characteristics Fig 11. Typical 74LV14 transfer characteristics
VI (V)
0 1.20.90.3 0.6
001aaa659
4
8
12
ICC
(μA)
0
VI (V)
021.60.8 1.20.4
001aaa660
40
60
20
80
100
ICC
(μA)
0
VCC = 3.0 V.
Fig 12. Typical 74LV14 transfer characteristics
VI (V)
032.41.2 1.80.6
001aaa661
100
200
300
ICC
(μA)
0
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 10 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
15. Application information
The slow input rise and fall times cause additional power dissipation, this can be
calculated using the following formula:
Padd =f
i(trICC(AV) +t
fICC(AV))VCC where:
Padd = additional power dissipation (W);
fi= input frequency (MHz);
tr=rise time (ns); 10%to90%;
tf= fall time (ns); 90 % to 10 %;
ICC(AV) = average additional supply current (A).
Average ICC(AV) differs with positive or negative input transitions, as shown in Figure 13.
An example of a relaxation circuit using the 74LV14 is shown in Figure 14.
(1) Positive-going edge.
(2) Negative-going edge.
Fig 13. A verage additional supply current as a function of VCC
001aah097
VCC (V)
1.0 3.02.51.5 2.0
50
25
75
100
ΔICC(AV)
(μA)
0
(1)
(2)
Fig 14. Relaxation oscillator
mna035
R
C
f1
T
---1
0.8 RC
---------------------
=
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 11 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
16. Package outline
Fig 15. Package outline SOT27-1 (DIP14)
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 12 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
Fig 16. Package outline SOT108-1 (SO14)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 13 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
Fig 17. Package outline SOT337-1 (SSOP14)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
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Product data sheet Rev. 6 — 12 December 2011 14 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
Fig 18. Package outline SOT402 -1 (TSSOP14)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 15 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
Fig 19. Package outline SOT762-1 (DHVQFN14)
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 3.1
2.9
Dh
1.65
1.35
y1
2.6
2.4 1.15
0.85
e1
2
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT762-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT762-1
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
14 terminals; body 2.5 x 3 x 0.85 mm
A(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
26
13 9
8
7
1
14
X
D
E
C
BA
02-10-17
03-01-27
terminal 1
index area
AC
CB
vM
wM
E(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D(1)
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Product data sheet Rev. 6 — 12 December 2011 16 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
17. Abbreviations
18. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Dis charge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LV14 v.6 20111212 Product data sheet - 74LV14 v.5
Modifications: •Legal pages updated.
74LV14 v.5 20110105 Product data sheet - 74LV14 v.4
74LV14 v.4 20090702 Product data sheet - 74LV14 v.3
74LV14 v.3 20071220 Product data sheet - 74LV14 v.2
74LV14 v.2 19980420 Product specification - 74LV14 v.1
74LV14 v.1 19970203 Product specification - -
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Product data sheet Rev. 6 — 12 December 2011 17 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
19. Legal information
19.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the shor t data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suit able for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or cu stomer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by custo m er’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semicon ductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly object s to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulatio ns. Export might require a prior
authorization from competent authorities.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LV14 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 12 December 2011 18 of 19
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automo tive use. It is neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applicat ions, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
19.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
20. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LV14
Hex inverting Schmitt trigger
© NXP B.V. 2011. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 12 December 2011
Document identifier: 74LV14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
21. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
13 Transfer characteristics . . . . . . . . . . . . . . . . . . 7
14 Waveforms transfer characte ristics. . . . . . . . . 8
15 Application information. . . . . . . . . . . . . . . . . . 10
16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
17 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
18 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
19 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
19.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
19.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
19.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
20 Contact information. . . . . . . . . . . . . . . . . . . . . 18
21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
