Rev. 1.4 November 2010 www.aosmd.com Page 1 of 18
AOZ1242
EZBuck™ 3A Simple Buck Regulator
General Description
The AOZ1242 is a high efficiency, simple to use, 3A buck
regulator flexible enough to be optimized for a variety of
applications. The AOZ1242 works from a 4.5V to 32V
input voltage range, and provides up to 3A of continuous
output current on each buck regulator output. The output
voltage is adjustable down to 0.8V.
The AOZ1242 comes in an SO-8 or DFN-8 package and
is rated over a -40°C to +85°C ambient temperature
range
Features
●4.5V to 32V operating input voltage range
●70mΩ internal NFET, efficiency: up to 95%
●Internal soft start
●Output voltage adjustable down to 0.8V
●3A continuous output current
●Fixed 370kHz PWM operation
●Cycle-by-cycle current limit
●Short-circuit protection
●Thermal shutdown
●Small size, SO-8 or DFN-8 package
Applications
●Point of load DC/DC conversion
●Set top boxes
●DVD drives and HDD
●LCD monitors & TVs
●Cable modems
●Telecom/networking/datacom equipment
Typical Application
Figure 1. 3.3V/3A Buck Regulator
LX
VIN BS
VIN
VOUT
FB
GND
EN
VBIAS
COMP
C1
22µF
C7
C4
C2, C3
22µF x 2
R1
R2
R
C
C
C
L1
6.8µH
AOZ1242
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 2 of 18
Ordering Information
AOS Green Products use reduced levels of Halog ens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional info rmation.
Pin Configuration
Pin Description
Part Number Ambient Temperature Range Package Environmental
AOZ1242AI -40°C to +85°C SO-8 Green Product
AOZ1242DI -40°C to +85°C DFN-8 Green Product
VBIAS
VIN
EN
COMP
1
2
3
4
LX
BST
GND
FB
SO-8
(Top View)
DFN-8
(Top Thru View)
8
7
6
5
VBIAS
VIN
EN
COMP
1
2
3
4
LX
BST
GND
FB
8
7
6
5
VIN
GND
Pin Number Pin Name Pin Function
1 LX PWM output connection to inductor. LX pin needs to be connected externally. Thermal connection
for output stage.
2 BST Bootstrap voltage input. High side driver supply. Connected to 0.1µF capacitor between BST and
LX.
3 GND Ground.
4 FB Feedback input. It is regulated to 0.8V. The FB pin is used to determine the PWM output voltage
via a resistor divider between the output and GND.
5 COMP External loop compensation. Output of internal error amplifier. Connect a series RC network to
GND for control loop compensation.
6 EN Enable pin. The enable pin is active HIGH. Connect EN pin to VIN if not used. Do not leave the EN
pin floating.
7V
IN Supply voltage input. Range from 4.5V to 32V. When VIN rises above the UVLO threshold the
device starts up. All VIN pins need to be connected externally.
8 VBIAS Compensation pin of internal linear regulator. Place a 1µF capacitor between this pin and ground.
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 3 of 18
Block Diagram
Absolute Maximum Ratings
Exceeding the Absolute Maximum Ratings may damage the device.
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
Recommended Operating Conditions
The device is not guaranteed to operate beyond the
Recommended Operating Conditions.
Note:
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA =
25°C. The value in any given application depends on the user's spe-
cific board design.
370kHz
/
24kHz
Oscillator
GND
VIN
EN
VBIAS
FB
COMP
LX
BST
OTP
ILimit
PWM
Control
Logic
5V LDO
Regulator
UVLO
& POR
+5V
GM = 200µA
/
V
Softstart
Reference
& Bias
0.8V
Q1
Q2
PWM
Comp
ISen
EAmp
0.2V
+
–
+
–
+
–
+
–
+
Frequency
Foldback
Comparator
Parameter Rating
Supply Voltage (VIN) 34V
LX to GND -0.7V to VIN+0.3V
EN to GND -0.3V to VIN+0.3V
FB to GND -0.3V to 6V
COMP to GND -0.3V to 6V
BST to GND VLX+6V
VBIAS to GND -0.3V to 6V
Junction Temperature (TJ) +150°C
Storage Temperature (TS) -65°C to +150°C
ESD Rating(1) 2kV
Parameter Rating
Supply Voltage (VIN) 4.5V to 32V
Output Voltage Range 0.8V to VIN
Ambient Temperature (TA) -40°C to +85°C
Package Thermal Resistance (ΘJA)(2)
SO-8
DFN-8
105°C/W
53°C/W
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 4 of 18
Electrical Characteristics
TA = 25°C, VIN = VEN = 12V, unless otherwise specified(3)
Note:
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
Symbol Parameter Conditions Min. Typ. Max. Units
VIN Supply Voltage 4.5 32 V
VUVLO Input Under-Voltage Lockout Threshold VIN Rising
VIN Falling
4.3
4.1 V
IIN Supply Current (Quiescent) IOUT = 0, VFB = 1.2V, VEN > 2V 23mA
IOFF Shutdown Supply Current VEN = 0V 320µA
VFB Feedback Voltage 0.782 0.8 0.818 V
Load Regulation 0.5 %
Line Regulation 0.08 % / V
IFB Feedback Voltage Input Current 200 nA
ENABLE
VEN EN Input Threshold Off Threshold
On Threshold 2.5
0.6 V
VHYS EN Input Hysteresis 200 mV
MODULATOR
fOFrequency 315 370 425 kHz
DMAX Maximum Duty Cycle 85 %
DMIN Minimum Duty Cycle 6%
GVEA Error Amplifier Voltage Gain 500 V / V
GEA Error Amplifier Transconductance 200 µA / V
PROTECTION
ILIM Current Limit 3.5 5.5 A
Over-Temperature Shutdown Limit TJ Rising
TJ Falling
145
100 °C
fSC Short Circuit Hiccup Frequency VFB = 0V 24 kHz
tSS Soft Start Interval 4ms
PWM OUTPUT STAGE
RDS(ON) High-Side Switch On-Resistance 70 100 mΩ
High-Side Switch Leakage VEN = 0V, VLX = 0V 10 µA
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 5 of 18
Typical Performance Characteristics
Circuit of Figure 1. TA = 25°C, VIN = VEN = 24V, VOUT = 3.3V unless otherwise specified.
Light Load (DCM) Operation Full Load (CCM) Operation
Startup to Full Load Short Circuit Protection
50% to 100% Load Transient Short Circuit Recovery
1μs/div 1μs/div
2ms/div 200μs/div
200
μ
s/div 2ms/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
Vo
2V/div
lin
0.5A/div
Vo Ripple
200mV/div
lo
1A/div
Vo
2V/div
lL
2A/div
Vo
2V/div
IL
2A/div
IL
1A/div
VLX
20V/div
Vin ripple
0.1V/div
Vo ripple
20mV/div
IL
1A/div
VLX
20V/div
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 6 of 18
Efficiency Curves
Efficiency
V
IN
= 5V
75
80
85
90
95
1.8V OUTPUT
5.0V OUTPUT
5.0V OUTPUT
3.3V OUTPUT
3.3V OUTPUT
8.0V OUTPUT
8.0V OUTPUT
3.3V OUTPUT
100
0 0.5 1.0 1.5 2.0 2.5 3.0
Current (A)
0 0.5 1.0 1.5 2.0 2.5 3.0
Current (A)
Efficieny (%)
Efficiency
V
IN
= 12V
75
80
85
90
95
100
Efficieny (%)
Efficiency
V
IN
= 24V
75
80
85
90
95
100
Efficieny (%)
0 0.5 1.0 1.5 2.0 2.5 3.0
Current (A)
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 7 of 18
Detailed Description
The AOZ1242 is a current-mode step down regulator with
integrated high side NMOS switch. It operates from a 4.5V
to 32V input voltage range and supplies up to 3A of load
current. The duty cycle can be adjusted from 6% to 85%
allowing a wide range of output voltage. Features include
enable control, Power-On Reset, input under voltage
lockout, fixed internal soft-start and thermal shut down.
The AOZ1242 is available in SO-8 or DFN-8 package.
Enable and Soft Start
The AOZ1242 has internal soft start feature to limit
in-rush current and ensure the output voltage ramps up
smoothly to regulation voltage. A soft start process
begins when the input voltage rises to 4.1V and voltage
on EN pin is HIGH. In soft start process, the output
voltage is ramped to regulation voltage in typically 6.8ms.
The 6.8ms soft start time is set internally.
Connect the EN pin to VIN if enable function is not used.
Pull it to ground will disable the AOZ1242. Do not leave it
open. The voltage on EN pin must be above 2.5 V to
enable the AOZ1242. When voltage on EN pin falls
below 0.6V, the AOZ1242 is disabled. If an application
circuit requires the AOZ1242 to be disabled, an open
drain or open collector circuit should be used to interface
to EN pin.
Steady-State Operation
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
The AOZ1242 integrates an internal N-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Since the N-MOSFET requires a
gate voltage higher than the input voltage, a boost
capacitor connected between LX pin and BST pin drives
the gate. The boost capacitor is charged while LX is low.
An internal 10Ω switch from LX to GND is used to insure
that LX is pulled to GND even in the light load. Output
voltage is divided down by the external voltage divider at
the FB pin. The difference of the FB pin voltage and
reference is amplified by the internal transconductance
error amplifier. The error voltage, which shows on the
COMP pin, is compared against the current signal, which
is sum of inductor current signal and ramp compensation
signal, at PWM comparator input. If the current signal is
less than the error voltage, the internal high-side switch
is on. The inductor current flows from the input through
the inductor to the output. When the current signal
exceeds the error voltage, the high-side switch is off. The
inductor current is freewheeling through the Schottky
diode to output.
Switching Frequency
The AOZ1242 switching frequency is fixed and set by an
internal oscillator. The switching frequency is set 370khz.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin with a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R2 with equation below.
Some standard values for R1 and R2 for the most
commonly used output voltages are listed in Table 1.
Table 1.
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
Protection Features
The AOZ1242 has multiple protection features to prevent
system circuit damage under abnormal conditions.
Over Current Protection (OCP)
The sensed inductor current signal is also used for
over current protection. Since the AOZ1242 employs
peak current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0.4V and 2.5V internally.
The peak inductor current is automatically limited
cycle-by-cycle.
The cycle-by-cycle current limit threshold is internally
set. When the load current reaches the current limit
threshold, the cycle by cycle current limit circuit turns
off the high side switch immediately to terminate the
current duty cycle. The inductor current stop rising.
The cycle-by-cycle current limit protection directly limits
inductor peak current. The average inductor current is
also limited due to the limitation on peak inductor current.
VO (V) R1 (kΩ) R2 (kΩ)
0.8 1.0 Open
1.2 4.99 10
1.5 10 11.5
1.8 12.7 10.2
2.5 21.5 10
3.3 31.6 10
5.0 52.3 10
VO0.8 1 R1
R2
-------
+
⎝⎠
⎜⎟
⎛⎞
×=
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 8 of 18
When cycle by cycle current limit circuit is triggered, the
output voltage drops as the duty cycle decreasing.
The AOZ1242 has internal short circuit protection to pro-
tect itself from catastrophic failure under output short cir-
cuit conditions. The FB pin voltage is proportional to the
output voltage. Whenever FB pin voltage is below 0.2V,
the short circuit protection circuit is triggered. To prevent
current limit running away, when comp pin voltage is
higher than 2.1 V, the short circuit protection is also trig-
gered. As a result, the converter is shut down and hic-
cups at a frequency equals to 1/16 of normal switching
frequency. The converter will start up via a soft start once
the short circuit condition disappears. In short circuit pro-
tection mode, the inductor average current is greatly
reduced because of the low hiccup frequency.
Power-On Reset (POR)
A power-on reset circuit monitors the input voltage.
When the input voltage exceeds 4.3V, the converter
starts operation. When input voltage falls below 4.1V,
the converter will stop switching.
Thermal Protection
An internal temperature sensor monitors the junction
temperature. It shuts down the internal control circuit and
high side NMOS if the junction temperature exceeds
145°C. The regulator will restart automatically under the
control of soft-start circuit when the junction temperature
decreases to 100°C.
Application Information
The basic AOZ1242 application circuit is shown in
Figure 1. Component selection is explained below.
Input Capacitor
The input capacitor (C1 in Figure 1) must be connected
to the VIN pin and GND pin of the AOZ1242 to maintain
steady input voltage and filter out the pulsing input
current. The voltage rating of input capacitor must be
greater than maximum input voltage plus ripple voltage.
The input ripple voltage can be approximated by equa-
tion below:
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
if let m equal the conversion ratio:
The relationship between the input capacitor RMS
current and voltage conversion ratio is calculated and
shown in Figure 2. It can be seen that when VO is half of
VIN, CIN is under the worst current stress. The worst
current stress on CIN is 0.5 x IO.
Figure 2. ICIN vs. Voltage Conversion Ratio
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high ripple current rating. Depending on the
application circuits, other low ESR tantalum capacitor
or aluminum electrolytic capacitor may also be used.
When selecting ceramic capacitors, X5R or X7R type
dielectric ceramic capacitors are preferred for their better
temperature and voltage characteristics. Note that the
ripple current rating from capacitor manufactures is
based on certain amount of life time. Further de-rating
may be necessary for practical design requirement.
Inductor
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is,
The peak inductor current is:
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
ΔVIN
IO
fC
IN
×
----------------- 1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
VO
VIN
---------
××=
ICIN_RMS IO
VO
VIN
---------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
VO
VIN
---------m=
0
0.1
0.2
0.3
0.4
0.5
0 0.5 1
m
ICIN_RMS(m)
IO
ΔIL
VO
fL×
-----------1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
×=
ILpeak IO
ΔIL
2
--------
+=
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 9 of 18
reduces RMS current through inductor and switches,
which results in less conduction loss.
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor needs to be checked for
thermal and efficiency requirements.
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise, but they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be consid-
ered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck con-
verter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
where;
CO is output capacitor value and
ESRCO is the Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switch-
ing frequency dominates. Output ripple is mainly caused
by capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric
type of ceramic, or other low ESR tantalum capacitor
or aluminum electrolytic capacitor may also be used as
output capacitors.
In a buck converter, output capacitor current is continuous.
The RMS current of output capacitor is decided by
the peak to peak inductor ripple current. It can be
calculated by:
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Schottky Diode Selection
The external freewheeling diode supplies the current to
the inductor when the high side NMOS switch is off. To
reduce the losses due to the forward voltage drop and
recovery of diode, Schottky diode is recommended to
use. The maximum reverse voltage rating of the chosen
Schottky diode should be greater than the maximum
input voltage, and the current rating should be greater
than the maximum load current.
Loop Compensation
The AOZ1242 employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
where;
CO is the output filter capacitor,
RL is load resistor value, and
ESRCO is the equivalent series resistance of output capacitor.
ΔVOΔILESRCO
1
8fC
O
××
-------------------------
+
⎝⎠
⎛⎞
×=
ΔVOΔIL
1
8fC
O
××
-------------------------
×=
ΔVOΔILESRCO
×=
ICO_RMS
ΔIL
12
----------
=
fp1
1
2πCORL
××
-----------------------------------
=
fZ1
1
2πCOESRCO
××
------------------------------------------------
=
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 10 of 18
The compensation design is actually to shape the
converter close loop transfer function to get desired gain
and phase. Several different types of compensation
network can be used for AOZ1242. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a stable
high-bandwidth control loop.
In the AOZ1242, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
where;
GEA is the error amplifier transconductance, which is 200 x 10-6
A/V,
GVEA is the error amplifier voltage, and
CC is the compensation capacitor
The zero given by the external compensation network,
capacitor CC (C5 in Figure 1) and resistor RC (R1 in
Figure 1), is located at:
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover frequency is also called the converter
bandwidth. Generally a higher bandwidth means faster
response to load transient. However, the bandwidth
should not be too high due to system stability concern.
When designing the compensation loop, converter stabil-
ity under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
less than 1/10 of switching frequency. It is recommended
to choose a crossover frequency less than 30kHz.
The strategy for choosing RC and CC is to set the cross
over frequency with RC and set the compensator zero
with CC. Using selected crossover frequency, fC, to
calculate RC:
where;
fC is desired crossover frequency,
VFB is 0.8V,
GEA is the error amplifier transconductance, which is 200x10-6
A/V, and
GCS is the current sense circuit transconductance, which is
5.64 A/V
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected
crossover frequency. CC can is selected by:
The equation above can also be simplified to:
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
Thermal Management and Layout
Consideration
In the AOZ1242 buck regulator circuit, high pulsing cur-
rent flows through two circuit loops. The first loop starts
from the input capacitors, to the VIN pin, to the LX pins, to
the filter inductor, to the output capacitor and load, and
then return to the input capacitor through ground. Current
flows in the first loop when the high side switch is on. The
second loop starts from inductor, to the output capacitors
and load, to the GND pin of the AOZ1242, to the LX pins
of the AZO1242. Current flows in the second loop when
the low side diode is on.
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is recommended to connect input capacitor, output
capacitor, and GND pin of the AOZ1242.
In the AOZ1242 buck regulator circuit, the three major
power dissipating components are the AOZ1242, exter-
nal diode and output inductor. The total power dissipation
of converter circuit can be measured by input power
minus output power.
The power dissipation of inductor can be approximately
calculated by output current and DCR of the inductor.
fp2
GEA
2πCCGVEA
××
-------------------------------------------
=
fZ2
1
2πCCRC
××
-----------------------------------
=
fC30kHz=
RCfC
VO
VFB
---------- 2πCO
×
GEA GCS
×
------------------------------
××=
CC
1.5
2πRCfp1
××
-----------------------------------
=
CC
CORL
×
RC
---------------------
=
Ptotal_loss VIN IIN VOIO
×–×=
Pinductor_loss IO2Rinductor 1.1××=
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 11 of 18
The power dissipation of the diode is:
The actual AOZ1242 junction temperature can be
calculated with power dissipation in the AOZ1242 and
thermal impedance from junction to ambient.
The maximum junction temperature of AOZ1242 is
145°C, which limits the maximum load current capability.
The thermal performance of the AOZ1242 is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC
will operate under the recommended environmental
conditions.
Several layout tips are listed below for the best electric
and thermal performance. Figure 3a and Figure 3b give
the example of layout for AOZ1242A and AOZ1242D
respectively.
1. Do not use thermal relief connection to the VIN and
the GND pin. Pour a maximized copper area to the
GND pin and the VIN pin to help thermal dissipation.
2. Input capacitor should be connected to the VIN pin
and the GND pin as close as possible.
3. Make the current trace from LX pins to L to Co to the
GND as short as possible.
4. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
5. Keep sensitive signal trace such as trace connected
with FB pin and COMP pin far away form the LX pins.
Pdiode_loss IOVF1VO
VIN
---------
–
⎝⎠
⎜⎟
⎛⎞
××=
Tjunction Ptotal_loss Pinductor_loss
–()Θ×JA
=
Tambient
++
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 12 of 18
Figure 3a. Layout Example for AOZ1242AI
Figure 3b. Layout Example for AOZ1242DI
R2
C4
Cb
C1
R1
Vin
1LX
BST
2
GND
FB
4
8VBIAS
5
6
COMP
EN 3
7Vin
GND
L1 Vo
C2 C
2
Rc
Cc
R1 R2
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 13 of 18
Package Dimensions, SO-8
Notes:
1. All dimensions are in millimeters.
2. Dimensions are inclusive of plating
3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 6 mils.
4. Dimension L is measured in gauge plane.
5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Dimensions in millimeters
Min.
1.35
0.10
1.25
0.31
0.17
4.80
3.80
5.80
0.25
0.40
0°
D
C
L
h x 45°
7° (4x)
b
2.20
5.74
0.80
Unit: mm
1.27
A1
A2 A
0.1
θ
Gauge Plane Seating Plane
0.25
e
8
1
E1E
Nom.
1.65
—
1.50
—
—
4.90
3.90
1.27 BSC
6.00
—
—
—
Max.
1.75
0.25
1.65
0.51
0.25
5.00
4.00
6.20
0.50
1.27
8°
Symbols
A
A1
A2
b
c
D
E1
e
E
h
L
θ
Dimensions in inches
Min.
0.053
0.004
0.049
0.012
0.007
0.189
0.150
0.228
0.010
0.016
0°
Nom.
0.065
—
0.059
—
—
0.193
0.154
0.050 BSC
0.236
—
—
—
Max.
0.069
0.010
0.065
0.020
0.010
0.197
0.157
0.244
0.020
0.050
8°
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 14 of 18
Tape and Reel Dimensions, SO-8
SO-8 Carrier Tape
SO-8 Reel
SO-8 Tape
Leader/Trailer
& Orientation
Tape Size
12mm
Reel Size
ø330
M
ø330.00
±0.50
Package
SO-8
(12mm)
A0
6.40
±0.10
B0
5.20
±0.10
K0
2.10
±0.10
D0
1.60
±0.10
D1
1.50
±0.10
E
12.00
±0.10
E1
1.75
±0.10
E2
5.50
±0.10
P0
8.00
±0.10
P1
4.00
±0.10
P2
2.00
±0.10
T
0.25
±0.10
N
ø97.00
±0.10
K0
Unit: mm
B0
G
M
W1
S
K
H
N
W
V
R
Trailer Tape
300mm min. or
75 empty pockets
Components Tape
Orientation in Pocket
Leader Tape
500mm min. or
125 empty pockets
A0
P1
P2
See Note 5
See Note 3
See Note 3
Feeding Direction
P0
E2
E1
E
D0
T
D1
W
13.00
±0.30
W1
17.40
±1.00
H
ø13.00
+0.50/-0.20
K
10.60
S
2.00
±0.50
G
—
R
—
V
—
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 15 of 18
Package Dimensions, 5x4A DFN-8
Notes:
1. Dimensions and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters.
3. The location of the terminal #1 identifier and terminal numbering convention conforms to JEDEC publication 95 SP-002.
4. Dimension b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. If the terminal has the
optional radius on the other end of the terminal, the dimension b should not be measured in that radius area.
5. Coplanarity applies to the terminals and all other bottom surface metallization.
6. Drawing shown are for illustration only.
7. The dimensions with * are just for reference
8. Pin #3 and Pin #7 are fused to DAP.
Symbols
A
A3
b
D
D2
D3
E
E2
e
L
L1
L2
L3
R
aaa
bbb
ccc
ddd
eee
Dimensions in millimeters
RECOMMENDED LAND PATTERN
FRONT VIEW
TOP VIEW
BOTTOM VIEW
BOTTOM VIEW
Min.
0.70
0.40
4.90
2.05
1.66
3.90
2.23
0.50
—
Nom.
0.75
0.20 Ref.
0.45
5.00
2.15
1.76
4.00
2.33
0.95 BSC
0.55
0.40
0.285 Ref.
0.835 Ref.
0.30 Ref.
0.15
0.10
0.10
0.08
0.05
Max.
0.80
0.50
5.10
2.25
1.86
4.10
2.43
0.60
—
Symbols
A
A3
b
D
D2
D3
E
E2
e
L
L1
L2
L3
R
aaa
bbb
ccc
ddd
eee
Min.
0.028
0.016
0.190
0.080
0.064
0.154
0.088
0.020
—
Nom.
0.30
0.008 Ref.
0.018
0.200
0.085
0.070
0.157
0.092
0.037 BSC
0.022
0.016
0.011 Ref.
0.033 Ref.
0.012 Ref.
0.006
0.004
0.004
0.003
0.002
Max.
0.032
0.020
0.201
0.089
0.074
0.161
0.096
0.024
—
4.51
0.285
2.33
1.165
0.285
1.86
0.40
2.25
0.50 Typ.
0.95 Typ.
0.65
4.20
Dimensions in inches
b
A
A3
Seating
Plane
D/2
E/2
D
E
L
L2*
L3*
E2
L2*
D3
L1
e
D2 Chamfer 0.30
Pin #1 IDA
Option 1
Index Area
(D/2 x E/2)
Pin #1 IDA
Option 2
R
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 16 of 18
Tape and Reel Dimensions, 5x4A DFN-8
R0.40
P0
K0 A0
E
E2 D0
E1
D1
B0
Package
DFN 5x4
(12 mm)
A0 B0 K0 E E1 E2D0 D1 P0 P1 P2 T
5.30
±0.10 ±0.10
4.30
±0.10
1.20 Min.
1.50 1.50 12.00
±0.10
1.75
±0.10
5.50
±0.10
8.00
±0.20
4.00
±0.10
2.00
±0.05
0.30
UNIT: mm
T
Typ.
0.20
Feeding
Direction
Tape
Leader/Trailer and Orientation
±0.30
+0.10 / –0
Trailer Tape
300mm Min.
Components Tape
Orientation in Pocket
Leader Tape
500mm Min.
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 17 of 18
Reel
VIEW: C
C
0.05 3-1.8
ø96±0.2
6.45±0.05
3-ø2.9±0.05
3-ø1/8"
3-ø1/4"
8.9±0.1
11.90
14 REF
1.8
5.0
12 REF
41.5 REF
43.00
44.5±0.1
2.00
6.50
10.0
10.71
10°
3-ø3/16"
R48 REF
ø86.0±0.1
2.20
6.2
ø13.00
ø21.20
ø17.0
R1.10
R3.10
2.00
3.3
4.0
6.10
0.80
3.00
8.00
+0.05
0.00
R0.5
1.80
2.5
38°
44.5±0.1
46.0±0.1
8.0±0.1
40°
6°
3-ø3/16"
R3.95
6.50
ø90.00
6.0
1.8
1.8
R1
8.00 0.00
-0.05
N=ø100±2
A
A
A
R121
R127
R159
R6
R55
P
B
W1
M
II I
I
6.0±1
R1
Zoom In
III
Zoom In
II
Zoom In
A
Tape Size
12mm
Reel Size
ø330
M
ø330
+0.3
-4.0
W1
12.40
+2.0
-0.0
B
2.40
±0.3
P
0.5
AOZ1242
Rev. 1.4 November 2010 www.aosmd.com Page 18 of 18
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
LEGAL DISCLAIMER
Alpha and Omega Semiconductor makes no representations or warranties with respect to the accuracy or
completeness of the information provided herein and takes no liabilities for the consequences of use of such
information or any product described herein. Alpha and Omega Semiconductor reserves the right to make
changes to such information at any time without further notice. This document does not constitute the grant of any
intellectual property rights or representation of non-infringement of any third-party’s intellectual property rights.
Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations,
and limitations.
LIFE SUPPORT POLICY
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
Part Marking
AOZ1242AI
AOZ1242DI
Z1242AI
FAY Part Numbe
r
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
WLT
Z1242DI
FAY Part Number
Assembly Lot Code
Fab & Assembly Location
Year & Week Code
WLT
