80523PY350512PE - Intel - Datasheet.Directory

Pentium® II Processor at 350 MHz,

400 MHz, and 450 MHz

Datasheet

Pr oduct Features

The I ntel P entium ® II process or is designed for high-per formance de sktops and for workstat ions

and servers. It is binary compa tible with previou s Intel Archit ecture process ors. The Pentium II

processor prov ides the best perfor mance availa ble for applicat ions running on advan ce d

operating systems such as W indows * 95, Wind ows NT and UNIX*. This is achi eved by

integ rat ing the be st a ttr ibute s of I nte l p roces sors —the d ynamic e xecut ion, Dual Inde pendent Bu s

architecture plus Int el MMX™ te chnology—bringing a new level of perf ormance for systems

buyers . T he Pentium II proces sor is scaleable to two proc es sors in a multiprocessor syst em and

extends the power of today’s P entium II processor with performance headroom for business

media, commun ication and inte rnet ca pabilities . Syste ms based on Pentium II processors also

include the latest features to simplify syste m management and lower the cost of owners hip for

large and sma ll busine ss environments. T he Pentium II proc essor offers great performance for

today’s and tomorrow’s applic ations.

•Available at 350 MHz, 400 MHz, and

450 MHz frequencies

•Syste m bus freq uenc y at 100 MHz

•Binary compatible with applications

running on previous member s of the Intel

microprocessor line

•Dynamic execution micro arch itecture

•Dual Independent Bus architecture:

Separate dedicated external S ystem Bus

and dedicate d internal high-s peed cache

bus

•Power Management ca pabilities

—System Management mode

—Multiple low-power states

•Optimized for 32-bit applications running

on advanced 32-bit opera ting systems

•Si ngle Edge Contact Cartridge (S.E.C.C.)

and S.E .C.C.2 packaging tec hnology; the

S.E.C. cartridge s deli ver high performance

with improv ed ha ndling protection and

socketability

•I ntegrated high per f ormance 16 KB

instruction and 16 KB data, nonb locking,

l evel one cache

•Available with integrated 512 KB unif ied,

nonblocking, level two cache

•Enabl es syst em s which are scale abl e up to

two processors

•Error-correcting code for System Bus data

Or d er N um be r : 24 36 57-00 3

August 1998

Datasheet

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual

property ri

hts is

ranted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relatin

to sale and/or use of Intel products includin

liability or warranties relatin

fitness for a particular purpose, merchantability, or infrin

ement of any patent, copyri

ht or other intellec tual property ri

ht. Intel products are not

intended for use in medical, life savin

, or life sustainin

applications.

Intel may make chan

es to specifications and product descriptions at any time, without notice.

Desi

ners must not rely on the absence or characteristics of any features or instructions marked “reserved“ or “undefined.“ Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or imcompatibilities arisin

from future chan

es to them .

The Pentium® II processor may contain desi

n defects or errors known as errata which may cause the product to deviate from published

specifcations. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placin

your product order.

Copies of documents which have an orderin

number and are referenced in this document, or other Intel literature, may be obtained by callin

1-800-

548-4725 or by visitin

Intel's website at http://www.intel.com.

Copyri

ht © Intel Corporation 1998.

*Third-party brands and names are the property of their respective owners.

Datasheet 3

Pentium

Processor at 350 MHz, 400 MHz, and 450 MHz

Contents

1.0 Introduction.........................................................................................................................7

1.1 Terminology...........................................................................................................8

1.1.1 S.E.C. Cartridge Terminology ..................................................................8

1.2 References............................................................................................................9

2.0 Ele ctrical Spec ificati o ns...... ....... ............ ............ ........... ............ ............ ....... ............ .........10

2.1 Processo r System Bus and V REF ......................................................................10

2.2 Clock Control and Low Power Sta tes..................................................................11

2.2.1 Normal State—State 1 ...........................................................................12

2.2.2 AutoHAL T Powerdown State—State 2 ...................................................12

2.2.3 Stop-G rant State—Sta te 3 .....................................................................12

2.2.4 HALT/Grant Snoop State— State 4 ........................................................13

2.2.5 Sleep Sta te—S tate 5. . ............................................................................13

2.2.6 Deep Sleep State—S tate 6....................................................................13

2.2.7 Clock Contro l..........................................................................................14

2.3 Power and Ground Pins ......................................................................................14

2.4 Decoupl ing Guidelin es ........................................................................................14

2.4.1 Processo r VCCCORE Decoupling............................................................15

2.4.2 Processo r System Bus AGTL+ Decouplin g............................................15

2.5 Processo r System Bus Clock and Processor C locking.......................................15

2.5.1 Mixing Processors of Different Frequencies...........................................15

2.6 Voltage Identification...........................................................................................15

2.7 Processor System Bus Unused Pins...................................................................17

2.8 Processo r System Bus S ignal Groups ................................................................17

2.8.1 Async hronous vs. Synchronous for System Bus Signals.......................19

2.8.2 System Bus Freque ncy Select Sig nal (100/66#)....................................19

2.9 Test Access Port (TAP) Connection................ ....... .......... ....... ....... ....... ....... .......20

2.10 Maximum Ratings................................................................................................20

2.11 Processor DC Sp ecifi catio ns...............................................................................21

2.12 AGTL+ System Bus Specifications .....................................................................24

2.13 System Bus AC Specifications............................................................................25

3.0 System Bus Signal Simulations........................................................................................36

3.1 System Bus Clock (BCLK) Signal Quali ty Specifications and Measurement

Guidelines ...........................................................................................................37

3.2 AGT L+ Signal Qua lity Specificat ions and Mea suremen t Gui delines ..................38

3.3 Non-AGT L+ S ignal Quality Speci fications and M easurem ent Gu idelines...........40

3.3.1 Overshoot/Undershoot Guidelines .................................................. .......41

3.3.2 Ringba ck Sp e cificati o n......... ............ ............ ....... ............ ............ ...........41

3.3.3 Settling Limit Guideline...........................................................................42

4.0 Thermal Specifications and Design Consid erations.........................................................42

4.1 Thermal Specification s........ ............ ....... ............ ............ ........... ............ ............ ..43

4.1.1 Therm a l Diode... ....... ............ ............ ............ ............ ....... ............ ...........44

5.0 S.E.C.C. and S.E.C.C .2 Mechanical Spec ifications........................................................44

5.1 S.E.C.C. Mechn ical Specifications......................................................................45

Pentium

Proces sor at 350 MHz, 400 MHz, and 450 MHz

4 Datasheet

5.2 S.E.C.C.2 Mechanical Specification............................................. ................... ....52

5.3 Processor Package Materials Information ..........................................................57

5.4 Pentium® II Processor Signal Listing ..................................................................58

6. 0 Box ed Pro ce sso r Sp e cificati o n s........ ........... ........ ........... ............ ............ ............ ............ .64

6.1 Introduction .........................................................................................................64

6.2 Mechanical Specifications...................................................................................66

6.2.1 Boxed Processor Fan Heatsink Dimensi ons..........................................66

6.2.2 Boxed Processor Fan Heatsink Weight..................................................69

6.2.3 Boxed Processor Retention Mechanism and Fan Heatsink Sup ports .. ..69

6. 3 Box ed Pro ce sso r Requ i r e men ts .......... ............ ............ ............ ........... ........ ........7 2

6.3.1 Fan Heatsink Power Supply...................................................................72

6.4 Thermal Specifications........................................................................................73

6.4.1 Boxed Processor Cooling Requirements ...............................................73

7.0 Pentium® II Processor Signal Description........................................................................74

7.1 Alphabetical Signa ls Reference . .........................................................................74

7.2 Signal Summari es...............................................................................................81

Figures 1 Seco nd Level (L2) Cache Implementations .........................................................8

2 AG TL+ Bus Topology..........................................................................................11

3 Stop Clock State M achine...................................................................................11

4 100/66# Pin Example..........................................................................................20

5 BCL K to Co re Log ic O ffset..................................................................................33

6 BCL K, PICCLK, and TCK Generic Clock Waveform...........................................34

7 System Bus Valid Delay Timings ........................................................................34

8 System Bus Setup and Hold Timings..................................................................34

9 System Bus Reset and Configuration Timings....................................................35

10 Power-On Reset and Configuration Timings.......................................................35

11 Test Timings (TAP Connection)..........................................................................36

12 Test Reset Tim ings.............................................................................................36

13 BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins ......37

14 BCLK, TCK, PICCLK Generic Clock Wave form at the Processor Edge

Fingers................................................................................................................38

15 Low to High AGT L+ Receiver Ringba ck Tolerance .............................................40

16 Non-AGTL+ Overshoot/Undershoot, Settling Limi t, and Ringback .....................40

17 Pentium® II Processor S.E.C.C. - Side View .......................................................42

18 Pentium® I I Processor (S.E.C.C. Package)— Top and Side View.......................45

19 Pentium® I I Processor (S.E.C.C. Package)—Extende d Thermal Plate Side

Dimensions .........................................................................................................46

20 Pentium® II Processor (S .E.C.C. Package)—Bottom View Dimensions.............46

21 Pentium® II Processor (S.E.C.C. Package)—Latch Arm, Extended Thermal

Plate Lug, and Cover Lug Dimensions.................... ....... ....... ....... ..... ....... ....... ....47

22 Pentium® II Processor (S.E.C.C. Package)—Latch Arm, Extended Thermal

Plate, and Cover Deta il Dimensions (Reference Dimensions Only) ............... ....48

23 Pentium® II Processor (S.E.C.C. Package)—Extended Thermal Plate

Attachment Detail Dim ensions............................................................................49

Datasheet 5

Pentium

Processor at 350 MHz, 400 MHz, and 450 MHz

24 Pentium® I I Proc esso r (S.E.C.C. Package)—Exten ded Thermal Plat e

Attachment Detail Dimensions, Continue d..........................................................50

25 Pentium® I I P roc essor Subst rate (S.E.C.C. Package)—E dge Fin ger

Contact Dimensions............................................................................................50

26 Pentium® I I P roc essor Subst rate (S.E.C.C. Package)—E dge Fin ger

Contact Dimensions, Detail A..............................................................................51

27 Pentium® I I Proc esso r Markings (S.E .C.C. Pack age).........................................51

28 Pentium® I I Proc esso r (S.E.C.C.2 Pa ckag e) Top and Side Views—

OLGA Pro ce sso r Cor e ............. ............ ........... ............ ............ ....... ............ .........52

29 Pentium® I I Proces sor (S.E.C.C.2 Pa ckag e) Top and Side Views—

PLGA Processor Core.........................................................................................53

30 Pentium® II Processor Assembly (S.E.C.C.2 Package)—Prim ary View .............53

31 Pentium® I I Processo r Assembly (S.E.C.C.2 Packag e)—Cover V iew with

Dimensions..........................................................................................................54

32 Pentium® II Process or Assembly (S.E.C.C.2 Package)—Heat Sink Attach

Boss Section ......... ............ ........... ........ ........... ............ ............ ............ ............ ....54

33 Pentium® II Processor Assem bly (S.E.C.C. 2 Package), Side View—

OLGA Sub str a te Sho w n........ ............ ............ ............ ............ ....... ............ ...........55

34 Detail View of Cover in the Vicinity of the Substrate Attach Features.................55

35 Pentium® II Processor Substr ate (S. E.C.C.2 Package), Edge Finger Contact

Dimensions..........................................................................................................56

36 Pentium® I I Proc esso r Markings (S.E .C.C.2 Package).......................................56

37 Boxed Pe ntium ® II Processor in the S. E.C.C. Pac kaging I nstalled in Retention

Mechanism (Fan Power Cable Not Shown).......................................................65

38 Boxed Pe ntium® II Processor in the S.E.C.C.2 Packaging (Fan Power Cable

Not Shown).........................................................................................................65

39 Side View Space Requirements for t he B oxed Processor with S.E.C.C.

Packaging............................................................................................................66

40 Front View Space Requirements for the Boxed Processor with S.E.C.C.

Packaging............................................................................................................67

41 Side View Space Requirement s for the Boxed Processor with S.E.C.C.2

Packaging............................................................................................................67

42 Front View Space Requirements for the Boxed Processor with S.E.C.C.2

Packaging............................................................................................................68

43 To p View Air Space Req uirements for the Bo xed Processor..............................68

44 Heatsink Support Hole Locations and Size.........................................................70

45 Side View Space Requirement s for Boxed Processo r Fan Heatsink Supports ...71

46 Top View Space Requirements for Box ed Processor Fan Heatsink Supports ...71

47 Boxed Processor Fan Heats ink Power Cable Connect or Description.................72

48 Recomm ended M otherb oard Power Header Placement Relative to Fan Power

Connector and Pentium ® II Processor ................................................................73

Tables 1 Voltage Identification Definition...........................................................................16

2 Recommended Pull-up Resistor Values (Approximate) for CMOS Signals. ..... ..18

3 S ystem Bus Signal Grou ps .................................................................................19

4 Absolute Maximum Rati ngs.................................................................................21

5 V oltage and Current Specifications ....................................................................22

6 A GT L+ Signal Groups DC Specifications . . .........................................................24

Pentium

Proces sor at 350 MHz, 400 MHz, and 450 MHz

6 Datasheet

7 N on-AGTL + Signal Group DC Specifications......................................................24

8 AGTL+ Bus Sp ecifications .................................................................................25

9 Syst em Bus AC Specifications (Clock) at the Processor Edge Fingers .............26

10 System Bus AC Specifications (Clock) at Processo r Core Pins ........................27

11 Valid System Bus, Core Frequency, and Cache B us Frequencies ....................27

12 System Bus AC Spec ifications (AGTL+ S ignal Group)at the Process or

Edge Fi n g er s ............... ............ ............ ............ ............ ....... ............ ............ ........28

13 System Bus AC Specificat ions (AGTL+ Signal Group) at the Processor

Core Pi ns .... ............ ....... ............ ............ ........... ............ ............ ....... ............ ......28

14 System Bus AC Spec ifications (CMOS Signal Grou p) at the Processor

Edge Fingers 29

15 System Bus AC Specifications (CMOS Signal Grou p)at the Processor Core

Pins 29

16 System Bus AC Specifications (Reset Conditions) . ...........................................30

17 System Bus AC Specifications (APIC Clock and APIC I/O) at the Process or

Edge Fi n g er s.. ............ ............ ............ ............ ........... ........ ........... ............ ...........30

18 System Bus AC Specifications (APIC Clock and APIC I/O)at the Processor

Core Pi ns .... ............ ....... ............ ............ ........... ............ ............ ....... ............ ......31

19 System Bus AC Spec ifications (TAP Connection)at the Proc esso r Edge

Fingers ...............................................................................................................31

20 System Bus AC Specifications (TAP Connection)at the Processor Core Pins ..32

21 BCLK Signal Quality Specifications for Simulation at the Processor Core ........37

22 BCLK Signal Quality Guide lines for Edge Finger Measurem ent ........................38

23 AGTL+ Sign al Groups Ringb ack Tolerance Sp ecificatio ns at the Processor

Core ...................................................................................................................39

24 AGTL+ Signal Groups Ringb ack Tolerance Guid elines for Edge Finger

Measurement .....................................................................................................39

25 Signal Ringback Specifications for Non-AGT L+ Signal Sim ulation at the

Processor Core ..................................................................................................41

26 Signal Ringback Guidelines for Non-AGTL + Signal E dge Finger Measurem ent 41

27 Thermal Specifications for S.E.C.C. Packaged Proces sors ...............................43

28 Thermal Specifications for S.E.C.C.2 Packaged Processors... .... ....... .......... ......43

29 Thermal Diode Parameters.................................................................................44

30 Thermal Diode Interface......................................................................................44

31 Description Table for Processor Markings (S.E.C.C. Packaged Processor).......52

32 Description Table for Processor Markings (S.E.C.C.2 Packaged Processor).....57

33 S.E.C.C. Mater ials ....... ............ ....... ............ ............ ............ ............ ............ ....... .57

34 S.E.C.C.2 Mate r ials ..... ............ ....... ............ ............ ............ ............ ............ ....... .57

35 Signal Listing in Order by Pin Number................................................................58

36 Signal Listing in Order by Signal Name ..............................................................61

37 Bo xed Processor Fan Heatsink Spatial Dimensions...........................................69

38 Boxed Processor Fan Heatsink Support Dimensions .................. ....... ..... ....... ....70

39 Fan Heatsink Power and Signal Spe cifications...................................................72

40 Motherboard F an Power Con nector Location .....................................................73

41 Signal Description ...............................................................................................74

42 O u tp u t Signals.............. ............ ............ ............ ....... ............ ............ ............ ........81

43 Input Signals .......................................................................................................82

44 Input/Output Sig nals (Single Driver) ....................................................................83

45 Input/Output Sig nals (Multiple D river).................................................................83

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 7

1.0 Introduction

The Pent ium II 350 MHz/400 MHz/ 450 MHz processor is the next in the Pentiu m II proces sor line

of Intel processors. The Pentium II proce ssor, l ike the Pentium Pro processor, implem ents a

Dynamic E xecution micro arc hitecture—a unique combination of mult iple branch pre diction, data

flow analysis, and speculative execution. This enables these processors to deliver higher

per f ormance than the Pentium processor, while maintaini ng b inary compa tibility with all previous

Intel Arch itecture proc essors . Th e Pen tium II processor also executes MMX technolog y

inst ructions for enhanced media and co mmunication p erformance . The Pentium II processor

utilizes multiple low-power states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to

conserve power during idle ti mes.

The Pent ium II proces sor utilizes the same multiprocessing sys tem bus technology as th e Pentium

Pro proces sor. This allows for a higher level of performance for both uni-processor and two-way

multipro ce ssor (2-way MP) syste ms. Memory is ca che able for up to 4 GB of addressabl e mem ory

space, allowing significant headroom for business des ktop systems. Please refer to the Inte l

Specification Update document’s S -spec number table to determine the cac hea bility for a giv en

proce ssor.

The Pentium II processor system bus operates in the sa me manner as the Pentium Pro processor

system bus. The Pentium II proce ssor system bus uses a va riant of GTL+ signa l technology called

AGTL+ signal technology. The Pentium II processor deviates from the Pentium Pro processor by

using comm ercially ava ilable di e for the second leve l (L2) ca che. The L2 c ac he (the TagRAM and

bur st pipeli ned sync hronous static RAM (BSRAM) memo ries) are now multipl e die. T r ansf er rate s

be tw een a Pentium II p r o cesso r’s co re and L2 cache are one-half th e p roce ss o r core clock

frequenc y and scale with the processor core frequency. Both the TagRAM and BSRAM receive

clocked data dir ectly from th e P entium II processor core. As wi th the Pentium Pro, the Pentium II

processor ha s a dedicated L2 cache bus, thus maintaini ng the dual independe nt bus architecture to

deliver high bus bandwidth and high performan ce (se e Figure 1).

Pentium II processors use either a Si ngle Edge Contact Cart ridge (S.E.C.C .) or a Single Edge

Conta ct Cart ridg e 2 (S.E.C. C.2) pac kaging t echnol ogy. Thes e packagin g te chnologi es allo w the L2

cache to remain tightly coupled to the pr ocessor, while enabl ing use of high volume commercial

SRAM components . The L2 c ache is perform ance optimized and tested at the package level. T he

S.E.C.C. an d S. E. C.C.2 package s utilize su rface mounted technology and a s ubstrate with a n edge

finger connection. Pentium II pr ocessors at 350, 400 and 450 MHz, while ava ilable at higher core

freque ncies t han the previous ly rel eased Pe nti um II proc essors a t 233, 266, 30 0 and 333 MHz , also

provide additional fe atures while utilizing either a com patible S.E.C.C. package or the follow-on

S.E.C.C.2 pa ckage.

The S.E.C. C. package has the foll o wing feature s: an ex tend ed thermal plate, a cover, and a

substr ate with a n edge fi nger co nnecti on. The exte nde d therm al pla te al lows he atsink a ttac hment or

cus tom ized thermal sol utions. The S.E.C.C.2 package has a cover and a subs trate with an edge

finger conenction. Thi s allows the thermal solutions t o be placed directly onto the processor core

pa cka g e. The ed g e finger con n ectio n maintains socketabilit y for system co nfiguration. The edg e

finger connector is called the ‘SC 242 connec tor ’ in this a nd othe r doc umentation.

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

8Datasheet

1.1 Terminology

I n this document, a ‘#’ s y mbol after a signal name ref ers to an active low signal. This means that a

sig n a l is in th e ac tiv e stat e (based on th e nam e of the si g nal) w h en dr i ven to a low lev el . F or

example, when FLUSH# is low, a flush has been reques ted. When NMI is high, a nonmaskable

interrupt has occurred. In the cas e of signals where the name does not imply an active state but

descr ibe s part of a binary sequenc e (such as address or data), the ‘#’ sym bol impli es that the signa l

is inverte d. For example , D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D#[3:0] = ‘LHLH’ also refers

to a hex ‘A’ (H= High logic leve l, L= Low logi c level).

The term “system bus” refers to the interfac e bet ween the processor, system core logic (a.k.a. the

AGPset components), and other bus agents. The system bus is a m ultiprocessi ng interface to

proce ssors , memory, and I/O. The term “cache bus” refers to the inte rface between the processor

and the L2 cache components (TagRAM and BSRAMs). The cache bus does NOT connect to the

system bu s, and is not vi sible to other ag ents on the s ys tem bus.

1.1.1 S.E.C. Cartridge Terminology

The followi ng terms are used often in this document and are e xplained here for clarification:

•Pentium® II proces sor—Th e entire product including inte rnal components, substrate,

extended thermal plate, a nd cover.

•S.E.C.C.—The process or packaging tec hnology is called a “Single Edge Contact Cart ridge.”

Initial releases of the Pentium II processor are based upon this pa ckaging technology.

•S.E.C.C.2—The follow-on to S.E.C.C. processor packaging technology. T he biggest

difference from its predecesso r is that it has no extended thermal plate, thus reducing thermal

resistance.

•Processor substrate—The structur e on whi ch comp onents are mo unted in side t he S. E.C.C. or

S. E. C.C.2 package technology (with or without components a ttached).

•Proce s so r co re—The proc es sor’s execution engine.

Figure 1. Second Lev el (L2) Cache Implementations

Pentium II Processor

Substrate and Components

Processor Core

Processor

Core Tag L2

Pentium® Pro Processor

Dual Die Cavity

Package

v001

Pentium® Pro Processor

Dual Ca vity

Package

Pentium II Processor

Substrate and Com ponents

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 9

•Extended Thermal Plate—Th is S.E.C.C. 100 MHz processo r featu re is the surfac e u sed to

attach a heatsink or other thermal solution to the pr ocessor. The extended thermal plate has an

extended skirt as compared to the 66 MHz Pentium II processors for increas ed thermal

capabilities.

•Cover—The plastic casing that covers the backsire of the substrate and holds processor

branding and marking information.

•Lat ch arms—A n S.E.C.C. processor fea ture which c an be used as a me ans for securi ng the

proces sor in the retention mechanism(s).

•PLGA - Pla stic Land Grid Array. This package technology incorporates a heat slug withi n the

packag e th at con ta cts th e ex t en d ed th er mal plate.

•OLGA - Organic Land Grid Array. This package technology permits attaching the heatsink

dir e ct ly to th e d ie.

Additional terms referred to in this and other rel ated doc um entat ion:

•SC 242—The 242-contact slo t connector (previously ref erre d to as S lot 1 connector) that the

S.E.C.C. and S.E.C.C.2 plug into, just as the Pentium® Pro pr o c essor uses So ck e t 8.

•Retention mechanism—An ena ble d me cha nic al piec e whic h ho ld s the S. E. C. car t ridg e in th e

SC 242 connector.

•Heatsink support—T he support pi eces t hat are moun te d on the m otherboa rd t o provid e a dded

support for heats inks.

The L2 cache (TagRAM, BSRAM) die keep industry names.

1.2 References

The reader of this specification should also be familiar with ma terial and co ncepts presented in the

following documents:

•AP-485, Intel Processor Identification and the CPUID Instruction (Or der Number 241618)

•AP-827, 100 MHz GTL+ La yout Guidelines for the Pent ium® II Processor and Intel® 440BX

AGPset (Order Number 243735)

•AP-586, Pentium® II Processo r Th ermal Desi gn Gu ideli ne s (Orde r Number 243331)

•AP-587, Pentium® II Proce ssor Po w er Di str ibu tio n Guide li nes (Order Number 243332)

•AP-588, Mechanical and Assembly Technology for S.E.C. Cartr idge Proce sso rs (Order

Number 243333)

•AP-589, Pentium® II Processor Electro-Magnetic Interfere nce (Order Number 243334)

•Pentium® II Pr ocessor at 233, 266, 300, 333 MHz (Order Number 243335)

•Pentium® II Processor Spec ification Update (Order Numb er 243337)

•Slot 1 Connector Specification (Order Number 243397)

•Slot 1 Bus Terminator Card Design Guide lines (Order Number 243409)

•Intel Architecture Software Developer's Manual (Order Number 243193)

—Vo lume I: Basi c Arch itecture (Or der Number 243190)

—Volume II: Instructi on Set Reference (Order Number 243191)

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

10 Datasheet

—Volu me III: System Progr amming Guide (Order Number 243192)

•P6 Fami ly of Proce ssors Ha rdwa re Developer’s Man ual (Order Number 244001)

•Pentium® II Processor I/ O Buffer Models, Quad Form at (deve lo p er.intel. co m)

2.0 Electrical S

ecifications

2.1 Processor System Bus an d VREF

Most Pentium II proce ssor signal s use a variation of th e lo w vol tage G un n i ng Trans c ei ve r Lo gi c

(GTL) signa ling technology.

The Pentium II proces sor sys tem bus spec ifica tio n i s simil ar to the GTL spec ifica tion, but has been

enhanc ed to provide larger noise margins and reduc ed ringing. The improvements are

accomplished by increasing the termination voltage level and controlling the edge rates. This

specific ation is di f feren t f r o m the s tandard GTL specif ication, and is referred to as GTL+. Fo r

more informa tion on GTL+ specifications, see AP-827, 100 MHz GTL+ Layout Guidelines for t he

Pentium® II Proce ssor and Intel ® 440BX AGPse t (Order Number 243735).

The Pentium II processor va ries from the Pentium Pro proc essor in its output buffer

implementation. The buffers tha t drive most of the s ystem bus signals on the Pentium II processor

are actively driven to VCCCORE for one cloc k cycle after the low to high transition to improve its

r is e times and redu ce noise. The se signals should still be considered open-drain and require

ter minat ion to a supply that provides the high signal level. Becau se this specifi cation is differ ent

f rom the s tandard GTL+ specification, it is referred to as Assisted Gun n ing Transit istor Logic

( AGTL+) in this document . AGTL+ logi c and GTL+ lo gic are compatibl e wi th eac h other and may

both be used on the same syst em bus.

AGTL+ signals are open-drain and require te rmination to a supply that provides the high si gnal

level. AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used

b y th e r eceivers to determine if a signal is a logical 0 or a logical 1, and is generated on t he S.E.C

cartridges for the proc essor c ore. Local VREF copies should be generated on the mother board for all

other device s on the AGTL+ sys tem bus. Termination (usually a resistor at each en d of the signal

tr ace) is used to pull t he bus up to the high voltage level and to cont rol reflections on the

tr ansmiss ion li ne. Th e process or cont ai ns ter mination re sisto rs that prov ide te rminat ion for one end

of the Pentium II processor sy stem bus. Thes e specifications assume another resistor at the end of

each signal trace to ens u re ad equate signal qu ality for t h e A G TL+ s i g nals; see Table 8 for the bus

terminat ion voltage specifications for AGTL+ and the Pentium® II Processor Dev eloper’s Manual

( Or der Num ber 243 502) for the GTL+ bus spe cification. Solutions exist for single-ended

termination as well, though solution space is affected. Figure 2 is a schematic re pres entation of

AGTL+ bus topology with Pentium II processors.

The AGTL+ bus depends on incident wave switc hing. Therefore tim ing calculations for AGTL+

signal s are ba sed on flight time as opposed to ca pac itive deratings. Analog signal simulation of the

Pentium II proc es sor system bus including trace lengths is highly recommende d when designing a

system wi th a he avily loaded AGTL+ bus, especially for systems us ing a sin gle set of termination

resistors (i.e., those on the processor substrat e) with the Intel® 440BX AGPset. Such desi gns will

not match the solution space allowed for by instal lation of termination resistors on the

mot herboard . See Int el’s World Wid e Web page (ht tp://dev eloper.i ntel. com) to downl oad t he buf fer

mode ls: Pentium® II Processo r I/O Bu ffer Mo dels, Quad Format (Electronic Form).

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 11

2.2 Clock Contr ol and Low Power States

Pentium II proc essors allow the use of AutoHALT, Stop -Grant, Sle ep, and Deep Sleep state s to

reduce power cons um ption by stopping the clock to internal se ctions of the proces sor, depe nding

on each p ar ticular sta t e. S e e F igure 3 for a visual re presentation of the Pentium II processor low

power states.

Figure 2. AGTL+ Bus Topo logy

Pentium® II

Processor ASIC Pe n tiu m II

Processor

ASIC

Figure 3. Stop Clock State Mach in e

PCB757a

2. Auto HALT Power Down Sta te

BCLK runnin g.

Snoop s and in terrupts al l owe d.

HALT Instr ucti on and

HA LT Bus C ycl e Generated

INIT#, BINIT# , INTR,

SMI#, RESET#

1. Normal State

Norm al execution.

STPCLK#

Asserted STPCLK#

De-asserted

3. Stop Grant State

BCLK runnin g.

Snoop s and in terrupts al l owe d.

SLP#

Asserted SLP#

De-asserted

5. S leep S tate

BCLK runnin g.

No snoops or i nterrupts allowed.

BCLK

Input

Stopped

BCLK

Input

Restarted

6. Deep S leep State

BCLK s t opped .

No snoops or i nterrupts allowed.

4. HALT /G rant Snoop S ta te

BCLK runnin g.

Service snoops to caches.

Snoop Event Occurs

Snoop Event Serviced

Snoop

Event

Occurs

Snoop

Event

Serviced

STPCLK# Asserted

STPCLK# De-as serted

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

12 Datasheet

For the processor to fully realize the low curre nt consumption of the Stop-Grant, Sleep, and Deep

Sl eep states, a Model Specific Register (MSR) bit mus t be set. For the MSR a t 02AH (Hex), bit 26

must be set to a ‘1’ (this is the power on def ault setting) for the proces sor to stop all internal cl ocks

during these modes. For more information, see the Pentium® II Process or Developer's Manual

( Order Num ber 243502).

Du e to the inability of processors to recog n ize bus transac tions during the Sleep an d Deep S leep

sta tes, two-way MP syste ms are not allowed to have one processor in S leep/D eep Sleep state and

the o th e r p roces so r in N o rm al or Sto p - G r an t stat e simu lt an e ou sly.

2.2.1 Normal State—State 1

This is the normal operating state for the pr ocessor.

2.2.2 AutoHALT Powerdown State—State 2

AutoHALT is a low power state entered when the processor executes the HALT instruction. The

pr oce ssor will transition to the Normal st ate upon the occurrenc e of SMI#, BINIT#, INI T#, or

LINT[1:0] (NMI, INTR). RESE T# will cause th e pr ocessor to immediately initialize itself.

The return from a Syste m Manage ment Interrupt (SMI) handle r can be to either Normal Mode or

the AutoHALT Power Down state. See the Intel Architecture Software Dev eloper's Manual,

Vol ume III: System Programmer's Guide (Order Number 243192) for mor e informati on.

FLUSH # will be serviced du ring the AutoHALT state, and th e p roceso r will retu rn to th e

AutoHALT state.

The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.

When the syste m deasser ts the STPCLK# int errupt, the processor will return executi on to the

HALT state.

2.2.3 Stop-Grant State—S tate 3

The Stop-Grant state on the processor is entere d when the STPCL K# sig nal is asserted.

Si nce the AGTL+ signal pins recei ve power from the syst em bus, these pins should not be driven

( allowing the level to r eturn to VTT) for minimum power drawn by the termination resistors in this

state. In addition, all other input pins on the system b us shoul d be driven to the inactiv e s tate.

BINIT# will be rec ognized while the processor is in Stop-Grant sta te. If STPCLK# is st ill asserted

at t he com pleti on o f the BINIT # bus ini tiali zati on, the proc essor wi ll remain i n Stop -Grant m ode. If

the STPCLK# is not as serted a t the completion of the BINIT# bus initializati on, the proces so r will

r eturn to Normal s tate.

FLUS H# will not be serviced during Stop-Grant state.

RESET# will cause the proce ssor to imme diately in itialize itself, but the processor will stay in

Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the

STPCL K# signal.

A transition to the HALT/Grant Snoop st ate will occur when the processor detects a snoop on the

system bus (see Sec tion 2. 2.4). A t ran siti on to the Slee p sta te (see Sec tion 2. 2.5) will oc cur wi th the

as sert ion of the SLP # si gnal.

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 13

While in the Stop-Grant St ate , SMI#, I NIT#, and LINT[1:0] will be latched by the processor, and

only serviced when the processor returns to the Normal state. Only one occurrence of each event

will be recognized u p on return to th e Normal state.

2.2.4 HALT/Grant Snoop State—State 4

The process or will respond to snoop tra ns actions on the Pentium II proces s or sy st em bus while in

Stop-Grant state or in AutoHALT Power Down state . During a snoop transaction, the processor

enters the HALT/Grant Snoop s tate. The processor will stay in this st ate until the snoop on the

Pentium II processor system bus has be en serviced (whethe r by the processor or another agent on

the Pentium II processor system bus). After the snoop is serviced, the processor will return to the

Stop-Grant state or AutoHALT Power Down state, as appr opriate.

2.2.5 Sleep State—State 5

The Sleep state is a very low power state in which the processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped all internal clocks . The Sleep s tate c an only be

entered from Stop-Grant state. Onc e in the Stop-Gr ant st ate, the SLP # pin can be asserted, causing

the processor to enter the Sleep st ate. The SL P# pin is not r ecognized in the Normal or AutoHALT

states.

Snoop even ts that occ ur while in Sleep State or dur ing a transition into or out o f Sl eep st ate wi ll

cause unpredicta ble behavior.

In the Sleep state, the proce sso r is in capable of responding to sn oop transactions or latchi ng

interrupt signa ls. No transitions or ass ertions of signals (with the exception of SLP# or RESET#)

are al lowed on the syste m bus while the process or is in Sleep state. Any tr ansi tion on an input

sign al before the processor has returned to Stop-Grant state wil l result in unpredict able be havior .

If RE S ET # is driven a ctive while the processor is in the Sleep state, and held active as specified in

the RE SET# pin specificatio n, then the process or will res et its elf, ignoring the transi tion through

Stop-Grant State. If RES ET# is driven active while the proc essor is in th e Sleep State, the SLP#

and STPCL K# signal s shoul d be de as sert ed im m ediately afte r RESE T# is asserted t o ens ure the

processor correctly executes the Reset sequence.

While in the Sleep st ate, the process or is capable of ent ering its l owest power state, the Deep Sl ee p

sta te, by stopping the BCLK input (se e Section 2.2.6). Onc e in the Sleep o r Deep Sl eep states, t h e

SLP# pin can be deasserted if another as ynchronous syste m bus eve nt occurs. The SLP# pin has a

mini mum assert ion of one BCLK period.

2.2.6 Deep Sleep State—State 6

The D eep Slee p state is th e l o w est power state the processor ca n en ter while maintaining co ntext.

The Deep Sl eep st ate i s ent ered by sto pping the BCL K input (afte r the Sl eep sta te was ent er ed from

th e asser tion of the SLP# pin). The proc essor is in Deep Sleep state immediately a f ter BLCK is

stopped. It is recomme nded that the BLCK input be he ld low during the Deep Sleep State.

Sto pping of the BCLK input lowers the overall current cons umption to leakage levels .

To re-enter the Slee p stat e, the BLCK input must be restarted. A pe riod of 1 ms (to allow for PLL

stabilization) mus t occ ur before the processor can be considered to be in the Slee p state. Once in

the Sleep sta te, the SLP# pin can be deasserted to re-enter the Stop-Grant state.

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

14 Datasheet

While in Deep Sleep state, the processor is inca pable of responding to snoop transactions or

latc hing interrupt signals. No transitions or assertions of signa ls are allow ed on the system bus

while the proce ssor i s in Deep Sleep s tate . Any transition on an input s ignal before the proce ssor

has returned to Stop-Grant state will result in unpre dictable behavior.

2.2.7 Clock Control

The pr ocessor pr ovides t he clock signal to the L2 cache. During AutoHALT Power Down an d

St op-Grant states, the pr ocessor will process a system bus sno op. The proces s or will not stop the

clock to the L2 cache during AutoHALT Power Down or Stop-Grant st ates. Entrance into the Halt/

Grant Snoop sta te w ill allow the L2 cache to be s nooped, similar to the Normal state.

When the proce sso r is in Sl eep and Deep Sleep st ates, it will not res pond to interrupts or sn oop

t ransactions. During t h e Sleep s tate, the clock to the L2 cache is not stopped . During the Deep

Sleep state, the clock to the L2 cache is stopped. The clock to the L2 cache will be restarted only

afte r the inte rnal clocking mec hani sm for the processor is stable (i.e., the processor has re-entered

Sleep state).

PIC CLK should not be remov ed during the AutoHALT Power Down or Stop-Grant states.

PIC CLK can be removed during the Sleep or Deep Slee p st ates . Wh en trans itioni ng from the Deep

Sleep state to the Sleep st ate, PICCLK mus t b e r estarted with BCLK.

2.3 Power and Ground Pins

The o perati ng voltag e of the proc essor die and of the L2 cache die diff er from each ot her. There are

two groups of power inputs on the Pentium II proce sso r pac kage to support thi s vol tage difference

bet ween the compo nents in the pa ckage. T here a re also five pins define d on t he packa ge f or volta ge

identification (VID). These pins specify the voltage required by the processor core. These have

been adde d to cleanly support voltage sp ec ification variations on current and future Pentium II

processors.

For clean on-chip power distribution, Pentium II processors have 27 VCC (power) and 30 VSS

(ground) inputs. The 27 VCC pins are fu rther divided to provide the dif f erent volt age levels to the

components. VCCCORE i nputs for th e processor cor e and some L2 cache co mpo nents account fo r 19

of th e VCC pins, while 4 VTT inputs (1.5 V) are used to provide a n AGTL+ terminatio n voltage to

the processor and 3 VCCL2 inputs (3.3 V) are for use by the L2 cache TagRAM and BS RAMs. One

VCC5 pin is provi ded for use by the Slot 1 T e st Kit . VCC5, VCCL2, and VCCCORE must remain electrically

se parated from each other. On the circ uit board, all VCCCORE pins must be connec ted to a voltage

island a nd all VCCL2 pins must be connec ted to a separate voltage island (an isla nd is a portion of a

power plane that has been divi ded, or an entire pla ne). Similarly, all VSS p ins must be connected to

a system ground plane.

2.4 De co upling Guide lines

Due to the large number of transistors and high internal clock speeds, the proc essor is capable of

gene rating la rge a verage current swings betwe en low and full power st ates. This ca uses vol ta ges on

power planes to sag be low the ir nom inal values if bulk decoupling is not adequate. Care must be

take n in the board design to ensure that the voltage provided to the processor re mains within the

spe ci fic at ion s list ed in Table 5. Fai lure to d o so ca n result in timing violations or a reduce d lifetime

of the component.

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 15

2.4.1 Proces sor VCCCORE Decoupling

Regulator solutions need to provide bulk capac itance with a low E ffective Series Res is tance (E SR )

and ke ep an interconnec t re sistance from the regula tor (or VRM pins) to the SC 242 connector of

les s than 0.3 mΩ. This can be acc omplishe d by keepi ng a maximum dis tance of 1.0 in ches between

the regulator output and SC 242 connec tor. T he re commended V CCCORE intercon nect is a 2.0 i nch

wide (the width of the VRM 8.2 connector) by 1.0 inch long (maximum dista nce bet ween the

SC 242 connector and the VRM 8.2 connector) plane segment with a 1-ounce plating. Bulk

decoupling for the large c urrent swings when the pa rt is powering on, or ente ring/exit ing low

power st ates, is provided on the voltage re gulation module (VRM). The VCCCORE input should be

capable of delivering a rec ommended minimum dI CCCORE/dt ( d efined in Ta ble 5) while mainta ining

the required tolerances (also defined in Table 5).

2.4.2 Processor System Bus AGTL+ Decou pling

The Pent ium II proces sor contai ns high frequency decoup ling capac itance on the processor

substr ate ; bulk dec ouplin g must be pr ovided for by the syste m motherboa rd for pro per AGTL+ bu s

operation. See AP-827, 100 MHz GTL+ Layo ut Guidelines for the Pentium® II Processor and

Intel® 440BX AG Pset (Order Number 243735), AP-587, Pentium® II Processor Pow e r

Distribution Guidelines (Order Number 243332), and the Pentium® II Processor Developer's

Manual (Orde r Numb er 243502) for mor e informati on.

2.5 Pro cessor System Bus Clock and Processor Clocking

The BCLK input directly c ontrols the operating speed of the Pentium II processor system bus

in terface. Al l Pentium II process o r system bus timing parameters are spec if ied with res p ect to the

risi ng edge of t he BCLK input . Se e the Pentium® II Proce ssor Deve lo per's Man ual (Order Number

243502) for further details.

2.5.1 Mixing Pr ocessors of Di fferent Fr equencies

Mixing processors of different interna l clock frequencie s is not supported and has not been

validated by Intel . One should als o note that when attempting to mix process ors rated at different

frequenci es in a two-way MP system, a c ommon bus clock fre quency and a set of multipliers must

be found that is acce ptable to both processors in the syste m. A process or may run at a core

frequency as low as its mini mum rating.

2.6 Voltage Identification

There are five voltage identifica tion pins on the SC 242 conne ctor. These pins ca n be us ed to

support automat ic selec tion of power s upply voltages . Th es e pins ar e not si gnals, but are eithe r an

open circ uit or a short circuit to VSS on the processor. The combination of opens and shorts defi nes

the voltage req uired by the processor core . The VI D pins are ne eded to cl eanly support voltage

specification variations on current and future Pentium II processors. These pins (VID[0] through

VID[4]) are defined in Table 1. A ‘1’ in this table refers to an open pin and a ‘0 ’ refers to a short to

ground. The de finition p r ovided in Table 1 is a supe rs et of the defi nition previous ly defined for the

Pentium Pro processor. The power s upply must s upply the voltage that is request ed or disable

itself.

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

16 Datasheet

To ensure the system is ready for curre nt and future Pentium II process ors , the range of va lue s in

bold in Table 1 must be supported. A smaller range will ris k the abi lity of the system t o migrate to

a highe r performance Pentium II proce ssor and/or maintain compat ibility with current P entium II

processors.

NOTES:

1. 0 = Proces sor pin connected to VSS.

2. 1 = Open on processor; may b e pulled up to TTL VIH on mo therboard.

3. VRM output should be dis a bled for VCCCORE values less than 1.80 V.

4. To ensur e the system is r eady for the P entium® II pr ocessors, the values in BOLD in Table 1 must be su pport ed.

Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given

slot as long as the power supply used does not a ffec t these lines. Detection logic and pull-ups

should not affect VID inputs at the power sourc e (see Section 7. 0).

The VID pins should be pulle d up to a TTL-compatible leve l with external resistors to the power

source of the regulator only if required by the regulator or external logic monitoring the VID[4:0]

signal s. The power source chosen m ust be guaranteed to be stabl e whenever the supply to the

volt age regulat or is sta ble. T his wil l prevent the pos sibil ity of the proces sor suppl y going above the

specified VCCCORE in the event of a fa ilure in the supply for the VID lines. In the case of a DC-to-DC

converter, this can be accom plished by using the input voltage to the converter for the VID line

Table 1. Vo ltage Identification Definition 1, 2, 3

Processor Pins

VID4 VID3 VID2 VID1 VID0 VCCCORE

01111 - 00110 Reserved

00101 1.80 4

00100 1.85 4

00011 1.90 4

00010 1.95 4

00001 2.00 4

00000 2.05 4

11111 No Core

11110 2.1 4

11101 2.2 4

11100 2.3 4

11011 2.4 4

11010 2.5 4

11001 2.6 4

11000 2.7 4

10111 2.8 4

10110 2.9

10101 3.0

10100 3.1

10011 3.2

10010 3.3

10001 3.4

10000 3.5

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 17

pull-u ps. A resistor of gre ater tha n or equal to 10 k Ω may be used t o connect the VID si gnals to the

converter input. Note that no changes have been made to the physical connector betwee n the VRM

8.1 and VRM 8.2 specifications, though pin definitions have changed.

2.7 Processor System Bus Unused Pins

All RESERVED pins must re ma in unconnected. Connection of thes e pins to V CCCORE, VCCL2, VSS, or

to any other signal (including each other) can result in component malfunction or incompatibility

with future Pentium II proc essors. See Sectio n 5.4 for a pin listing of the processor and the location

of each RESERVED pin.

All TES THI pins mus t be connected to 2.5 V via a pull-up resistor of betwee n 1 and 100 kΩ value.

PICCL K must be driven with a valid clock input and the PI CD[1:0] lines mu st be pulled-up to

2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each

PICD line (see Table 2 for recommende d values).

For reliable opera tion, always connect unus ed inputs or bidirectional signa ls to an appropriate

signal level . Unuse d AGTL+ inputs should be left as no connects; AGTL+ termination is provided

on the process or. Unused active low CMOS inputs sh ould be conne cted to 2.5 V. Unuse d ac tive

high inputs should be conne cted to ground (VSS). Unused outputs can be left unc onnected. A

res is tor m ust be used when tying bidirecti onal si gnals t o power or gro und. When tying any signal

to power or ground, a resistor will also a llow for syste m testability. For unused pins, it is s uggested

that ~10 kΩ r esis tors be used for pull-ups (except for P ICD[1:0] discussed above), and ~1 kΩ

resistors be used as pull-downs.

2.8 P ro cessor Sys tem Bus Sign al Groups

In order to s im plify the follo wing disc ussion, the Pentium II proces sor system bus signals have

been combined into groups by buffer type. All Pentium II processor system bus outputs are

open dra in and require a high-level source provided externally by the termi nation or pull-up

resistor.

AGTL+ input signals have differential input buffers, which use VREF as a re ferenc e signal. AGTL +

output signals require term ination to 1.5 V. In this do cument, the te rm “AGTL+ Input” refers to the

AGTL+ in put group as well as the AGTL+ I/O group when rece iving. Simil arly, “AGTL+ Output”

refers to the AGTL+ output group as well as the AGTL+ I/O group when driv ing.

EMI pins sho uld be connect ed to motherboard ground and/or to chass is ground through zero ohm

(0Ω) resisto rs . The 0Ω resistors should be placed in cl ose proximity to t he SC 242 connec tor. T he

path to chass is ground should be short in length and have a low imped ance.

The CMOS, Cl ock, APIC, and TAP inputs ca n eac h be driven from ground to 2.5 V. The CMOS,

APIC, and TAP outputs a re open drain and should be pulled high to 2.5 V. This ensures not only

correct operatio n for current Pentium II processors, but compatibility for future Pentium II

products as well. See Table 2 for recommended pull-up resistor values on each CMOS signal.

~150Ω resistors are expe cted on the PICD [1:0] l ines; other values in Table 2 ar e specifi ed f or

prop er logic analyzer and test m ode operation only.

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

18 Datasheet

NOTES:

1. These res ist or values ar e recommende d for system implementations us ing open-drain CMOS bu ffers.

2. ~150Ω resistors are expected for t hes e si gnals. This value may vary by s ystem and should be corr elated with the output

driv e charac teristics of th e devices generating the input signals. Other ap proximate val ues are recommended for proper

operation with the Pentium® II pr oces sor L ogic Analyzer Inte r face .

3. TRST# must be

ulled to

roun d vi a a 6 80Ω r esistor or driven low at

ower on with the assertion of RESET# (see

Table 19).

4. 1K−10KΩ pullup to 2.0 V (VCCCORE) or, if 2.5 V ramp s afte r core, pull up TES THI to 2.5V (VCC2.5) with a 100 kΩ

resistor.

The groups and the signals contained within eac h group are shown in Table 3. Refer to Section 7.0

f or des criptions of the se signals.

Table 2. Recommended Pull-u p Resi stor Values (Approximate ) for CMOS Signals 1, 2, 3

Recommended Resistor

Value (A

roximate) CMOS Si

nal

150ΩT DI, TDO, TMS, PICD[0], PICD[1]

150Ω – 220ΩFERR#, IERR#, THERMTRIP#

150Ω – 330ΩA20M#, IGNNE#, INIT#, LINT[1]/NMI, LINT[0]/INTR, PWRGOOD, SLP#, PREQ#

410ΩSTPCLK#, SMI#

500ΩFLUSH#

1KΩ–100KΩTESTHI4

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 19

NOTES:

1. The BR0# pin is the only BREQ# signal that is bidirectional. The internal BREQ# signals are mapped onto BR# pins

after th e agent ID is determined. See Section 7.0 for more information.

2. See S e ction 7. 0 for information on the PWRGOOD signal.

3. See S e ction 7. 0 for in for mat ion on the SLP # signal.

4. See Se ct i o n 7.0 for information on the THERMTRIP# signal.

5. These si gnals are specified for 2.5 V op eration. See Ta ble 2 for reco mmended pull-up resistor valu es .

6. VCCCORE is the power supply for the processor core an d L2 cache I/ O logic.

VCCL2 is the power supply for the L2 cache component core logic.

VID[4:0] is de scribe d in Se ction 2.6.

VTT is used to t erminate the sys tem bus and gen e r a te VREF on the process or s ubs trate.

VSS is s ys tem ground.

TESTHI s hould be connected to 2.5 V with a 1–100 kΩ resistor.

VCC5 is not connected to the Pentium® II pr ocesso rs. This supply is used for the Slot 1 Test Kit .

SLOTOCC# is described in Sectio n 7.0.

100/66# is described in Se ctio n 2.8.2 and Section 7.0.

EMI pins are desc ribed in Se c t io n 7.0.

THERMDP, THERMDN are described in Sect i o n 7.0.

2.8.1 As ynchronous vs. Synchronous for System Bus Signals

All AGTL + signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signa ls

can be applied as ynchronously to BCL K.

All APIC signal s a re s ynchronous to PICCLK. All TAP signals are syn chronous t o TCK.

2.8.2 System Bus Frequency Select Signal (100/66#)

This bidirectional si gnal is used to sel ect the system bus frequency. A logic low will se lect a

66 MHz system bus freq uency and a logic high (3.3 V) will se lect a 100 MHz system bus

freque ncy. The freq uency i s det ermi ned by t he proc essor(s ), AGPset and frequenc y syn thesize r . Al l

system bus agents must operate at the same frequency; in a two-way MP Pentium II processor

configuration, this signal must co nnect the pins of both Pe ntium II proc essors. This signa l will be

grounded by proce ssors that are onl y capable of operating at a host frequency of 66 MHz. On

Tabl e 3. System Bus Signal Groups

Grou

Name Si

nals

AGTL+ Input BPRI#, BR1#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#

AGTL+ Output PRDY#

AGTL+ I/O A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#1,

D[63:0]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM# , LOCK#, REQ[4:0]#, RP#

CMOS Input5A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGOOD2, SMI#,

SLP#3, STPCLK#

CMOS Out put5FERR#, IERR#, THERMTRIP#4

System Bus Clock BCLK

APIC Clock PICCLK

APIC I/O5PICD[1:0]

TAP Input5TCK, TDI, TM S, TRS T#

TAP Output5TDO

Power/Other6VCCCORE, VCCL2, VCC5, VID[4:0], VTT, VSS, SLOTOCC#, THERMDP, THERMDN,

100/66#, EMI

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

20 Datasheet

motherboards which support operation at eit her 66 or 100 MHz, this signal must be pulle d up to

3.3 V with a 1/4 W, 200Ω resi st or (as show n in Figure 4) and provided as a frequency selection

signal to the cloc k driver/synthesizer. If the system motherboard is not capa ble of operating at

100 MHz (e.g., Intel 440FX PCIset and 440LX AGPset-based systems), it should ground this

signa l and generate a 66 MHz s ystem bus frequency. T his signal can also be incorporated into

RESE T# logic on the motherboard if onl y 100 MHz operation is supported (thus forcing the

RESET# signal to remain active as long as the 100/66# signal is low).

2.9 Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Acce ss P ort (TAP) logic, it is

recommended that the Pentium II processor be first in the TAP chain and followed by any othe r

com ponents within the system. A translation buffer shoul d be us ed to conne ct to the rest of the

chain unless one of the othe r components is capabl e of ac ce pting a 2.5 V input. Si mi lar

considerat ions must be made for TCK, TMS, and TRST#. Two copies of each signal m ay be

required with each driving a different voltage le vel.

The Debug Port will have to be placed a t the start and end of the TAP chain with the TDI of the

f irs t component coming from the Debug Port and the TDO from the last compone nt going to the

Debug Port. In a two-way MP system, be cautious when inclu ding an empty SC 242 connector in

the scan cha in. All connecto rs in the sca n chain must have a processor installed to complete the

chain or the system mus t s upport a me thod to bypas s the e mp ty connec tors; SC 242 terminator

substr ates should not connec t TDI to T DO in order to avoid plac ing t he TDO pull-up resistors in

parall el. (See Slot 1 Bus Ter minator Car d Design Guidelines (Order Number 243409) fo r more

details.)

2.10 Maximum Ratings

Table 4 contains Pe ntium II processor stress rati ngs only. Functional operation at the abs olute

ma xim um a nd mi nimum is not implied nor guaranteed. The proces sor should not receive a clock

while subjected to these conditions. Functional operating conditions are given in the AC and DC

tables in Section 2.11 an d Section 2.13. Exte nded exposure to th e maxim um r atings may affe ct

device reliability. Furthermor e, alt hough the processor contains protective cir cuitry to resist

dam age f r om sta tic el ectric discharge, one should always take precautions to a void high stat ic

vol ta g es o r elec t ric f ie ld s.

Figure 4. 100/66# Pin Example

3.3 Volts

100/66#

CK100

Processor

Core

GND

Pentium® II Processor

3. 3 K Ω

1 KΩ

200 Ω

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 21

NOTES:

1. Operating voltage is the voltage to which the component is designed to operate. See Table 5.

2. Th is rat ing app lies to the VCCCORE, VCCL2, VCC5, and any inp ut (ex cept as noted below) to the pr oces s or.

3. Parameter applies to CMOS, APIC, and TAP bus signal groups o nly.

4. The mechanical integrity of the latch arms is specified to last a maximum of 50 cycles.

5. The elect rical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion /extractio n

cycles.

6. While ins ertion/extract ion cycli ng above 50 i ns ertion s w ill cause an i ncr ease in t he contact re s istance (above 0.1Ω) and

a degr adati on in the mat eri al integ rit y of the edg e fing er gol d plati ng, it is pos sibl e to have pr oces sor func tion al ity ab ove

the specified lim it. The actual number of inser tio ns before proces s or failure will vary based upon system confi gur ation

and environmental conditions.

2.11 Pr oc essor DC Specifications

The proces sor DC specifications in this section are defined at the Pentium II processor edge

fingers. See Section 7.0 for the process or edge finger signal definitions and Section 5.0 for the

signal listing.

Most of the signals on the Pentium II proc es s or system bus are in the AGTL+ signal group. These

signals are specified to be terminated to 1.5 V. The DC specifications for these signals are listed in

Table 6.

To allow connec tion with other devices, t he Clock, CMOS, APIC, and TAP sign als are designed to

interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 7.

Table 5 thro ugh Ta ble 8 l ist the DC sp ec ifications for Pentium II proce ssors ope rating at 100 MHz

processor syste m bus frequencie s . S pec ifications are valid only while meeting specifications for

case te mpera ture, clock freq uenc y, a nd input voltages. Care should be taken to read all notes

as so ci at ed w it h each p aramet er.

Table 4. Absolute Maximum Ratings

mbol Parameter Min Max Unit Notes

TSTORAGE Pr ocessor storage temperature –40 85 °C

VCC(All) Any processor supply voltage

with respect t o VSS –0.5 Oper ating voltage + 1.0 V 1, 2

VinAGTL AGTL+ buffer DC input

voltage with respect to VSS –0.3 VCCCORE + 0.7 V

VinCMOS CM OS buffer DC i npu t

voltage with respect to VSS –0.3 3.3 V 3

IVID Max VID pin cur rent 5 mA

ISLOTOCC Max SLOTOCC# pin current 5 mA

Mech Max

Latc h Arms Mechanic al integrity of latch

arms 50 Cycles 4

Mech Ma x Edg e

Fingers Mechanical integrity of

pro ces s or edge fingers 50 Insertions/

Extractions 5, 6

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

22 Datasheet

Table 5. Voltage and Current Specifications 1

mbol Parameter Core Fre

Min T

Max Unit Notes

VCCCORE VCC for pr ocessor core 1.9 2.00 2.1 V 2, 4, 5, 6

VCCL2 VCC f or s econd level

cache 3.135 3.30 3.465 V 3.3 V ±5% 7

VTT AGTL+ bus termination

voltage 1.365 1.50 1.635 V 1.5 ±9% 8

Baseboard

Tolerance,

Static

Processor core vo ltage

stati c tole ra nce level at

SC 242 pins –0.070 0.070 V 4, 9

Baseboard

Tolerance,

Transient

Processor core vo ltage

transient tolerance level

at SC 242 pins –0.110 0.110 V 4, 9

VCCCORE

Tolerance,

Static

Processor core vo ltage

stati c tole ra nce level at

edge fingers –0.085 0.085 V 4, 10

VCCCORE

Tolerance,

Transient

Processor core vo ltage

transient tolerance level

at edge fingers –0.140 0.140 V 4, 10

ICCCORE ICC for processor core 350 MHz

400 MHz

450 MHz

10.8

12.0

13.6

2, 4, 12, 13

ICCL2 ICC for second level

cache

350 MHz

400 MHz

450 MHz

0.7

0.9

1.0

4, 7, 12

IVTT T ermination voltage

supply current 2.7 A 14

ISGnt ICC Stop-Grant for

processor core

350 MHz

400 MHz

450 MHz

0.8

0.9

1.0

4, 11, 12, 15

ISGntL2 ICC Stop-Grant for

seco nd level cache 0.1 A 4, 7, 12

ISLP ICC Slee p f or process or

core

350 MHz

4 00 MH z

450 MHz

0.8

0.9

1.0

4, 11, 12

ISLPL2 ICC Sleep for second

level cache 0.1 A 4, 7, 12

IDSLP ICC Deep Sleep for

processor core 0.35 A

IDSLPL2 ICC Deep Sl eep for

seco nd level cache 0.1 A

dICCCORE/dt P ower supply current

slew rate 20 A/µs 3 , 16, 17, 18

dICCL2/dt L2 cache power s upply

curre nt slew rate 1A/

µs 16, 17, 18

dICCvTT/dt Termination current slew

rate 8A/µs

See

Ta ble 8 17, 18

VCC5 5 V supply voltage 4.75 5.00 5.25 V 5 V ±5% 19

ICC5 ICC for 5 V s upply

voltage 1.0 A 19

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 23

NOTES:

1. Unless otherwise noted, all spec ifications in this table apply to all processor frequencies and cache sizes.

2. VccCORE and IccCORE su p ply the processor core and the TagR AM and BSRAM I/O buffers.

3. Th is spe c ifica tio n appli es only to the Pen tiu m® II processor . Unless otherwise noted, this specification applies to all

Pentium II pr ocessor frequencie s and cache sizes.

4. This s pecifi cati on ap plie s only t o the Pen tiu m II proc essor when opera ting with a 10 0 MHz Pen tiu m II pro cessor syst em

bus. Unless otherwise noted, this spe ci fication applies to all Pe ntium II processor cache sizes.

5. These voltages are targets only. A var iable vol tage source should exist on s ys tems in the event t hat a dif f erent vol tage is

required. See Sect ion 2.5 and Tab le 1 for more inf ormati on.

6. Use the Typical Voltage specification with the Tolerance specificati ons t o provide correct voltage regu lation to the

processor.

7. VCCL2 and ICCL2 su p pl y the seco n d leve l cach e. Unles s oth erw ise noted, th is speci fic a tion a pplie s to all Pe nt ium II

pro ces s or cache sizes. Systems s hould be designed for thes e sp ecificatio ns , even if a smaller cache size is used.

8. VTT must be held to 1.5 V ±9%. It is recommended that VTT be held to 1.5 V ±3% while the Pentium II processor

system b us is idle. This is me asured at the processor edg e f ingers .

9. These are the toleran ce requ i rement s, a cross a 20 MHz band widt h, a t the SC 242 connect or pi n on th e bott om side of the

ba s eboard. The req uirements at the SC 242 connector p ins account for voltage drops ( and impedance di s continuities)

across the connector, pr ocessor edge fi ngers, and to the process or core. VccCORE must return to within the static volta ge

specifica tion within 100 µs after a transient even t.

10.These ar e the tolerance requirements, across a 20 MHz bandwidth, at the proces s or edge fingers. Th e requireme nts a t

the processor edge fingers accoun t f or voltage drops ( a nd impedance dis continuities) at th e processor edge fi ngers and

to the proc es s or cor e. VccCORE must return to within the static voltage specification within 2 µs after a transient event.

11.These are estimated valu es not actual measu rements.

12.Max ICC measurement s are measured at VCC max voltage, 95 °C ±2 °C , under maxi mum s ignal loadin g conditio ns . The

Max I cc currents specified do not occ ur s imultaneously under the stres s meas urement condition.

13.Voltage regul ators may be designed with a mi nimum equival ent internal resistance to ensure that the out put voltag e, at

maximum current output, is no greater than the nomi nal (i.e., typical) volt age level of VccCORE (VccCORE_TYP). In this

cas e, t he maximum current le vel for the regul ator, Icc CORE_REG, can be reduced from the specified maximum current

IccCORE _MAX and is calcu lated by the equation:

IccCORE_REG = I cc CORE_MAX × Vc cCORE_TYP / (V ccCORE_TYP + VccCORE Tolerance, Transient)

14.The curr e nt specifie d is t he current required for a single Pentium II processor. A simi lar amo unt of current is dr aw n

through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended termination is used (see

Sectio n 2.1).

15.The current specified is also for AutoHALT state.

16.Maximum values are specified by design/characterization at nominal VccCORE and nominal V CCL2.

17.Based on simulati on and averaged over the duratio n of any change in cur r ent. Use to compute t he maximum inductance

tolerable and reaction time of the voltage regulator . This parameter is not tested.

18.dICC/dt specification s ar e meas ured and specified at the SC 242 connector pi ns .

19.VCC5 and ICC5 are not used by the Pentium II processors. This supply is used for the SC 242 T est Kit.

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

24 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. VIH and VOH for the Pentium II processor may exp erience excursions of up to 200 m V above VTT for a single system bus

clock. However, input signal drivers must comply with the signal quality specifications in Sect ion 3.0.

3. Mi nimum and maximum VTT are gi ven in Table 8.

4. (0 ≤ VIN ≤ 2.0 V +5%).

5. (0 ≤ VOUT ≤ 2. 0 V +5%).

6. Refer to the I/O Buf fer Mode ls for IV characteristics.

7. Parameter corre lated to measure into a 25Ω resistor terminated to 1.5 V.

8. Refer to the IO Buffer Models for IV characteristics.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. Para meter measur ed at 14 mA (for use wit h TTL inputs).

3. (0 ≤ VIN ≤ 2.5 V +5%).

4. (0 ≤ VOUT ≤ 2. 5 V +5%).

2.12 AGTL+ System Bus Specifications

I t is recommen ded that the AGTL+ bus be rout ed in a dai sy-cha in fash ion with terminat ion

resist ors to VTT at each end o f th e si gnal t race. Th ese te r mination resis tors ar e p l aced electrically

between the ends of th e s ignal traces and the VTT voltage supply and gen erally are cho sen to

approximate the subst rate impedance. Th e valid high and low levels ar e determined by the input

buffers using a refe renc e voltage called VREF.

Table 8 li sts the nominal specification for the AGT L+ ter mination vo ltage (VTT). The AGTL+

r efe renc e voltage (VREF) is generated on the proce s sor substrate for the processor c ore, but should

b e set to 2/3 VTT for other AGTL+ logic using a voltage divider on the m otherboard. It is im portant

that the motherboard impedanc e be specified and held to a 65Ω± 15% tolerance, and that the

Tabl e 6. AGTL+ Signal Groups DC Spec ifications 1

mbol Parameter Min Max Unit Notes

VIL Input L ow Voltage –0.3 0.82 V

VIH Input Hi gh Voltag e 1.22 VTT V 2, 3 , 7, 8

Ron Buffer On Resistance 16.67 Ω 6

ILLeakage Cu r rent ±100 µA 4

ILO Output Leakage Current ± 15 µA 5

Tabl e 7. Non-AGTL+ Si gn al Group DC Spe cifications 1

mbol Parameter Min Max Unit Notes

VIL Input L ow Voltage –0.3 0.5 V

VIH Input Hi gh Voltag e 2.0 2.625 V 2. 5 V +5% maxi mum

VOL Output Low Voltage 0.4 V 2

VOH Output High Volta ge N/A 2.625 V All outputs are open-

drain to 2.5 V +5%

IOL Output Low Current 14 mA

ILI Input Leakage Curre nt ± 100 µA 3

ILO Output Leakage Current ± 15 µA 4

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 25

intrinsic trace ca pacitance for the AGTL+ signal group trace s is known and well -controlled. For

more details on GTL+, se e the Pentium® II Processor Dev eloper's Manual (Order Number

243502) an d AP-827, 100 MHz GT L + L ayout Gui delines f or the Pent ium® II Processo r and Intel®

440BX AGPset (Order Number 243735).

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. Pentium II pr ocessors contain AG TL + termination resistors at t he end of each signal trace on the processor substrate.

Pentiu m II processor s generate VREF on the process or substrat e by u s ing a voltage divid e r on VTT supplied through the

SC 242 connector.

3. VTT must b e held to 1.5 V ±9%; dICCVTT/dt is specified in Table 5. It is r ecommended that VTT be he ld to

1.5 V ±3% while the Pentium II processor syste m bus is idle. This is measured a t the processor edge fingers.

4. VREF is generated on the processor substrate to be 2/ 3 V TT nominally.

2.13 System Bus AC Specificat ion s

The Pe ntium II processor system bus timi ngs specified in this section are defi ned at the Pentium II

processor e dge fingers an d the proce ssor core pads. Unless ot herwise spec ified, timings are tes ted

at the pr oce ssor core during manufacturing. T imings at the proc essor edg e fingers are specified by

design cha racteriz ation. See Section 7.0 for the Pentium II proce ssor edge c onnector signal

defini tions. See the Pentium® II Pr oc ess or at 233, 266, 300 , and 333 MHz (Orde r Numbe r 2433 35)

for more detail.

Table 9 throug h Table 20 list the AC specifications associated with the Pentium II processor system

bus. The se sp ecifications are brok en into the following cate gories: Table 9 through Table 1 1

contain the system bus clock cor e freq uenc y and cache bus frequenci es, Table 12 and Table 13

contain the AGTL+ spec ifications, Table 14 and Table 15 are the CMOS signal group

specificati ons, Tabl e 16 contains timings for the Re set c onditions, Table 17 and Table 18 cover

APIC bus tim ing, and Table 19 and Table 20 cover TAP timing. For each pa ir of tables, the firs t

table cont ains timing spec ifications for m easure ment or simulation at the processor edge fingers.

The sec ond table c ontains specifications for simula tion at the processor core pads.

All Pentium II proce ssor s yste m bus AC specifications for the AGTL+ signa l group are relative to

the rising edge of the BCLK input. All AGTL+ timings are refe renced to VREF for both ‘0’ and ‘1’

logic levels unless otherwise specified.

The timings spe cified in th is section should be used in conjunction with the I /O buffer mode ls

provided by Intel. These I/O buffer models , which inc lude package information, are available for

the Pentium II processor in Q uad format as the Pentium® II Processor I/O Buffer Models, Quad

Format (Electronic Form) on Intel’s website: “http://www.intel.com.” GTL + layout guideli nes are

also available in AP-827, 100 MHz GTL+ Layout Guidelines for the Pentium ® II Pro ce ssor and

Intel® 440BX AG Pset (Order Number 243735).

Care should be taken to read all notes associa ted with a pa rticular timi ng parameter.

Table 8. AGTL+ Bus Specifications

1, 2

mbol Parameter Min T

Max Units Notes

VTT Bus T ermination Voltage 1.365 1.50 1.635 V 1.5 V ±9% 3

RTT Termin ation Resist or 56 Ω±5%

VREF Bus Reference Voltage 2/3 VTT V4

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

26 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edg e at 0.50 V at the processor edge fingers.

Thi s r e f e r ence is to account for trace length and capacitance on the processor substrate, al lowing the processor co re to

receive the si gnal with a reference at 1.25 V. All AGTL+ signal timi ngs (address bus, data bus, etc.) are refer e nced at

1.00 V at the processor edge fingers.

3. All AC t imi ngs for the CM OS s ignal s are refe r e nced to the BCLK ris ing edge at 0.7 V at th e processor edge fingers.

Thi s r e f e r ence is to account for trace length and capacitance on the processor substrate, al lowing the processor co re to

receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at

1.25 V at the processor edge fingers.

4. The internal core clock f r e quency is deri ved from th e Pentium II processor system bus clock. The system bus cl ock to

core clock ratio is determined during initialization as described in Se ction 2. 5. Table 1 1 shows the su pported ratios for

e ach pr ocessor.

5. The BCLK period allows a +0.5 ns -0.0ns tolerance for clock driver variation.

6. This s pecifi catio n applies to Pen tium II processors w hen operating with a Penti um II processor sys tem bus frequency of

100 MHz.

7. The BCLK of fset t ime is t he a bs olute difference needed between the BC LK s ignal arri ving at the Pentium II processor

edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account for the del ay

be tween the SC 242 conne ctor and proces s or core. The posi ti ve of fset ens ures both the processor core and the core logic

receive the BCLK edge concurrently.

8. See Sectio n 3.1 for Penti um I I process or s ys tem bus cloc k s ignal quality specifications.

9. Not 100% tested. Specified by design characterization as a clock driver requirement .

Tabl e 9. System Bus AC Specif ications (Clock) at the Processor Edge Fingers 1, 2, 3

T# Parameter Min Nom Max Unit Fi

ure Notes

Syst em Bus Frequency 100.00 MHz All processor core

frequencies 4

T1’: BCLK Perio d 10.0 ns 6 4, 5

T1B’: SC 242 to Core Logic BCLK Offset 0.78 ns 6 Absolute Value 7, 8

T2’: BCLK Period Stability See Table 10

T3’: BCLK High Time 2.1 ns 6 @>2.0 V 6

T4’: BCLK Lo w Time 1.97 ns 6 @<0.5 V 6

T5’ : BCLK Rise Time 0.88 2.37 ns 6 (0.5 V– 2.0 V) 6, 9

T6’: BCLK Fall Time 1.13 2.94 ns 6 (2.0 V–0.5 V) 6, 9

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 27

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. All AC timings for the AG TL+ signals are refere nced to t he BCLK risin g edge at 1.25 V at th e processor cor e pin. All

AGT L+ signal timin gs (address bus , data bus, etc.) are refer enced at 1.00 V at t he processor core pins.

3. All AC timing s for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the proce ssor core pin. All

CMOS signal t imings (compatibili ty signals, etc.) are ref erenced at 1. 25 V at the proces s or core pins.

4. The int e r nal core clock frequency is derived from the Pentium II processor system bus clock. The system bus c lock to

core clock ratio is determined during initialization as described in Secti on 2.5. Table 11 shows the supported ratios for

eac h pr ocessor.

5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.

6. This specification applies to the Pentium II processor when operating with a Pentium II processor system bus frequency

of 100 MHz.

7. Due to the difficulty of accurately measuring clock jitter i n a system, it is recommended that a clock driver be used that

is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on the

risin

es of ad

acent BCLKs crossin

1.25 V at the

rocessor core

in. The jit ter pre sent m ust be acco un ted for

as a comp onent of BCLK tim ing skew between devices.

8. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter create d

by th e clock dr ive r . The –20 dB attenu at ion po int, as measu red int o a 10 to 20 pF load, sho uld be les s than 500 kHz. This

spe c ification may be ensured by design charact erization and/or measured with a spectrum analyzer.

9. Not 100 % tested. Specified by desi gn character ization as a cl ock driv er requi remen t.

10.The average period over a 1uS period of time must be greater t han the mi nimum specifie d period.

NOTES:

1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency multiplie rs.

2. While oth er bus ratio s are defined, operation at frequencies other than those listed are not supported.

Ta b l e 10. Sy st em Bus AC S p ec i fica t i o n s (Cl o ck ) at Pro ce s so r C o re Pin s 1, 2, 3

T# Parameter Min Nom Max Unit Fi

ure Notes

Sys tem Bus Frequency 100.00 MHz All proc essor core

frequencies 4

T1: BCLK Period 10.0 ns 6 4, 5, 6, 10

T2: BCLK Period Stability ±250 ps 6 6, 7, 8, 10

T3: BCLK High Time 2.6 ns 6 @ >2.0 V 6

T4: BCLK Low Time 2.47 ns 6 @<0.5 V 6

T5: BCLK Rise Time 0.38 1.25 ns 6 (0.5 V–2.0 V) 6, 9

T6: BCLK Fall Time 0.38 1.5 ns 6 (2.0 V–0.5 V) 6, 9

Table 11. Valid System Bus, Core Frequency, and Cache Bus Frequencies 1, 2

Core Fre

uenc

(MHz) BCLK F re

uenc

(MHz) Fre

uenc

Multi

lier L2 Cache (MHz)

350.00 100.00 7/2 175.00

400.00 100.00 4/1 200.00

450.00 100.00 9/2 225.00

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

28 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II proces s or fr equencies and cache sizes.

2. Not 100% tested. Specified by design characterization.

3. All AC timings for AGTL+ signals are re ferenced to the BCLK rising edge at 0. 7 V at the pro cessor edge fingers. All

AGT L+ signal timings (co m patibility s ignals, et c.) are referenced at 1. 00 V at the pr ocessor edge fingers.

4. Valid delay timings for these signals are specified into 50Ω t o 1.5 V and wi th VREF at 1.0 V.

5. A mini mum of 3 clocks must be guaranteed between two active-to-i nactive transitions of TRD Y #.

6. RESET# can be asserted (active) as ynchron ous ly, but must be deasserted synchronously.

7. Sp e cifi c a tion is for a m inim um 0. 40 V s w ing.

8. Specification is for a maximum 1.0 V swing.

9. After VCCCORE, VCCL2, and BCLK become stable.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II proces s or fr equencies and cache sizes.

2. These speci f ications ar e tested during manufacturing.

3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edg e at 1.25 V at the processor core p in. All

AGT L+ signal timings (co m patibility s ignals, et c.) are referenced at 1. 00 V at the pr ocessor core pins.

4. Valid delay timings for these signals are specified into 25Ω t o 1.5 V and with VRE F at 1.0 V.

5. A mini mum of 3 clocks must be guaranteed between two active-to-i nactive transitions of TRD Y #.

6. RESET# can be asserted (active) as ynchron ous ly, but must be deasserted synchronously.

7. Sp e cifi c a tion is for a m inim um 0. 40 V s w ing.

8. Specification is for a maximum 1.0 V swing.

9. This should be measured after VCCCORE, VCCL2, and BCLK become stable.

Table 12. System Bus AC Sp ecifications (AGTL+ Signal Group)at the Processor Edge Fingers 1, 2, 3

T# Parameter Min Max Unit Fi

ure Notes

T7’: AGTL+ Output Val id Delay 0.71 4.66 ns 7 4

T8’: AGTL+ Input Setup Time 1.97 ns 8 5, 6, 7

T9’: AGTL+ Input Hold Time 1.61 ns 8 8

T10’: RESET# Pulse W idth 1.00 ms 10 9

Table 13. System Bus AC Speci ficati ons (AGTL+ Signal Group) at the Processor Core Pins 1, 2, 3

T# Parameter Min Max Unit Fi

ure Notes

T 7: AGTL+ O u t pu t Val id De l a y -0. 20 3.4 5 ns 7 4

T8: AGTL+ Input Setup Time 2.10 ns 8 5, 6, 7

T9: AGTL+ Input Hold Time 0.85 ns 8 8

T10: RESET# Pulse W idth 1.00 ms 10 6, 9

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 29

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. Not 100 % tested. Specified by desi gn character ization.

3. All AC timin gs for the CMOS signa ls are r efere nced to the BCLK risi ng edge a t 0.5 V at the process or edge finger s. Al l

CMOS signal t imings (address bus, data bus, etc.) a re re ferenced at 1.25 V.

4. These si gnals may be driven asynchronously.

5. Valid delay timings fo r these signals ar e s pecified to 2.5 V +5%. See Ta ble 2 for pull-up resisto r valu es .

6. To ensur e r ecognition on a s pecific clock, the setup and hold times with respect to BCLK must be met.

7. INTR and NMI are only valid when the local APIC is disabled. LINT[1:0] are only valid when the local APIC is

enabled.

8. When driven inactive or after VCCCORE, VCCL2, and BCLK become stable.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. These specifications are teste d dur ing manufactu ring.

3. All AC timing s for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the proce ssor core pins. All

CMOS signal t imings (address bus, data bus, etc.) a re re ferenced at 1.25 V.

4. These si gnals may be driven asynchronously.

5. Valid delay timings fo r these signals ar e s pecified to 2.5 V +5%. See Ta ble 2 for pull-up resisto r valu es .

6. This s pecification applies to Pentiu m II pr ocessors operating w ith a 100- MHz Penti um II proces sor syst em bus only.

7. To ensur e r ecognition on a s pecific clock, the setup and hold times with respect to BCLK must be met.

8. INTR and NMI are only valid when the local APIC is disabled. LINT[1:0] are only valid when the local APIC is

enabled.

9. When driven inactive or after VCCCORE, VCCL2, and BCLK become stable.

Table 14. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers 1, 2, 3, 4

T# Parameter Min Max Unit Fi

ure Notes

T11’: CMOS Output Valid Delay 1.00 10.5 ns 7 5

T12’: CMOS In put Setup T ime 4.50 ns 8 6, 7, 8

T13’: CMOS Input Hold Time 1.50 ns 8 6, 7

T14’: CMOS In put Pulse Width, except

PWRGOOD 2 BCLKs 7 Active and Inactive

states

T15’: PWRGOOD Inactive Pulse Width 1 0 BCLKs 7, 10 8

Table 15. System Bus AC Specifications (CMOS Signal Group)at the Processor Core Pins 1, 2, 3, 4

T# Parameter Min Max Unit Fi

ure Notes

T11: CM OS O utput Valid D e lay 0.00 8.00 ns 7 5

T12: CMOS Input Setup Time 4.00 ns 8 6 , 7, 8

T13: CMOS Input Hold Time 1.30 ns 8 6, 7

T14: C MOS Input Pulse Width, except

PWRGOOD 2BCLKs7

Active and Inactive

states

T15: PWRGOOD Inactive Pulse Wi dth 10 BCLKs 7, 10 9

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

30 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. For a Reset, the clock ratio defined by t hes e signals must be a sa fe value (their fina l or a lower multiplier) within this

delay unless PWRGOOD is being driven inactive.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. Not 100% tested. Specified by design characterization.

3. All AC timings for the APIC I/O sig nals are referenced to the PICCLK rising edge at 0.7 V at the processor edge

fingers. All APIC I/O signal timing s are referenced at 1.25 V at the processor edge fingers.

4. Reference d to PICCLK rising edge.

5. For open drain s ignals, valid delay is synonymous w ith float delay.

6. Valid delay timings for these signals are specified to 2.5 V +5%. See Table 2 f o r r ec o m m e nded pull-up res is tor va l u e s .

Table 16. System Bus AC Speci ficati ons (Reset Condi tio ns) 1

T# Parameter Min Max Unit Fi

ure Notes

T16: Reset Configuration Signals

(A[1 4:5]#, BR0#, FLUSH#,

INIT #) Setu p Time 4 BCLKs 9 Before deassertion of

RESET#

T17: Reset Configuration Signals

(A[1 4:5]#, BR0#, FLUSH#,

INIT# ) Hold Time 2 20 BCLKs 9 After clock that

deasserts RESE T#

T18: Reset Configuration Signals

(A20M#, IGNNE#, LINT[1:0 ])

Setup Time 1ms9

Before deass ertion of

RESET#

T19: Reset Configuration Signals

(A20M#, IGNNE#, LINT[1:0 ])

Delay Time 5 BCLKs 9 After asse rtion of

RESET# 2

T20: Reset Configuration Signals

(A20M#, IGNNE#, LINT[1:0 ])

Hold Time 220BCLKs9, 10

After clock that

deasserts RESE T#

Table 17. System Bus A C Specifications (AP IC Clock and A PIC I/O ) at the Processor Edge Fingers

1, 2, 3

T# Parameter Min Max Unit Fi

ure Notes

T21’ : PICCLK Frequency 2.0 33.3 MHz

T22’: PICCLK Period 30.0 500.0 ns 6

T23’: PICCLK High Time 12.0 ns 6

T24 ’: PICC LK Low Time 12. 0 ns 6

T25’: PICCLK Rise Time 1.0 5.0 ns 6

T26 ’: PICC LK Fa ll Time 1.0 5.0 ns 6

T27’ : PICD [1:0] Setu p Time 8.5 ns 8 4

T28’: PICD [1: 0] Hold Tim e 3.0 ns 8 4

T29’: PICD[1:0] Valid Delay 3.0 12.0 ns 7 4, 5, 6

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 31

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. These specifications are teste d dur ing manufactu ring.

3. All AC t imings for the API C I/O si gnals are referenced to the P ICCL K rising edge at 1.25 V at the pr oces sor core pins.

All APIC I /O signal t imings are referenced at 1.25 V at the processor co re pi ns .

4. Referenced to PICCLK rising edge.

5. For open drain signals, valid delay is synonymous with float delay.

6. Valid delay timings fo r these signals ar e s pecified to 2.5 V +5%. See Ta ble 2 for reco mmended pull-up resistor valu es .

Tabl e 18. System Bu s AC Speci ficati o ns (APIC Clock and APIC I/O )a t the Processor Co re Pins 1, 2, 3

T# Parameter Min Max Unit Fi

ure Notes

T21: PICCLK Frequency 2.0 33.3 MHz

T22: PICCLK Period 30.0 500.0 ns 6

T23: PICCLK High Time 12.0 ns 6

T24: PICCLK Low Time 12.0 ns 6

T25: PICCLK Rise Time 1.0 5.0 ns 6

T26: PICCLK Fall Time 1.0 5.0 ns 6

T27: PICD[1:0] Setup Time 8.0 ns 8 4

T28: PICD[1:0] Hold Time 2.5 ns 8 4

T29: PICD[1:0] Valid Delay 1.5 10.0 ns 7 4, 5, 6

Ta b l e 19. Syst em Bus AC Sp ec i fi ca t i o ns (TAP Co n n e ct io n ) at the Proc esso r Ed g e Fin gers 1, 2, 3

T# Parameter Min Max Unit Fi

ure Notes

T30’: TCK Frequency 16.667 MHz

T31’: TCK Period 60.0 ns 6

T32’: TCK High Time 25.0 ns 6 @1 .7 V

T33’: TCK Low Time 25.0 ns 6 @0.7 V

T34’: TCK Rise Time 5.0 ns 6 (0.7 V–1.7 V) 4

T35’: TCK Fall Time 5.0 ns 6 (1.7 V–0.7 V) 4

T36’: TRST # Pulse W idth 40.0 ns 12 Asyn chronous

T37’: TDI, TMS Setup Time 5.5 ns 11 5

T38’: TDI, TMS Hold Time 14.5 ns 11 5

T39’: TDO Va lid Del ay 2.0 13. 5 ns 11 6, 7

T4 0’: TDO Fl oa t D el ay 2 8.5 ns 11 6, 7

T41’: All Non-Test Outputs Valid Delay 2.0 27.5 ns 11 6, 8, 9

T42’: All Non-Test Inputs Setup Time 27.5 ns 11 6, 8, 9

T43’: All Non-Test Inputs Setup Time 5.5 ns 11 5, 8, 9

T44’: All Non-Test Inputs Hold Time 14.5 ns 11 5, 8, 9

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

32 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. All AC t imi ngs for the TAP signal s ar e referen ced to th e TCK r ising edge at 0. 7 V a t t he pr ocessor ed ge fin gers. A ll

TAP signal timings (TMS, TDI, et c.) are refer enced at 1.25 V at the processor edg e fingers.

3. Not 100% tested. Specified by design characterization.

4. 1 ns can be added to the maximum TCK rise and fall time s fo r every 1 MHz below 16. 667 MHz.

5. Referenced to TCK rising edge.

6. Referenced to TCK falling edge.

7. Valid delay timing for this signal is specified to 2.5 V +5%. See Table 2 for pull-up resistor values.

8. Non- Test Output s and Input s are th e norma l ou tput or input sig nals ( beside s TC K, TRST #, TDI , TDO, an d TMS) . The se

ti mings correspond to th e response of these signals due to TAP operations.

9. During Debug Port ope ration, use the nor mal specified timings r ather than the TAP sig nal timings .

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. All A C timings for the TAP sig nals are refer enced to the TCK ris ing edge at 1.25 V at t he processor core pins. All TAP

signal t imings (T MS, TDI, etc.) are refer enced at 1.25 V at the pr oces s or core pins.

3. These speci f ications ar e tested during manufacturing, unless ot herwise no ted.

4. 1 ns can be added to the maximum TCK rise and fall time s fo r every 1 MHz below 16. 667 MHz.

5. Referenced to TCK rising edge.

6. Referenced to TCK falling edge.

7. Valid delay timing for this signal is specified to 2.5 V +5%. See Table 2 for pull-up resistor values.

8. Non- Test Output s and Input s are th e norma l ou tput or input sig nals ( beside s TC K, TRST #, TDI , TDO, an d TMS) . The se

ti mings correspond to th e response of these signals due to TAP operations.

9. During Debug Port ope ration, use the nor mal specified timings r ather than the TAP sig nal timings .

10. Not 100% tested. Specified by design characterization.

Table 20. System Bus AC Speci fications (TAP Connection)at the Processor Cor e Pins 1, 2, 3

T# Parameter Min Max Unit Fi

ure Notes

T30: TCK Frequency 16.667 MHz

T31: TCK Period 60.0 ns 6

T32: TCK High Time 25.0 ns 6 @1.7 V 10

T33: TCK Low Ti me 25.0 n s 6 @0.7 V 10

T34: TCK Rise T ime 5.0 ns 6 (0.7 V–1.7 V) 4, 10

T35: TCK Fall Time 5.0 ns 6 (1.7 V–0.7 V) 4, 10

T36: TRST# Pulse Width 40.0 ns 12 Asynchronous 10

T37 : TDI, TM S Se tup Time 5.0 ns 11 5

T38 : TDI, TM S H old Time 14.0 ns 11 5

T39: TDO Valid Del a y 1.0 10.0 ns 1 1 6, 7

T40: TDO Float Del ay 25.0 n s 11 6, 7, 10

T41: All Non-Test Outputs Valid Del ay 2.0 25.0 ns 11 6, 8, 9

T42: All Non-Test I nputs Setup Tim e 25.0 ns 11 6, 8, 9, 10

T43: All Non-Test I nputs Setup Tim e 5.0 ns 11 5, 8, 9

T44: All Non-Test Inpu ts Hold Time 13. 0 ns 11 5, 8, 9

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 33

Note: For Figur e 6 through Figure 12, the following apply:

1. Figure 6 through Figure 12 are to be used in conjunction with Table 9 through Table 20.

2. All AC timings for the AGTL+ signals at the proc essor edg e fingers are referenced to the

BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on

the proc es s or substrate, allowing the process or core to rec eive the si gnal with a re ferenc e a t

1.25 V. All AGTL+ signal timi ngs (address bus, data bus, etc .) are refe rence d at 1. 00 V at the

proce ssor e dge fingers.

3. All AC timings for the AGTL+ signals at the proc essor core pins are refe rence d to the BCLK

risi ng edge at 1.25 V. All GTL+ signal ti mi ngs (add res s bus, data bus, etc .) are ref erenced at

1.00 V at the proce ssor core p ins .

4. All AC timings for the CMOS signal s at the processor edge fingers are ref ere nced to the

BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on

the proc es s or substrate, allowing the process or core to rec eive the si gnal with a re ferenc e a t

1.25 V. All CMOS signal ti mings (compatibility signals, etc.) a re re ferenced at 1.25 V at the

proce ssor e dge fingers.

5. All AC timings for the APIC I/O signals at t he processor edge fingers are referenced to th e

PICCLK rising edge at 0.7 V. All APIC I/O sign al timings are r eferenced at 1. 25 V at the

proce ssor e dge fingers.

6. All AC timings for the TAP signals at the processor ed ge fingers are referenced to the TCK

risi ng edge at 0.70 V. All TAP signal timings (TMS, TDI, etc .) are referenced at 1.25 V a t the

proce ssor e dge fingers.

Figu re 5. BCLK t o Core Logic Offset

BCLK at

Edge Fingers

00080

0.5V

BCLK at

Core Logic 1.25V

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

34 Datasheet

Figure 6. BCLK, PICCLK, and TCK Generic Clock W aveform

Figure 7. System Bus Valid Delay Timings

Figure 8. System Bus Setup and Hold Timings

000761a

1.7V (2.0V*) 1.25V

0.7V (0.5V*)

CLK

= T5, pT25, T34 (Rise Time)

= T6, T26, T35 (Fall Time)

= T3, T23, T32 (High Time)

= T4, T24, T33 (Low Time)

= T1, T22, T31 (BLCK, TCK, PCICLK Period)

Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK and TCK are referenced to

0.7 V and 1.7 V

CLK

Signal

000762b

TxTx

Tpw

V Valid Valid

TxT7, T11, T29 (Valid Delay)

Tpw T14, T15 (Pulse Wdith)=

V1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups=

CLK

Signal

000763b

VValid

TsT8, T12, T27 (Setup Time)=

ThT9, T13, T28 (Hold Time)=

V1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups=

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 35

Figure 9. System Bus Reset an d Configuration Tim i ngs

Figure 10. Power-On Reset and Configuration T imings

Safe Valid

Valid

BCLK

RESET#

Configuration

(A20M#, IGNNE#,

LINT[1:0])

Configuration

(A[14:5]#, BR0#,

FLUSH#, INT#)

= T9 and T9' (GTL+ Input Hold Time)

= T8 and T8' (GTL+ Input Setup Time)

= T10 and T10' (RESET# Pulse Width)

= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)

= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)

T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)

Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)

Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)

PCD-764

BCLK

PWRGOOD

RESET#

V ,

REF

D0007-02

V ,

CCP,

IL,max

Confi

uration

(

A20M#, IGNNE#,

INTR, NMI

)

Valid Ratio

IH,min

= T15 and T15'

(

PWRGOOD Inactive Pulse Width

)

= T10 and T10'

(

RESET# Pulse Width

)

= T20

(

Reset Confi

uration Si

nals

(

A20M#, IGNNE#, LINT[1:0]

)

Hold Time

)

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

36 Datasheet

3.0 S

stem Bus Si

nal Simulations

Si gnals driven on the Pentium II processor system bus should meet signal quality specifications to

ens ure that the components read da ta properly and to ens ure that incoming signals do not af fect the

long term reliability of the component. Specific ations are provided for simulation at the processor

core; guidelines are provided for correlation to the processor edge fingers. The se edge finger

guidelines are intended for use during test ing and meas urement of system signal integrity.

Violations of these guideline s are permitted, but if they occur, simulation of signal quality at the

processor core should be performed to ensure that no violations of s ignal quality specific ations

occu r. Mee ti n g th e spec if i catio n s at th e p ro c esso r co re in Table 21, Tabl e 23, and Table 25 ensures

that si gnal quality effects will not adversely affect process or operation, but does not necessarily

guar an t ee th at th e gu id eli n es in Table 22, Table 24, and Table 26 will be met.

Figure 11. Te st T imings (TAP Co nnection)

Figur e 12. Test Reset Tim ings

TCK

DI, TM S

Input

Signals

TDO

Output

Signals

PCB766a

1.25V

TvTw

TrTs

TxTu

TyTz

1.25V

TrT43 (All Non-Test Inputs Setup Time)=

TsT44 (A ll Non -Test Inputs Hold Time)=

TuT40 (TDO Float De lay)=

TvT37 (TDI, TMS Se t up Ti me)=

TwT38 (TDI, TMS Hold Time)=

TxT39 (TDO Va lid De lay)=

TyT41 (A ll Non -Test Outputs Valid Delay)=

TzT42 (A ll Non -Test Outputs Float Delay)=

TRST#

PCB

773

1.25V

TqT37 (TR ST# Pulse Width)=

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 37

3.1 Syste m Bus Clock (BCLK) Signal Quality Specifications and

Measurement Guidelines

Table 21 describes t he s ignal qua lity specifica tions at the processor core for the Pentium II

processor syste m bus cl ock (BCLK) signa l. Table 22 describe s guidelines for si gnal quality

measur ement at the processor edge fingers. Figure 13 des cribe s the sign al quality wa veform for the

syste m bus clock at the proce ssor cor e pi ns. Figure 14 d escribe s the signal qual ity wav eform fo r the

syste m bus clock at the processor edge fingers.

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. This is the Pentium II processor syst em bus clock overshoot and undershoot sp ecification for 100-MHz system bus

operation.

3. The ri s ing and falling edge r ingba ck voltage specified is the mini mum (rising) or maximum (falling) absolute vol tage

the BCLK signal can dip back to after passing the VIH (rising) or VIL (fallin g ) volta ge lim its. This spe cific ation is an

absolute value.

Table 21. BCLK S ignal Quality Specifications for Simulation at the Processor Core 1

T# Parame ter Min Nom Max Unit Fi

ure Notes

V1: BCLK VIL 0.5 V 13

V2: BCLK VIH 2.0 V 13 2

V3: VIN Absolu te Volta ge Rang e –0 .7 3.3 V 13 2

V4 : R ising Edge Ringback 1.7 V 13 3

V5: Falling Edge Ringback 0.7 V 13 3

Figur e 13. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Cor e Pins

T6 T4 T5

Voltage

Time

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

38 Datasheet

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II process or fr e quencies and cache sizes.

2. This is the Pentium II processor system bus clock overshoot and undershoot measurement guideline.

3. The rising and fall ing edge r ingback voltage guideline is the minimum (r ising) or maxi mum (falling ) absolut e voltage

the BCLK sign al may dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This guideline is an

absolute value.

4. The BCLK at the proce s s or edge fi ngers may hav e a dip or ledge midway o n th e risi ng or falling edge. T he midpoint

voltage level of this ledge should be within the range of the guideline.

5. The ledge (V7’) is allowed to have peak-to-peak oscillation as given in the guideline.

3.2 AGTL+ Signal Qualit y Specifi cations and Measuremen t

Guidelines

Many scenarios have be en sim ulated to genera te a set of GTL+ layout guidelines which are

available in AP-827, 100 M Hz GTL+ Layout Guidelines for the Pentium® II Processor and Intel®

440BX AGPset (Order Number 243735). Refer to the Pentium® II Process or Developer' s Manua l

( Order Num ber 243502) for the GTL+ buffer speci f icat ion.

Table 22. BCLK Signal Quality Gu idelines fo r Edge F in ger Meas urem en t 1

T# Parameter Min Nom Max Unit Fi

ure Notes

V1’: BCLK VIL 0.5 V 14

V2’: BCLK VIH 2.0 V 14

V3’: VIN Absolute Voltage Ran ge –0.5 3.3 V 14 2

V4’: Rising Edge Ringback 2.0 V 14 3

V5’: Fal li ng Edge Rin gback 0.5 V 14 3

V6’: Tline Ledg e Voltage 1.0 1.7 V 14 At L edge Midpoint 4

V7’: Tline Ledge Oscillation 0.2 V 14 Peak-to-Peak 5

Figure 14. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers

000808

T6 T4 T5

Time

Voltage

’

’’’

’

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 39

Table 23 provides the AGTL+ si gnal quality sp ecifications for Pentium II proces sors for use in

simulating si gnal quality at the processor core. Table 24 provides AGTL+ signal quality guidelines

for measuring and testing si gnal quality at the processor edge fingers. Figure 15 describes the

sign al quali ty wav eform for AGTL+ signals at the proce ssor c ore and edge fingers. For mor e

in form ation on the AGTL + interface, see the Pentium® I I Processor Developer's Manual (Order

Number 243502).

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

2. Specificat ions are for t he edge rate of 0.3 - 0. 8 V /ns. See Figure 15 for the generic waveform.

3. All va lues specifi ed by des ign charact erizat ion.

4. This s pecification applies to Pentiu m II pr ocessors operating w ith a 100- MHz Penti um II proces sor syst em bus only.

5. Ringback below VREF + 20 mV is not supported.

6. Intel recommends performing simulations using an amplitude of -120 m V to allow margin for other sources of sy s tem

noise.

NOTES:

1. Unless otherwise noted, all guidelines in this table apply to all Pentium® II processor frequencies and cache sizes.

2. Guideli nes are fo r the edge rate of 0.3 - 0 .8 V/ns . See Figure 15 for the generic waveform.

3. All va lues specifi ed by des ign charact erizat ion.

4. Th is guid e lin e applie s to Pen tiu m II pro c es sors ope ra tin g with a 100 -MHz Pent iu m II p ro cesso r syste m bus only.

5. Ringback below VREF + 210 mV is not supported.

Table 23. AGTL+ Signal Groups Ringback Tolerance Specifica tions at the Processor Core 1, 2, 3

T# Parameter Min Unit Fi

ure Notes

α: Over s hoot 100 mV 15 4

τ: Minimum Time at High 0.50 ns 15 4

ρ: Am plitude of Ring back –20 mV 15 4, 5, 6

φ: Final Settling Voltage 20 mV 15 4

δ: Durat ion of Squarewave Ringback N/A ns 15

Table 24. AGTL+ Signal Groups Ringback Tolerance Guide lines for Edge Finger Measurement 1, 2, 3

T# Parameter Min Unit Fi

ure Notes

α’: Overshoot 100 mV 15

τ’: Min imu m Time at Hig h 0 .5 ns 15 4

ρ’: Amplitude of Ringback –210 mV 15 4,5

φ’: Final Settling Voltage 210 mV 15 4

δ’: Duration of Squarewave Ringback N/A ns 15

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

40 Datasheet

3.3 Non- AGTL+ Signal Qualit y Specif icatio ns and Measurement

Guidelines

The re are three s ignal qua lity parameters de fined for non-AGTL+ signals: over sh oot/undershoot,

r ingback, an d settling limit. All thre e s ignal quality parameters a re s hown in Figu re 16 for the non-

AGTL+ signal group.

Figure 15. Low to High AGTL+ Receiver Ringback Tolerance

Vstart

V +0.2

REF

VREF

V –0.2

REF

Time

000914a

Clock

Note: High to Low case is analogous.

δ0.7V Clk Ref

Figure 16. Non-AGTL+ Overshoot/U nde rshoot, Settling Limit, and Ringback

Undershoot

Overshoot Settling Limit

Settling Limit

Rising-Edge

Ringback Falling-Edge

Ringback

VLO

VSS Time

000767b

V =

HI VCC2.5

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 41

3.3.1 Overshoot/Undershoot Guidelines

Overshoot (or unders hoot) is the absolute value of the maxi mu m vol tage above the nominal high

volta ge or below VSS. The overs hoo t/under sh oot guidel in e limi ts tran siti ons beyo nd VCC or VSS due

to the fast signal edge rates. (See Figure 16 for non-AGTL+ signals.) T he processor can be

damaged by repeated overshoot events on 2.5 V tolerant buffers if the charge is large enough (i.e. ,

if the overshoot is great enough). However, excess ive ringback is the domina nt detrimental system

tim ing effect resulting from overs hoot/undershoot (i.e., vi olating the overshoot/undersh oot

guideline will ma ke s atisfying the ringback s pecification difficult). The ove rs h oot/undershoot

gu idel in e is 0. 7 V a nd assumes the absence of diodes on the input. These guidelines should be

ve r i f ied in s imu lati o n s without the on-c hip ESD protection diodes p resent because the diodes

will begin clamping the 2.5 V tolerant signals begi nning at approximately 0.7 V above the 2.5 V

supply and 0. 7 V below VSS. If signals ar e not reaching the clam ping voltage, this will n ot be an

issue. A system sho uld not rely on the diodes for over shoot/unders hoot pr otection as this will

negatively affect the li fe of the com ponents and m ake meeting the ringback specification very

difficult.

3.3.2 Ringback Specification

Ringbac k refers to the amount of reflection seen after a signal has swit ched. T he ringback

specific ation is the voltage that the signa l rings back to after ac hieving its m aximum absolu te

value. ( See Figure 16 for an il lus tration of ringback.) Excess ive ringbac k ca n cau se f alse signal

detec tion or extend the propagation delay. The ringbac k specification applie s to the input pin of

eac h rec eiving agent. Violations of the sign al ringback specification are not allowed under any

circ umstanc es for non-AGTL+ signals.

Ringback can be simul ated with or without the input pro tection diodes tha t can be added to the

input buffer model. However, signals that reach the clamping voltage should be evalua ted f urther.

See Table 25 for the signal ringbac k specifications for non-AGTL+ signals for simulations at the

proce ssor c ore, and Table 26 for guideline s on measuring ringback at the edge fingers.

NOTE:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

NOTE:

1. Unless otherwise noted, all specifications in this table apply to all Pentium® II processor frequencies and cache sizes.

Table 25. Signal Ringback Specifications for Non-AG TL+ Signal Simulation at the Processor Core 1

ut Si

nal G rou

Transition Maximum Rin

back

(with In

ut Diodes P resent) Unit Fi

ure

Non-AGTL+ Signals 0 → 11.7V16

Non-AGTL+ Signals 1 → 00.7V16

Table 26. Signal Ri ngback Guidelines for Non-AGTL+ Signal Edge Finger Measurement 1

ut Si

nal G rou

Transition Maximum Rin

back

(with In

ut Diodes Present) Unit Fi

ure

Non-AGTL+ Signals 0 → 1 2.0 V 16

Non-AGTL+ Signals 1 → 0 0.7 V 16

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

42 Datasheet

3.3.3 Settling Limit Guideline

Settling li mit defines the maximum amount of ringing at the receiving pin that a signal must rea ch

befor e i ts ne xt t ransi tion. The am ount a llo wed is 10% of the to tal sign al swi ng (VHI –VLO) above and

b elow its final value. A signal should be within the s ettling li mits of its final value, when eit h er in

its high state or low state , before it transitions again.

Signals that are not within their settling limit before transitioning are at risk of unwanted

osc illations which c ould j eopa rdize signal integrity. Simulations to verify settling limit ma y be

done either wit h or without the input pr otection diodes prese nt. Violation o f the s ettling li mi t

gu ideli ne is a ccept able if sim ulatio ns o f 5 to 10 suc cessi ve tr ansi tions do not show t he ampl itude of

the ringing incre asing in the subsequent transitions.

4.0 Thermal S

ecifications and Desi

n Considerations

I nitial Pentiu m II process o rs take advatange of S.E.C.C. package technology. This technology uses

an ex te nded the rmal pl ate for hea tsin k attac hment . The e xtende d th ermal plate int erface is in tended

to prov ide ac cessibli ty for multi ple type s of the rmal soluti ons. Follo w-on re leases of t he Pe ntium II

processor use S.E.C.C.2 packaging technology. This pakaging te chnology does n’t incorporat e an

ext ended th erm al pla te. Pr ocess ors whi ch use S.E.C. C.2 pa ckag ing te chno logy have eithe r a PL GA

or an OLGA process or core that is surface mounted onto the substra te. All three of these pac kage

variations require unique thermal measuring processe s. Thi s chap ter provides n eeded da ta for

des igning a therm al s olution. Howeve r, for the c orrect thermal m easuring proc es s es please refer to

AP-586, Pentium® II Processor Therm a l De sign Gui del ine s (Order Number 243331 ).

Figure 17 provides a side view of a n S .E .C.C. package. This figure provides the the r m al plate

location.

Figure 17. Pent ium® II Processor S.E.C.C. - Side View

Right Latch

Left Latch

Cover

Enhanced Thermal Plate

Extended Thermal Plat e

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 43

4.1 Thermal Specifications

Table 27 and Table 28 provide the ther mal design power dissipation and maximu m and mini mum

tem peratures for Pentium II processors with S. E.C. C. and S .E .C.C.2 packa ge technologies,

respectively. While the processor core dissipates the majority of the thermal power, thermal power

dissipated by the L2 cache also impac ts the overa ll processor power specification. Sys tems should

des ign for t he highest possible thermal power, e ven if a proce ssor wi th a lower thermal dissipat ion

is pla nned.

NOTES:

1. These v alues are specified at nomi nal VCCCORE for the processor core and nominal VCCL2 for the L2 cache.

2. Process or power in cludes the powe r dissipated by the processor c or e, the L2 cache, and the AGTL + bus t e rmination.

The maximu m power for each of the s e components does not occur simu ltaneously.

3. Extended Thermal Pl ate power is the processor power that is dissipa ted through the ext ended thermal plate.

4. These processors use the extended thermal plate for the Pentium® II processor (see Figure 17).

Ta b l e 28 . Therm al Sp ec if i ca t io n s for S.E.C.C.2 Pa ck a g e d Proc es s or s 1

NOTES:

1. These v alues are specified at nomi nal VCCCORE for the processor core and nominal VCCL2 for the L2 cache.

2. Process or power includes t he pow er dissipated by the proces s or core, the L2 cache, and the AGTL + bus t e r m inat ion.

The maximu m power for each of the s e components does not occur simu ltaneously.

For S.E.C.C. packaged processors , t h e extended therma l p late is the attach location for all thermal

solutions. T he m aximum and min imum extended thermal plate te mperatures are spec ified in Table

27. For S.E.C. C.2 pack aged processors, therm al sol utions attach to the processor by connecting

through the substrate to the cover . The maxi mum and minimum temper atures of the pertinent

locations are specified in Table 28. A the rmal s olution should be designe d to ensure the

temperature of the specified locations never exceeds these temperatures.

The t otal processor power is a res ult of heat dis si pation that is a com bination of heat from both the

processor core an d L2 cache. The overall system chassis thermal design must compreh end the

entire proc es sor power. In S.E.C. C. packa ged processors, the extended thermal plate power is a

comp onent of thi s power, and is c omposed of a combina tion of th e process or core a nd the L2 c ache

dissipating heat through the extended thermal plate. The heatsink need only be designed to

dissipat e th e exten ded the rmal plate pow er. See Table 2 7 fo r current Pen tium II processor thermal

des ign s pecificati ons.

Ta b l e 27 . Therm al Specifi ca t io n s fo r S .E .C . C . Pa ckaged Proc esso rs 1

Pr ocessor Cor e

Fre

uenc

(MHz)

L2 Cache

Size

(Kb

tes)

Processor

Power 2

(W)

Extended

Ther mal Plate

Power 3

(W)

Min

TPLATE

(°C)

Max

TPLATE

(°C)

Min

TCOVER

(°C)

Max

TCOVER

(°C)

450 4512 27.1 26.4 5 70 5 75

400 4512 24.3 23.6 5 75 5 75

350 4512 21.5 20.8 5 75 5 75

Processor

Core

Fre

uenc

(MHz)

L2 Cache

Size

(Kb

tes)

Pr ocessor

Power 2

(W)

Min

PLGA

TCASE

(°C)

Max

PLGA

TCASE

(°C)

Min

OLGA

TJUNC

(°C)

Max

OLGA

TJUNC

(°C)

L2 Cache

Min TCASE

(°C)

L2 Ca che

Max TCASE

(°C)

Min

TCOVER

(°C)

Max

TCOVER

(°C)

450 512 27.1 N/A N/A 5 90 5 105 5 75

400 512 24.3 N/A N/A 5 90 5 105 5 75

350 512 21.5 5 80 N/A N/A 5 105 5 75

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

44 Datasheet

For S.E.C.C.2 packaged processors, no extended thermal plate exists and thermal solutions need to

con ta c t th e co r e pa ck a g e di r ectl y and at ta ch th r o ug h th e s u b str a te to th e cover. T h e to t al pr o cesso r

power that must be diss ipated for S.E. C.C.2 proc essors can be thought of just as it is for S.E.C. C.

package d processors: a combination o f both the processor core and L2 cache. In rega rds to the

core, thermal specifications depe nd on the packaging technology used. Pentium II processors in

S. E. C.C.2 util izing PLGA core packa g ing t echnology have a case te mp er a tu r e s p ec if i ed . Pent i um

I I process ors in S.E.C. C.2 uti li zing OL GA core pac kaging techno logy have a junction tem pe rat u re

spe cified. Specifics on how to meas ure these two parama ters a r e outlined in AP-586, Pentium® II

Processor Ther mal Design Guidelines (Order Number 243331). In addition, the re are surface

mounted SRAM components for the L2 Cach e on the substrate tha t have a separate TCASE

specification in Table 28.

4.1.1 Thermal Diode

The Pentium II proc es sor incorporates an on-die diode that must be used to monitor the die

t emperature (junction temperature). A thermal s ensor located on t h e mother board, or a stand-al o n e

meas urement kit, may monitor the die temperature of the Pe ntium II proc essor for thermal

management or instrumentation purposes.Table 29 and Ta ble 30 provide the diode parameter and

interface specifications.

NOTES:

1. Not 100% tested. Specified by design characterization.

2. In tel do es not support or recommend ope r a tion of t he thermal diode under reverse bias.

3. At room temperature with a forwar d b ias of 63 0 mV.

4. n_ideality is the diode ideality factor parameter, as represented by the diode equation:

I-Io(e (Vd*q)/(nkT) - 1).

5.0 S.E.C.C. and S.E.C.C.2 Mechanical S

ecifications

Pentium II processors use either S.E. C.C. or S.E.C.C.2 package technology. Both package types

contain the processor c ore, L2 cache, and other passive components. The cartridges connect to the

motherboard through an edge connector. Mechanic al specifications for the proc essor are given in

th is section. See Section 1.1.1 for a complete te rminology listing.

Table 29. Thermal Diode Parameters1

mbol Min T

Max Unit Notes

Iforwa r d bias 5500uA2

n_ideality 1.0000 1.0065 1.0173 3,4

Table 30. Thermal Diode Interface

Pin Name SC 242 C onnector Si

nal # Pin Des cri

tion

THER MD P B14 diode anode

THERMDN B15 diode cathode

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 45

5.1 S.E. C .C. Mechnical Specifications

S.E.C.C. pa ckage dra w ings and dim ens ion d etails are pro vided in Figure 18 throu gh F igure 27.

Figure 18 shows all views of the Pentium II proc essor in an S.E.C.C. package; Figure 19 through

Figure 22 show the S.E. C.C. package dimensions; Figure 23 and Figure 24 show the extended

therma l plate dim ensions ; and Figure 25 and Figu re 26 provide details of th e processor su bstrate

edge finger contacts. Figure 27 and Table 31 contain process or marking informati on.

The processor ed ge connec tor defined in this docu me nt is referred to as the “SC 242 connector.”

See the Slot 1 Connector Spec ification (Order Number 243397) for further details on the SC 242

connector.

Note: For Figur e 18 through Figure 35, the following apply:

1. Unl es s otherwise specified, the f o llowing drawings are dimensioned in inches .

2. All dimensions provided with tolerances are guaranteed to be met for all norm al produc tion

product.

3. Fig ures and drawings labeled a s “Ref erence Dimensions” are pr ovided for informat ional

pur pos es only. R eference Dimensions are extrac ted from t he mechani cal design databa s e and

are nominal dimensions with no tolerance inform ation applied. Ref erence Dimens ions are

NOT checked as part of the processor manufa cturing. Dimensi ons in pare ntheses without

tole ranc es are Reference Dimensions.

4. Drawings are not to scale.

Figure 18. Pentium® II Processor (S.E.C.C. Package)—Top and Side View

Left Right Right

Side LeftRight Thermal Plate

Side View

Cover Side view

Top View

Left Latch Right Latch

Cover Thermal

Plate

v006a.vsd

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

46 Datasheet

Figure 19. Pent ium® II Processor (S.E .C.C. Package)—Extended Thermal Plate Side Dimensions

Figure 20. Pent ium® II Processo r (S.E.C.C. Package )—Bottom V iew Dimensions

v005a

2.473±.016

2.070±.020

1.235±.020

These dimensions are from the bottom

of the substrate ed

e fin

ers

2X .365±.005 1.745±.005 1.877±.020

2X .342±.005

2X .125±.005

3.805±.020

v007

5.505±.010

5.341±.010

3.243±.0152.181±.015

Thermal Plate

5.255±.006

Cover

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 47

Figure 21. Pentium® II Proc esso r (S .E .C .C. Pa ck a ge)— L a tch A rm , Ex t e n ded Therm al Pla te Lug , an d

Cover Lug Dime nsions

001056a

2X 0.174 ±0.005

2X 0.488

±0.020

2X 0.238

2X 0.103 ± 0.005

2X 0.647

±0.020

2X 0.253

2X 0.058

±0.005 2X 0.136

±0.005

Left

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

48 Datasheet

Figure 22. Pent ium® II P r oc ess or ( S.E. C. C. P ack ag e)—L at c h Arm, Extend ed T herm al P la t e, a nd Cove r

Detail Dimensions (Reference Dimensions Only)

0.236

0.113

Detail A Detail B

(Bottom Side View)

0.084

0.122

0.075

Detail C Detail D Detail E

001057a

Note: All dimensions without tolerance information

are considered reference dimensions only

0.120 Min.

0.082

0.316 0.116

0.291

45°

0.276

0.216

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 49

Figure 23. Pentium® II Processor (S.E.C.C. Package)—Extended Thermal Plate At tachm ent Detail

Dimensions

Detail A

6X 0. 124 +0.001

–0.002

8X R 0.0 625 ± 0 .002

4X 0. 365

±0.005

See Detail A

2.11 0 ± 0 .0080.00 0

0.97 8 ± 0 .008

0.50 0 ± 0 .008

0.25 0 ± 0 .008

0.000

0.37 5 ± 0 .008

001051

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

50 Datasheet

Figure 24. Pent ium® II Processo r (S.E.C.C. Package )—Extended Thermal Plate Attachmen t Deta il

Dimensions, Continued

Figure 25. Pent ium® II Processor Substrate (S.E.C.C. Package)—Edge Finger Contact Dimensions

v008

2.500

1.250

0.0032 / 1.000 x 1.000

.062 +.007

-.005

.045 70°

2.01 ±.0082.992 ±.008

2.835 1.85

5.000

NOTE:

All dimensions without tolerance information are

considered reference dimensions only.

See Detail A in

Next Figure

Substrate

Cover

Thermal Plate

Pin A121

Pin A1

007.vsd

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 51

Figure 26. Pentium® II Processor Substrate (S.E.C.C. Package)—Edge Finger Contact Dimensions,

Detail A

Figure 27. Pentium® II Processor Markings (S.E.C.C. Package)

.098

.039

.037

.074 ±.002

.236

.045

121 X 0.043 ±.002

.138 ±.005

.008

.360

.010

121 X 0.16 ±.002

Pin A73 Pin A74

NOTE:

1. All dimensions without tolerance information are considered reference dimensions only.

2. Z reference datum shown in Figure 35

.008 Z W

.002 Z

.008 Z W

.002 Z

010.vsd

SZNNN/XYZ ORDER CODE

XXXXXXXX-NNNN

2-D Matrix Mark

Hologram

Location

pentium

P R O C E S S O R

'94 '96

Dynamic Mark Area

pentium

®II

P R O C E S S O R

pentium

®II

P R O C E S S O R See Note

NOTE:

Please refer to the Pentium® II

Pr ocess or Specifica tion Update

for this information.

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

52 Datasheet

5.2 S.E .C.C.2 Mechanical Specifi cation

S. E. C.C.2 package d drawings and dimens ion de tails are provi ded in Figure 28 through Figure 35 .

Figure 28 shows all views of the P entium II processor in an S.E.C.C.2 package using an OLGA

p ackaged p rocessor core; Figure 29 shows all views of a Pentium II processor in an S.E.C.C.2

package using a PLGA packaged processor core; Figure 30 through Figure 34 show the S. E.C.C.2

package dimensions ; Figure 35 provides dimensi ons of the processor substrate edge fing er

contacts; an d Figure 36 and Table 32 contain processor marking information.

Tabl e 3 1 . De script ion Table for Processor Markings (S.E.C.C . Packaged P rocessor)

Code Letter Descri

tion

ALogo

BProduct Name

C Trademark

DLogo

EProduct Name

F Dynamic Mark Are a – with 2-D matrix

Figure 28. Pent ium® II Processor (S.E.C.C.2 Package) Top and Side Views—OLGA Processor Core

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 53

Figure 29. Pentium® II Processor (S.E.C.C.2 Package) Top and Side Views—PLGA Processor Core

Figure 30. Pentium® II Proces sor A sse mbly (S.E. C .C. 2 Pac ka ge) — Pri m ary View

PLGA

OLGA

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

54 Datasheet

Figure 31. Pent ium® II Processor Assembly (S.E.C.C.2 Package)—Cover Vi ew with Dimensions

Figure 32. Pent ium® II Processor Assembly (S.E.C.C.2 Package)—Heat Sink Attach Boss Section

PLGA

OLGA

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 55

Figure 33. Pentium® II Processor Assembly ( S.E.C.C.2 Package), Side View—OLGA Substrate Shown

Figur e 34. Detail View of Cove r in th e Vicinity of the Su bstrate Attach Featu res

PLGA

OLGA

See Figure 40

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

56 Datasheet

Figure 35. Pent ium® II Processor Substrate (S.E.C.C.2 Package), Edge Finger Contact Dimensions

Figure 36. Pent ium® II Processor Markin gs (S.E.C.C.2 Package)

OLGA

Package

iCOMP® 2.0 index=YYY

SZNNN/XYZ ORDER CODE

XXXXXXXX-NNNN

2-D Matrix Mark

Dyn ami c Mark Are a

Hologram

Location

pentium®

P R O C E S S O R

See Note

NOTE:

Please refer to the Pentium® II

Processor Specificatio n Update

for this information.

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 57

Table 32. Des cription Table for Process or M arkings (S.E.C.C.2 Packaged Processor)

5.3 Proc essor Pack age Materials Inform ation

Both the the S.E.C .C. and S.E. C.C.2 proc essor cartri dge s are compri sed of multi ple pieces to make

the complete assembl y. This section provides information r elevant to the use and ac ceptance of the

package. Ta ble 33 and Section 34 contain piec e-part information of the S.E.C.C. and S.E.C.C.2

processor packages, respectively.

NOTE:

1. Unless otherw ise n oted, t hese specifications apply to all S.E.C.C . packaged Pen tium® II pr ocessor frequencie s and

cac he sizes.

Table 34. S.E.C.C.2 Materials 1

NOTE:

1. Unless otherwise n oted, these specifications apply to all S.E.C.C.2 packaged Pentium® II processor frequencies and

cac he sizes.

Code Letter Descri

tion

ALogo

B Product Name

C Trademark

DLogo

E Product Name

F Dynamic Mar k Area – with 2-D matri x

Table 33. S.E.C.C. Mate rials 1

S.E.C.C. Piece Piec e Material Maximum Piece Wei

ht (Grams)

Extended Thermal Plate Aluminum 6063-T6 84.0

Latch Arms GE Lexan 940-V0, 30% glass filled Less than 2.0 per latch arm

Cover GE Lexan 940-V0 24.0

Total Pentium® II Processor 150

S.E .C.C.2 Piece Pi e ce Material M aximum Piece Wei

ht (Grams)

Cover GE Lexan 940-V0 18.0

Total Pen tium ® II Pro cessor 57.0

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

58 Datasheet

5.4 Pentium® II Processor Signal Listing

Table 35 and Table 36 provide the processor edge finger and Pentium II processor connector si gnal

definitions for Pentium II pr ocessors. The signal locations on th e SC 242 edge conne ctor are to be

use d for si gnal routing, si mulation, an d component placement on the motherboard.

Table 35 is the Pentium II processor substrate edge finger listing i n or der by pin numb er.

Tabl e 35. Signal Listing in Orde r by Pin Number ( She et 1 of 4)

Pin No. Pin Name Si

nal Buffer T

e Pin No. Pin Name Si

nal Buffer T

A1 VCC_VTT AGTL+ VTT Supply B1 EMI EMI Management

A2 GND VSS B2 FLUSH# CMOS Input

A3 VCC_VTT AGTL+ VTT Supply B3 SMI# CMOS Input

A4 IERR# CMOS Output B4 INIT# CMOS Input

A5 A20 M# C MOS Input B5 VCC_VTT AGTL+ VTT Supp l y

A6 GND VSS B6 STPCLK# CMOS Input

A7 FERR# CMOS Output B7 TCK JTAG Input

A8 IGNNE# CMOS Inp ut B8 SLP# CMOS Input

A9 T DI JTAG Input B9 VCC_VTT AGTL+ VTT Supp ly

A10 GND VSS B10 TMS JTAG Input

A11 TDO JTAG Output B11 TRST# JTAG Input

A12 PWRGOOD CMOS Input B12 Reserved Reserved for Future Use

A13 TESTHI CMOS T est Input B13 VCC_CORE Processo r core VCC

A14 GND VSS B14 THERMDP Diode Anode

A15 THERMTRIP# CMOS Output B15 THERMDN Diode Cathode

A16 Reserved Re served for Future Use B16 LINT[1]/NMI CMOS Input

A17 LINT[0]/INTR CMOS Inp ut B17 VCC_CORE Processor core VCC

A18 GND VSS B18 PICCLK APIC Clock Input

A19 P ICD[0] C MOS I/O B19 BP#[2] AGTL + I/O

A20 PREQ# CMOS Input B20 Rese rved Reserv ed for Futu re Use

A21 BP#[3] AG TL + I /O B21 1 00/66# BCLK F requency S elect

A22 GND VSS B22 PICD[1] CMOS I/O

A23 BPM# [0] AGTL+ I/O B23 PRDY# AGTL+ Output

A24 BINIT# AGTL+ I/O B24 BPM#[1] AGTL+ I/O

A25 DEP#[0] AGTL+ I/O B25 VCC_CORE Processor core VCC

A26 GND VSS B26 D EP#[2 ] AGTL+ I/O

A27 DEP#[1] AGTL+ I/O B27 DEP#[4] AGTL+ I/O

A28 DEP#[3] AGTL+ I/O B28 DEP#[7] AGTL+ I/O

A29 DEP#[5] AGTL+ I/O B29 VCC_CORE Processor core VCC

A30 GND VSS B30 D#[ 62] AGTL + I/O

A31 DEP#[6] AGTL+ I/O B31 D#[5 8] AGTL+ I/O

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 59

A32 D#[61] AGTL+ I/O B32 D#[63] AGTL+ I/O

A33 D#[55] AGTL+ I/O B33 VCC _CORE P rocessor core VCC

A34 GND VSS B34 D#[56] AGTL+ I/O

A35 D#[60] AGTL+ I/O B35 D#[50] AGTL+ I/O

A36 D#[53] AGTL+ I/O B36 D#[54] AGTL+ I/O

A37 D#[57] AGTL+ I/O B37 VCC _CORE P rocessor core VCC

A38 GND VSS B38 D#[59] AGTL+ I/O

A39 D#[46] AGTL+ I/O B39 D#[48] AGTL+ I/O

A40 D#[49] AGTL+ I/O B40 D#[52] AGTL+ I/O

A41 D#[51] AGTL+ I/O B41 EMI EMI Management

A42 GND VSS B42 D#[41] AGTL+ I/O

A43 D#[42] AGTL+ I/O B43 D#[47] AGTL+ I/O

A44 D#[45] AGTL+ I/O B44 D#[44] AGTL+ I/O

A45 D#[39] AGTL+ I/O B45 VCC _CORE P rocessor core VCC

A46 GND VSS B46 D#[36] AGTL+ I/O

A47 Reserved Rese rved for Future Use B47 D#[40 ] AGTL+ I/O

A48 D#[43] AGTL+ I/O B48 D#[34] AGTL+ I/O

A49 D#[37] AGTL+ I/O B49 VCC _CORE P rocessor core VCC

A50 GND VSS B50 D#[38] AGTL+ I/O

A51 D#[33] AGTL+ I/O B51 D#[32] AGTL+ I/O

A52 D#[35] AGTL+ I/O B52 D#[28] AGTL+ I/O

A53 D#[31] AGTL+ I/O B53 VCC _CORE P rocessor core VCC

A54 GND VSS B54 D#[29] AGTL+ I/O

A55 D#[30] AGTL+ I/O B55 D#[26] AGTL+ I/O

A56 D#[27] AGTL+ I/O B56 D#[25] AGTL+ I/O

A57 D#[24] AGTL+ I/O B57 VCC _CORE P rocessor core VCC

A58 GND VSS B58 D#[22] AGTL+ I/O

A59 D#[23] AGTL+ I/O B59 D#[19] AGTL+ I/O

A60 D#[21] AGTL+ I/O B60 D#[18] AGTL+ I/O

A61 D#[16] AGTL+ I/O B61 EMI EMI Management

A62 GND VSS B62 D#[20] AGTL+ I/O

A63 D#[13] AGTL+ I/O B63 D#[17] AGTL+ I/O

A64 D#[11] AGTL+ I/O B64 D#[15] AGTL+ I/O

A65 D#[10] AGTL+ I/O B65 VCC _CORE P rocessor core VCC

A66 GND VSS B66 D#[12] AGTL+ I/O

A67 D#[14] AGTL+ I/O B67 D#[7] AGTL+ I/O

A68 D#[9] AGTL+ I/O B68 D# [6] AGTL+ I/O

A69 D#[8] AGTL+ I/O B69 VCC_CORE P rocessor core VCC

Table 35 . S ignal List ing in Order b y P i n Num b e r ( S h e e t 2 of 4)

Pin No. Pin Name Si

nal Buffer T

e Pin No. Pin Name Si

nal Buffer T

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

60 Datasheet

A70 GND VSS B70 D#[ 4] AGTL+ I/O

A71 D#[5] AGTL+ I/O B71 D# [2] AGTL+ I/O

A72 D#[3] AGTL+ I/O B72 D# [0] AGTL+ I/O

A73 D#[1] AGTL+ I/O B73 VCC_CORE Processor c ore VCC

A74 GND VSS B74 R ES ET # A GTL + Inpu t

A75 BCLK Proc essor Clock Input B75 BR1# AGTL+ Input

A76 BR0# AGTL+ I/O B76 Rese rved Reserved for Futu re Use.

A77 BERR# AGTL+ I/O B77 VCC_CORE Processor core VCC

A78 GND VSS B78 A#[ 35] AGTL + I/O

A79 A#[33] AGTL+ I/O B79 A#[32] AGTL+ I/O

A80 A#[34] AGTL+ I/O B80 A#[29] AGTL+ I/O

A81 A #[30 ] AGTL+ I/O B81 EMI EMI Management

A82 GND VSS B82 A#[ 26] AGTL + I/O

A83 A#[31] AGTL+ I/O B83 A#[24] AGTL+ I/O

A84 A#[27] AGTL+ I/O B84 A#[28] AGTL+ I/O

A85 A#[22] AGTL+ I/O B85 VCC_CORE Processor c ore VCC

A86 GND VSS B86 A#[ 20] AGTL + I/O

A87 A#[23] AGTL+ I/O B87 A#[21] AGTL+ I/O

A88 R eserve d R eserve d for Future Use B88 A#[25] AGTL+ I/O

A89 A#[19] AGTL+ I/O B89 VCC_CORE Processor c ore VCC

A90 GND VSS B90 A#[ 15] AGTL + I/O

A91 A#[18] AGTL+ I/O B91 A#[17] AGTL+ I/O

A92 A#[16] AGTL+ I/O B92 A#[11] AGTL+ I/O

A93 A#[13] AGTL+ I/O B93 VCC_CORE Processor c ore VCC

A94 GND VSS B94 A#[ 12] AGTL + I/O

A95 A#[14] AGTL+ I/O B95 A#[8] AGT L+ I/O

A96 A#[10] AGTL+ I/O B96 A#[7] AGT L+ I/O

A97 A#[5] AGTL+ I/O B97 VCC_CORE Processor c ore VCC

A98 GND VSS B98 A#[ 3] AGTL+ I/O

A99 A#[9] AGTL+ I/O B99 A# [6] AGTL+ I/O

A100 A#[4] AGTL+ I/O B100 EMI EMI Management

A101 BNR# AG TL + I/O B10 1 SLOTOCC# SC 2 42 O ccupied

A102 GND VSS B102 REQ#[0 ] AGTL + I/O

A103 BPRI# AGTL+ I nput B103 REQ#[1] AGTL+ I/O

A104 TRDY# AGTL+ Input B104 REQ#[4] AGTL+ I/O

A105 DEFER# AGTL+ Input B105 VCC_CORE Processor c ore VCC

A106 GND VSS B106 LOCK# AGTL + I/O

A107 REQ#[2] AGTL+ I/O B107 DRDY# AGTL+ I/O

Tabl e 35. Signal Listing in Orde r by Pin Number ( She et 3 of 4)

Pin No. Pin Name Si

nal Buffer T

e Pin No. Pin Name Si

nal Buffer T

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 61

Table 36 is the Pentium II proc es sor substrate edge connect or listing in order by signal name.

A108 REQ#[3 ] AGTL+ I/O B108 RS#[ 0] AGTL+ Input

A109 HITM# AGTL+ I/O B10 9 VCC5 Othe r VCC

A110 GND VSS B11 0 HIT# AGTL+ I/O

A111 DBSY# AGTL+ I/O B111 RS#[2] AGTL+ Input

A112 RS#[1] AGTL+ Input B112 Reserved Reserve d for Future Use

A113 Reserved Rese rved for Fu ture Use B113 VCC_L2 Other VCC

A114 GND VSS B114 RP# AGTL+ I/O

A11 5 ADS# AGTL+ I/O B115 RS P# AGTL+ Input

A116 Reserved Reserved for Future Use B11 6 AP#[1] AGTL+ I/O

A11 7 AP#[0] AGTL+ I/O B117 VCC_L 2 Oth er VCC

A118 GND VSS B11 8 AERR# AGTL+ I/O

A119 VID [2] Voltage Identi f ication B119 VID[3] Voltage Identific ation

A1 20 VID[1] Voltage Identi f ication B120 VID[0] Voltag e Id entificati on

A121 VID[4] Voltage Identification B121 VCC_L2 Other VCC

Table 35 . S ignal List ing in Order b y P i n Num b e r ( S h e e t 4 of 4)

Pin No. Pin Name Si

nal Buffer T

e Pin No. Pin Name Si

nal Buffer T

Table 36 . S ignal List ing in Order b y S ignal Na me ( S h e e t 1 of 4)

Pin No. Pin Name Si

nal Buffer T

e Pin No. Pin Name Si

nal Buffe r T

B21 100/6 6# BCLK Fr equency Select A29 DE P#[ 5] AGTL+ I/O

B98 A#[3] AGTL+ I/O A31 DEP#[6] AGTL+ I/O

A100 A#[4] AGTL+ I/O B28 DEP#[7] AGTL+ I/O

A97 A#[5] AGTL+ I/O B107 DRDY# AGTL+ I/O

B99 A#[6] AGTL+ I/O B1 EMI EMI Management

B96 A#[7] AGTL+ I/O B41 EMI EMI Man agement

B95 A#[8] AGTL+ I/O B61 EMI EMI Man agement

A99 A#[9] AGTL+ I/O B81 EMI EMI Management

A96 A#[10] AGTL+ I/O B100 EMI EMI Management

B92 A#[1 1] AGTL+ I/O A7 FERR# CMOS Output

B94 A#[12] AGTL+ I/O B2 FLUS H# CMOS Input

A93 A#[13] AGTL+ I/O B76 Reserved Reserved for Future Use

A95 A#[14] AGTL+ I/O A2 GND VSS

B90 A#[15 ] AGTL+ I/O A6 GND VSS

A92 A#[16] AGTL+ I/O A10 GND VSS

B91 A#[17 ] AGTL+ I/O A14 GND VSS

A91 A#[18] AGTL+ I/O A18 GND VSS

A89 A#[19] AGTL+ I/O A22 GND VSS

B86 A#[20 ] AGTL+ I/O A26 GND VSS

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

62 Datasheet

B87 A#[21] AGTL+ I/O A30 GND VSS

A85 A#[22] AGTL+ I/O A34 GND VSS

A87 A#[23] AGTL+ I/O A38 GND VSS

B83 A#[24] AGTL+ I/O A42 GND VSS

B88 A#[25] AGTL+ I/O A46 GND VSS

B82 A#[26] AGTL+ I/O A50 GND VSS

A84 A#[27] AGTL+ I/O A54 GND VSS

B84 A#[28] AGTL+ I/O A58 GND VSS

B80 A#[29] AGTL+ I/O A62 GND VSS

A81 A#[30] AGTL+ I/O A66 GND VSS

A83 A#[31] AGTL+ I/O A70 GND VSS

B79 A#[32] AGTL+ I/O A74 GND VSS

A79 A#[33] AGTL+ I/O A78 GND VSS

A80 A#[34] AGTL+ I/O A82 GND VSS

B78 A#[35] AGTL+ I/O A86 GND VSS

A5 A20M# CM OS Input A90 GND VSS

A11 5 ADS# AGTL+ I/O A94 GND VSS

B118 AERR# AGTL+ I/O A98 GND VSS

A11 7 AP#[0] AGTL+ I/O A102 GND VSS

B116 AP#[1] AGTL+ I/O A106 GND VSS

A75 BCLK Processor Clock Input A110 GND VSS

A77 BERR# AGTL+ I/O A114 GND VSS

A24 BINIT# AGTL+ I/O A118 GND VSS

A101 BNR# AGTL+ I/O B110 HIT# AGTL+ I/O

B19 BP#[2] AGTL+ I/O A109 HITM# AGTL+ I/O

A21 BP#[3] AGTL+ I/O A4 IER R# CMOS Output

A23 BPM#[0] AGTL+ I/O A8 IGNNE# CMOS Input

B24 BPM#[1] AGTL+ I/O B4 INIT# CMOS Input

A103 BPRI# AGTL+ Input A17 LINT[0]/INTR CMOS Input

A76 BR0# AGTL+ I/O B16 LINT[1]/NMI CMOS Input

B75 BR1# AGTL+ Input B106 LOCK# AGTL+ I/O

B72 D#[0] AGTL+ I/O B18 PICCLK APIC Clock Input

A73 D#[1] AGTL+ I/O A19 PICD[0] CMOS I/O

B71 D#[2] AGTL+ I/O B22 PICD[1] CMOS I/O

A72 D#[3] AGT L+ I/O B23 PRDY# AGTL+ Output

B70 D#[4] AGTL+ I/O A20 PREQ# CMOS Input

A71 D#[5] AGTL+ I/O A12 PWRGOOD CMOS Inpu t

B68 D#[6] AGT L+ I /O B102 RE Q #[0] AGTL + I/O

Tabl e 36. Signal Listing in Orde r by Si gn al Name (She et 2 of 4)

Pin No. P in Name S i

nal Buffer T

e Pin No. Pin Name Si

nal Buffer T

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 63

B67 D#[7] AGTL+ I/O B103 REQ#[1] AGTL+ I/O

A69 D#[8] AGTL+ I/O A107 REQ#[2] AGTL+ I/O

A68 D#[9] AGTL+ I/O A108 REQ#[3] AGTL+ I/O

A65 D#[10] AGTL+ I/O B104 REQ#[4] AGTL+ I/O

A64 D#[11] AGTL+ I/O A16 Reserved Reserved for Future Use

B66 D#[12] AGTL+ I/O A47 Reserved Reserved for Future Use

A63 D#[13] AGTL+ I/O A88 Reserved Reserved for Future Use

A6 7 D#[14] AGTL+ I/O A113 Reser ved Reserved for Futur e Use

B64 D#[ 15] AGTL + I/O A116 Reserved Reserved for Fut ure Use

A61 D#[16] AGTL+ I/O B12 Reserved Reserved for Future Use

B63 D#[17] AGTL+ I/O B14 THER MD P Diode Anode

B60 D#[18] AGTL+ I/O B15 THER MD N Diode Cathode

B59 D#[19] AGTL+ I/O B20 Reserved Reserved for Future Use

B62 D#[20] AGTL+ I/O B11 2 Reserved Reserve d for Future Use

A60 D#[21] AGTL+ I/O B74 RESET# AGTL+ Input

B58 D#[22] AGTL+ I/O B114 RP# AGTL+ I/O

A59 D#[23] AGTL+ I/O B108 RS# [0] AGTL+ Input

A57 D#[24] AGTL+ I/O A112 RS#[1] AGTL+ Input

B56 D#[25] AGTL+ I/O B111 RS#[2] AGTL+ Input

B55 D#[26] AGTL+ I/O B11 5 RSP# AGTL+ Input

A56 D#[27] AGTL+ I/O B101 SL OTO CC# SC 242 Occupied

B52 D#[28] AGTL+ I/O B8 SLP# CMOS Input

B54 D#[29] AGTL+ I/O B3 SMI# CMOS Input

A55 D#[30] AGTL+ I/O B6 STPCLK# CMOS Input

A53 D#[31] AGTL+ I/O B7 TCK JTAG Input

B51 D#[32 ] AGTL+ I/O A9 TDI JTAG Input

A51 D#[33] AGTL+ I/O A11 TDO JTAG Output

B48 D#[34 ] AGTL+ I/O A13 TESTHI CMOS Test Input

A52 D#[35] AGTL+ I/O A15 T H ER MTRIP# CMOS Output

B46 D#[36] AGTL+ I/O B10 TMS JTAG Input

A49 D#[37] AGTL+ I/O A104 TRDY# AGTL+ Input

B50 D#[38] AGTL+ I/O B11 TRST# JTAG Input

A45 D#[39 ] AGTL+ I/O B13 VCC_CORE Processor core VCC

B47 D#[40] AGTL+ I/O B17 VCC_CORE Processor core VCC

B42 D#[41] AGTL+ I/O B25 VCC_CORE Processor core VCC

A43 D#[42 ] AGTL+ I/O B29 VCC_CORE Processor core VCC

A48 D#[43 ] AGTL+ I/O B33 VCC_CORE Processor core VCC

B44 D#[44] AGTL+ I/O B37 VCC_CORE Processor core VCC

Table 36 . S ignal List ing in Order b y S ignal Na me ( S h e e t 3 of 4)

Pin No. Pin Name Si

nal Buffer T

e Pin No. Pin Name Si

nal Buffe r T

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

64 Datasheet

6.0 Boxed Proce sso r S

ecifications

6.1 Introduction

The Pentium II processor is also offered as an Intel boxed processor. Intel boxed processors are

intended for system integra tors who build systems from motherboards and components. Boxed

Pentium II proc es sors are supplied wit h an attache d fan heatsink. This section documents

motherboard and sy st em requirements for the f an he atsink that will be s upplied with the boxed

Pentium II proc es sor. This section is pa rticularly imp ortant for OEM's tha t manufacture

motherboards for syste m integrators. Unless otherwise noted, all figures i n this section are

dimensioned in inches. Fig ure 37 shows a mechanic al repre sent ation of a box ed Pent ium II

A44 D#[45] AGTL+ I/O B45 VCC_CORE Processor core VCC

A39 D#[46] AGTL+ I/O B49 VCC_CORE Processor core VCC

B43 D#[4 7] AGTL+ I/O B53 VCC_CORE Processor core VCC

B39 D#[4 8] AGTL+ I/O B57 VCC_CORE Processor core VCC

A40 D#[49] AGTL+ I/O B65 VCC_CORE Processor core VCC

B35 D#[5 0] AGTL+ I/O B69 VCC_CORE Processor core VCC

A41 D#[51] AGTL+ I/O B73 VCC_CORE Processor core VCC

B40 D#[5 2] AGTL+ I/O B77 VCC_CORE Processor core VCC

A36 D#[53] AGTL+ I/O B85 VCC_CORE Processor core VCC

B36 D#[5 4] AGTL+ I/O B89 VCC_CORE Processor core VCC

A33 D#[55] AGTL+ I/O B93 VCC_CORE Processor core VCC

B34 D#[5 6] AGTL+ I/O B97 VCC_CORE Processor core VCC

A37 D#[57] AGTL+ I/O B105 VCC_CORE Processor core VCC

B31 D#[58] AGTL+ I/O B1 13 VCC_L2 Other VCC

B38 D#[59] AGTL+ I/O B1 17 VCC_L2 Other VCC

A35 D#[60] AGTL+ I/O B121 VCC_L2 Other VCC

A32 D#[61] AGTL+ I/O A1 VCC_VTT AGTL+ VTT Supp l y

B30 D#[62] AGTL+ I/O A3 VCC_VTT AGTL+ VTT Supp l y

B32 D#[63] AGTL+ I/O B5 VCC_VTT AGTL+ VTT Su pp l y

A111 DBSY# AGTL+ I/O B9 VCC_VTT AGTL+ VTT Supp ly

A105 DEFER# AGTL+ Inp ut B109 VCC5 Other VCC

A25 DEP#[0] AGTL+ I/O B120 VID[0] Voltage Identification

A27 DEP#[1] AGTL+ I/O A120 VID[1] Voltage Identification

B26 DEP#[2] AGTL+ I/O A1 19 VID[2] Voltage Identification

A28 DEP#[3] AGTL+ I/O B119 VID[3] Voltage Identification

B27 DEP#[4] AGTL+ I/O A121 VID[4] Volta ge Identification

Tabl e 36. Signal Listing in Orde r by Si gn al Name (She et 4 of 4)

Pin No. P in Name S i

nal Buffer T

e Pin No. Pin Name Si

nal Buffer T

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 65

proce ssor in the Single Edge Cont act Cartrid ge (S. E.C.C.) pa ckage in its re tenti on mechanis m with

heatsink supports installed. Figu re 38 shows a mechanical representation of a boxed Pent ium II

processor in the S.E.C.C.2 package.

Note: T he ai rflow of the fan heatsink is into the center and out of the sides of the f an he ats ink. The lar ge

arrows in F igure 37 denote the direction of airflow.

Fi gur e 37 . B o xed P entium® II Processor in the S.E.C.C. Packaging Installed in Retention Mechanism

(Fan Power Cable Not Shown)

Figure 38. Boxed Pentium®

II Processor in the S.E .C.C.2 Packaging (Fan Po wer Cable Not Shown)

Heatsink Support Mechanism

Processor Fan

Shroud Covering Heatsink Fins

Retention

Mechanism

Fan Power

Connector

Heatsink Support Mechanism

Motherboard

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

66 Datasheet

6.2 Mechanical Specifications

This section documents the mechanical specifications of the boxed Pentium II proc essor fan

heatsinks. Motherboard manufac turers and system designers should take into ac count the spac ial

r equirement for both the boxed Pentium II pr ocessor in the S.E.C.C. package and the boxed

Pentium II proc es sor in the S.E.C.C. 2 package.

6.2.1 Boxed Process or Fan Heatsink Dimensions

The boxed processor is shipped with an attached fan heatsink . Clearance is required around the f an

heatsink to ensure unimpeded air fl ow for proper cooling. The space requirements and dimens ions

for the boxed p rocessor in t h e S.E.C.C. package ar e shown i n F igure 39 (Side View), Figure 40

( Fr ont View), and Figure 43 (Top View). Spacia l requirements and dimensions for the box ed

pro c essor in th e S .E .C.C . 2 p ac ka g e ar e sh o w n in Figure 41 (Side Vi ew ), Figure 42 (Front View),

and F igure 43 (Top View). All dimensions are in inches.

Figure 39. Side View Space Requir ements for the Boxed Processor wi th S.E.C.C. Packag ing

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 67

Figur e 40. Front View Space Requirements for the Boxed Processor with S.E.C.C. Packaging

Figure 41. Side View Space Require ments for the Boxed Processor with S.E.C.C.2 Packaging

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

68 Datasheet

Figure 42. Fr on t View Space Requirements for the Boxed Processo r with S .E.C.C.2 Packaging

Figure 43. Top View Air Space Requirements f or the Boxed Processor

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 69

NOTE:

1. See Figure 45, label N.

6.2.2 Boxed Processor Fan Heatsink Weight

The bo xed proces sor fan heatsin k will not weigh mo re than 2 25 grams. See Se ction 4 .0 and S ecti on

5.0 for details on the heat sink pre f orm ance requirements and proces sor weight.

6.2.3 Boxed Processor R etention Mechanism and Fan Heatsink Supports

The boxed process or requires processor retenti on mechanism(s ) to secure the proc essor in the 242-

contact sl ot connector. S.E.C. C. pr ocessors must use either the rete ntion mechani sm desc ribed in

AP-588, Mechan ical and Assembly Technology for S.E. C. Cartr idge Proce sso rs (Order Number

243333), o r retention me chanisms tha t have bee n des igned to support S .E .C.C., S.E. C.C.2, and

Single Edge Processor Pac kage (S.E.P.P.) form factors (also known a s uni versal reten tion

mechanisms). S.E.C.C.2 proces sors must us e either retention m echanis ms described in AP-826,

Mech anical Assembly and Cus tomer Manufacturing Technology for S.E.P. Packages (Order

Number 243748). The boxe d proc essor will not ship with a retention mechanism. Motherboards

des igned for use by system integrators must include retention mech anisms that support the

S.E.C.C. an d S.E. C.C.2 form factors and the approp riate installation instruct ions.

Some bo xed Penti um II proc essors usin g the S.E.C .C. packa ging te ch nology were ship ped with fa n

heatsink supports. T hes e supports differ from supports for passive he atsinks. Th e boxed processor

fan heatsink support r equires heats ink support holes in the motherboard. Loca tion and s ize of these

holes are give n in Figure 44.

Tabl e 37. B oxed Processor Fan Heatsi nk Spatial Dimensi ons

. Ref.

Label Refers to

ure Dimensions (Inches) Min T

Max

AFigure 39 S.E.C. C. Fan Heatsink Dept h (off processor ex tended

thermal plate) -1.11.3

BFigure 39 S.E.C.C. Fan Heatsink Height Above Motherboard Note 1 0.5 -

CFigure 40 S.E.C.C. Fan Heatsink Heig ht - 2.1 2.2

DFigure 40 S.E.C.C. Fan Heatsink W idth (plastic shroud only) - 4.8 4.9

EFigure 40 S.E.C.C. Power Cable Connector Location From Edge

of Fan Heatsink Shroud 1.3 - 1.45

FFigure 41 S.E.C.C. 2 Fan Heatsink Depth (off processor subst rate) - 1.3 1.4

GFigure 41 S.E.C. C. 2 Fan Heatsink Height A bove Moth erboard 0.4 0.6 -

HFigure 42 S.E.C. C. 2 Fan Heatsink Height - 2.0 2.2

IFigure 42 S.E.C. C. 2 Fan Heatsink Width (plastic shro ud o nly) - 4.7 4.8

JFigure 42 S. E.C .C. 2 Powe r Cable Con necto r Locat ion Fr om Edge

of Fan Heatsink Shroud 1.4 - 1.45

KFigure 43 A ir flow keep out zon e s from e nd of fan heats ink 0.40 - -

LFigure 43 A irflow keepout zones fr om f ace of fan heatsi nk 0.20 - -

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

70 Datasheet

Any mot herboard compone nts placed in the area be neath the fan he atsi nk supports must recognize

the cl earan ce giv en in Ta ble 38. Component height restrictions for passive heatsi nk support

des igns, as described in AP-588, Mec hanical and Assembly Technology for S. E. C. Ca rt ridge

Processors (O rder Num ber 243333), still apply.

Motherboards designed for use by system integrators should not have objec ts installed in the

heat sink support holes. Othe rwise, removal instructions for objec ts preinstalled in the heatsink

support holes should be included in the mot herboard documentation.

NOTE:

1. All dimensions are in inches. Unless otherw ise speci f ied, all dimensions with th ree significant digits have a tolerance of

± 0.005 inches. All dimens ions with two significant di git s have a tol e r ance of ± 0.01 inches.

Figure 44. Heatsink Support Hole Loc ations and Size

Table 38. Boxed Pr ocessor Fan Heatsi nk Support Dimensions1

. Ref.

Label Refers to

ure Dimensions (Inc hes) Min T

Max

MFigure 45 Fan He atsin k s upport height 2.261

NFigure 45 Fan Hea tsi nk suppor t clearance above mother board 0.43 0

OFigure 45 Fan Heatsin k s upport standoff diameter 0.275 0.30 0

PFigure 45 Fan Heatsin k s upport front ed ge to heatsink su pport hole

center 0.240

QFigure 45 Fan Heats ink support standoff protrusion ben eath mother board 0.06

RFigure 45 Moth erb o ard th ic kne ss 0.0 5 0.0 6 0 .0 75

SFigure 46 Spacing between FH S Suppor ts 4.084

TFigure 46 Fan Heatsink support width 0.600

UFigure 46 Fan He atsin k s upport inner edge to heatsink support hole 0.40 0

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 71

Figure 4 5. Si de Vi ew Space Requirements for Box ed Processor Fan Heatsink Supports

Figure 46. Top Vi ew Space Requirements for Boxed Processor Fan Heatsink Supports

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

72 Datasheet

6.3 Boxed Processor Requirements

6.3.1 F an Heatsink Power Supply

The boxed processor's fan hea ts ink requires a +12 V powe r su pply. A fan power cable will be

shipped with the boxed processor to draw power from a power he ader on the motherboard. The

power cable connector a nd pinout are shown in Figure 47. Motherboards must pr ovide a matched

power he ade r to support the boxed processor. Table 3 9 contains specifications for the input and

output signals at the fan heatsi nk connec tor. T he cable length will be 7.0 ± 0.25 inches. The fan

heat sink outputs a SENSE signal, which is an open-collector output, that pulses at a rate of two

pulse s per fan revolution. A motherboa rd pull-up resistor provides VOH to match the motherboard-

mounted fan speed mon itor requirements , if appl icable. Use of the SENSE s ignal is optional. If the

SENS E signal is not used, pin 3 of the conn ec tor should be tied to GND.

The power hea der on the baseboard mu st be posit ioned to allow the fan heatsi nk power cable to

r each it. The power head er identificat ion and location shoul d be document ed in the motherboard

do cum entation, or on the mot herboard itself. Figure 48 shows the location of the fan power

connect or relative t o the 242-contact slot connec tor. The mo therboard power header should be

positioned within 4.75 inches (lateral) of the fan power connector.

Figur e 47. Boxed Processor Fan Heatsi nk Power Cable Connector Desc ript ion

Table 39. Fan Heatsink Power and Signa l Specifications

Descri

tion Min T

Max

+12 V: 12 volt f a n po w e r su p pl y 9 V 12 V 1 3. 8 V

IC: Fan current draw 100 mA

SENSE: SENSE frequency (motherboard should pull this pin

up to appropria te VCC with re sisto r) 2 pulses per fan revolution

Pin Signal

Straight square pin, 3-pin terminal housing with

polarizing ribs and friction locking ramp.

0.100" pin pitch, 0.025" square pin width.

Waldom/Molex P/N 22-01-3037 or equivale nt.

Match with straight pin, friction lock header on motherboard

Waldom/Molex P/N 22-23-2031, AMP P/N 640456-3,

or equivalent.

GND

+12V

SENSE

000888

123

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 73

6.4 Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution utilized by the boxed

processor.

6.4.1 Boxed Processor Cooling Requirements

The boxed processor will be coo led with a fa n hea tsink. The boxed proce sso r f an heats ink will

keep the proc essor temperature , within the specifications ( see Section 4.0), provided a irflow

through the fan heatsink is unimpeded and the a ir temperature entering the fan is below 45 °C ( see

Figure 43 for measurement location).

Airspace is re quired around the fan to ensure that the airflow through the fan heatsink is not

blocke d. Blocking the a irflow to the fan he atsink reduces the cooling efficiency a nd de creases fan

life. Figure 43 i l lu strat es an acce pt ab l e ai rs p ac e cl earan ce fo r th e fa n hea ts in k .

Figur e 48. Recommended Motherboard Power Header Placement Relative to Fan Power Connector and

Pentium® II P roces so r

Ta bl e 40 . Mot herbo a rd Fan Po w e r C onnec t or Loca t i on

. Ref. Labels Dime nsio ns (I nches) Min T

Max

VAproximate perpendicular di s tance of the fan power

connector from the center of the 242-conta ct slot connector 1.44

WAproximate parallel distance of the fan power connector

from the edge of the 242-contact slot connector 1.45

XLateral distance of the motherboard fan power header

locat ion from the fan power connector 4.75

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

74 Datasheet

7.0 Pentium® II Processor Si

nal Descri

tion

This section provides an alphabetic al lis ting of all Pentium II processor sig nals. The tables at the

end of this section summarize the signa ls by direction: output, input, and I/O.

7.1 Alph abet ical Signals Reference

Table 41. Signal Descri ption (She et 1 of 8)

Name T

e Descri

tion

100/66# I/O

This bidirectional signal is used to select the system bus frequency. A logic low will select a

66 M H z s ystem bus frequenc y and a logic high (3 .3 V) will s elect a 100 M Hz sy s tem bus

frequenc y. The frequenc y is de termined by the p rocessor(s), PCIset, and frequency

synthesizer. All sy stem bus agents mus t operate at the same fr equency; in a two - wa y MP

Pentium® II procesor configuration, t his signal must connect the pins of bo th Pentium II

processors. This signal will be gr ounded by pr ocessors that ar e only capab le of operating at

a hos t frequenc y of 66 MHz. On mother boards which support op eration at either 66- or

100 MHz, t his sig nal mus t be pul led up to 3. 3 V w ith a 2 00Ω resistor (as shown in the figure

be low) an d provided as a f r e quency selection sig nal to the clo c k dr iver/synth es izer. If the

syst em motherb oard is not capable o f ope rating at 100 MHz (e.g., Intel® 440FX and 440LX

PCIs et-based s ys tems), it s hould ground this signal and generate a 66 MHz system bus

frequency. This s ignal can also be in corporated into RESET# logic on the motherboard if

only 100 MHz operation is supported (thus forcing the RESET# signal to remain active as

long as the 100/66# signal is low).

100/66# Pin Exam

A[35:3]# I/O

The A[ 35:3]# (Address) signals define a 236-byte physical memor y address space. When

ADS# is act ive, these pins transmit th e address of a transaction; whe n AD S# i s inactive,

these pins t ran smit tr ansac tion ty pe infor mati on. Th ese signa ls mu st connec t the ap prop riate

pins of all agent s on the Pentium II processor system bus. The A[35:24]# signals are parity-

protected by the AP1# parity signal, and the A [23:3]# s ignals ar e parity-protected by the

AP0# parit y s ignal.

On the active-to-inactive transition of RESET#, the processors sample the A[35:3]# pins to

de termin e their power - on configur ation. See the Pentium® II Processor Developer’s

Manual (Order Number 243502) for details.

3. 3 Vol ts

100/66#

CK100

Processor

Core

GND

Pentium® II Processor

3.3 K Ω

1 KΩ

200 Ω

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 75

A20M# I

If the A20M# (Address-20 Mask) input signal is asserted, the Pentium II processor masks

phys ical address bit 20 (A20#) before looking up a li ne in any internal cache and before

driving a read/write t r ansaction on the bus. Asserting A20M# emulates the 80 86 pro cessor's

address wra p-around at th e 1-Mbyte b oundary. Assertion of A20M# is only supported in

real mode.

A20M # is an a s ynchronous s ignal. H ow ever , to ensure recog niti on of t his signal following

an I/O write in struc t ion, it m ust be valid along with the TRD Y# asse rtio n of the

corresponding I/O Write bus transacti on.

During active RESET#, each processor begins sampling the A20M#, IGNNE#, and

LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock frequency.

See Tab le 9. On the active- to-inactiv e transition of RESE T#, each processor latches these

signal s and freezes the frequency rati o i nternally. Syst em logic must then release these

signals for nor mal operat ion.

ADS# I/O

The ADS# (Address Strobe) signal is asserted to indicate the validity of the transaction

address o n the A[35: 3]# pins. Al l bus agents observe the A D S# activation to begin par it y

chec king, protocol check ing, addres s decode, internal snoop, or deferr ed reply ID match

ope r ati ons associated with th e new transacti on. This s ignal mus t connect the a ppr opriate

pins on all Pentium II processor system bus agents.

AERR# I/O

The AERR# (Address Parity Error) s ignal is observed a nd driven by all Pentium II

processor syst em bus ag ents, and if us ed, must connect the appropriate pi ns on all P entium

II proc e s s or s ys tem bu s age nts . AERR# obs erv ation is op t iona lly e na b l e d du r i n g pow e r - o n

config urati on; if enabled, a valid assert ion of AERR# abo r ts the current transaction.

If AERR# observation is disabled during power-on configuration, a central agent may

handle an assertion of AERR# as ap propriate to th e error handling architecture of the

system.

AP[1:0]# I/O

The AP[1:0]# (Address Parity) signals are driven by the request init iator along with ADS#,

A[35:3]#, REQ[4:0]#, and RP#. AP1# covers A[35 :24]#, and AP0# covers A[ 23:3]#. A

correct parity signal is hig h if an even number of cover ed s ignals are low and lo w if an odd

number of cove red signals are low. This allows parity to be high when all the covered

signals are high. AP[1: 0]# should connect the appropriat e pi ns of all Pentium II processor

system bus ag ents.

BCLK I

The BCLK (Bus Clock) si gnal deter mines the bus fre quency. All Pentium II processor

system bus agents must receive this signal to drive their outputs and latch their inputs on the

BCLK ris ing edge.

All external timing parameters are specifie d with respect to the BCLK signal.

BERR# I/O

The BERR# (Bus Error) signal is asserted to indicate a n unrec overable error without a bus

prot ocol viola tion . It ma y be dri ven b y all Pe ntiu m II proc ess or syst em bu s agents , and must

connect the appropriate pins of all such agents, i f used. Ho w ever, Penti um II pr ocessors do

not observe asser tions of t he B ER R# signal.

BERR# assertion conditions are configurable at a system level. Asserti on options are

defi ned by the follow ing option s :

• Enabled or disabl ed.

• Asserted optionally for internal errors along with IERR#.

• Asserted optionally by the request initiator of a bus transaction after it observes an

error.

• Asserted b y any bus agent when it obse r ves an error in a bus transac tion.

Table 41. Si gnal Desc ription (Sheet 2 o f 8)

Name T

e Descri

tion

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

76 Datasheet

BINIT# I/O

The BINIT# (Bus I nitializat ion) sign al may be observed and driven by all Pentium II

pro ces s or s ys tem bus agents, and i f us ed mus t connect the appropriate pins of all s uch

agents. If the BINIT# driver is e nabled during power on configuration, BINIT# is asserted

to signal any bus condition that prevents reliable future information.

If BIN IT# observation is e nabled duri ng power-on configuration, an d BIN IT# is sampled

asserted, al l bu s st at e machines are reset an d any data which was in tra nsit is lost. All agents

reset their rotating ID for bus arbitration to the state after Reset, and internal count

infor mation is lost. The L1 and L2 caches are not affected.

If BIN IT# observation is disabled du ring power-on configurati on, a central agent may

handle an assertion of BINIT# as app ropri ate to the error handlin g archi tecture of the

system.

BNR# I/O

The BN R# (Block Next Reques t) s ignal i s us ed to assert a bus st all by any bus agen t who is

unabl e to acc ept new bu s tra nsacti ons. Duri ng a bus stal l, the cu rr ent bus ow ner can not i ssue

any new transactions.

Sin ce multip le agent s might need to reque st a bus st all at the same time, BNR# is a wire- OR

signal which must connect the appropriate pins of all Pentium II processor system bus

agents. In order to avoid wire-OR glitches associated with simultaneous edge transitions

driven by multiple drivers, BNR# is activated on specific clock edges and sample d on

specific clock edges.

BP[3:2]# I/O The BP[3:2]# (Breakpoint) signals are outpu ts from the proces s or that indicate the status of

breakpoints.

BPM[1:0]# I/O The BPM[1 :0]# (Breakpoint Monitor) signal s are breakpoint and perfor m ance monitor

signals. They are outputs from the pr oces sor which indicate the status of breakpoints and

program ma ble counter s used for m on ito ring proce ssor performan ce.

BPRI# I

The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the Pentium II

processor system bus. It must connect the appropriate pins of all Pentium II processor

system bus agents. O bse r ving BPRI# act ive (as assert ed by the priority agent) c aus es all

othe r agent s to s top iss uing new req uests, unles s such request s are par t of an ong oi ng loc ked

operation. The priority agent keeps BPRI# asserted until all of its requests are completed,

then releases the bus by deasserting BPRI#.

BR0#

BR1#

I/O

The BR0 # and BR1# (Bus R equest) pins dr iv e the BRE Q [ 1:0]# s ignals in the sys tem. The

BREQ[ 1:0]# sig nals are interconnected i n a r otating mann er to individual processor pi ns .

The t able below gives the rotating int e r connect between the pro ces s or and bus s ignals.

D[63:0]# I/O The D[63: 0]# (Data) signals are t he data signals. These signals provi de a 64-bit da ta path

be tween the Pentium II processor system bus agents, and must connect the appr opriat e pins

on all s uch a gents. The data dr iver assert s D RDY# to i ndicate a vali d data transfer .

Table 41. Signal Descri ption (She et 3 of 8)

Name T

e Descri

tion

Du rin g pow er-up con fig urati on, the central agent must ass ert t he BR0# bus s ignal. All

symmetric agents sample their BR[1:0]# pins on active -to-inactive transition of RESET#. T

pin on which the agent samples an active level determines its agent ID. All agents then

c onf igure their pins to match the appropriate bus signal pr otocol, as shown below .

BR0# (I/O) and BR1# Si

nals Rotatin

Interconnect

Bus Si

nal A

ent 0 Pins A

ent 1 Pins

BREQ0# BR0# BR1#

BREQ1# BR1# BR0#

BR[1:0]# Si

nal A

ent IDs

Pin Sam

led Act ive in RESET# A

ent ID

BR0# 0

BR1# 1

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 77

DBSY# I/O

The DB SY# (Data Bus Bus y) signal is asserted by the agent responsible for driving dat a on

the Pentium II processor system bus to indicate that the data bus is in use. The data bus is

released after DBSY# is deasserted. This signal must connect the approp riate pins on all

Pentium II processor system bus agents.

DEFER# I

The DEF ER# s ignal is asse r ted by an agent t o indicate that a transaction cannot be

gua ranteed in-order completion. Assertion of DEFER# is normally the responsibility of the

addressed memory or I/O agent. Th is signal must connect the appropriate pins of al l

Pentium II processor system bus agents.

DEP[7:0]# I/O

The DEP [7:0]# (Dat a Bus ECC Protection ) si gnals provide option al ECC protect ion for the

data bus. They are dri ven by the agent re s ponsible fo r drivin g D [63:0]#, and mus t connect

the appropr iate pins of all Pentium II pr ocessor system bus agents whi c h us e th em. The

DEP[ 7:0]# signals are enabl e d or di s abled for ECC protection during power on

configuration.

DRDY# I/O

The DRDY# (Data R eady) signal is asse r ted by the data dr iver on each dat a transfer,

indi cating valid data on the dat a bus. In a multi-cycle data transfer, DRDY# may be

deas s e r ted to insert idle clocks. This signa l must c onnect the appropriate pins of all Pentium

II pr ocessor system bus agents.

EMI I

EMI pi ns sho ul d be conn ect ed to mo ther boa rd grou nd an d/or to ch assi s gr ound t hrou gh ze ro

ohm (0Ω) resist ors. The zero ohm resistors should be placed in c lose proximity to the

Penti um II processor connector. Th e path to chassi s ground sho uld be short in length and

h a ve a low imp eda n ce . The s e pins are us e d for EM I man a ge m e nt purposes.

FERR# O

The FERR# (F loating-poin t E rror) signal is ass erted when t he processor detects an

unma s ked floating- point error. F ERR # is similar to the ER ROR # s ignal on the In tel 387

co proc es sor, and is include d for compa tib ili ty with syste ms using MS-DOS *-type floating-

point error reporting.

FLUSH# I

When the FL U SH# input sig nal is asserted, processors wri te back al l dat a in the Modi fied

state from the ir internal caches and inval idate a ll int ernal cache lines. At the compl etion of

thi s oper ation, the proce s s or issues a Flush Acknow ledge tr ans action. The proces s or does

not cache any new data while the FLUSH # signal r emains asserted.

FLUSH # is an asynchronous s ignal. However, to ensure recognition of this s ignal following

an I/O write in struc t ion, it m ust be valid along with the TRD Y# asse rtio n of the

corresponding I/O Write bus transacti on.

On the act ive-to-inactive transi tion of RESET#, each processor sa mples FLUSH# to

de term in e its powe r-o n config ur at io n. See P6 Family of Processors Hardwa re Developer’s

Manual (Order Number 244001) for det ails.

HIT#

HITM#

I/O

The HIT# (Snoop Hit) a nd H I TM# (Hit Mo dified) signals con vey transacti on snoop

operation results, and must connect the appropriate pi ns of all Pentium II processor system

bus ag ents. Any such agent may as s ert both HIT # and HITM# tog ether to i ndicate th at it

requires a s noop stall, w hich can be conti nued by reas s erting HIT# and HI TM# to gether.

IERR# O

The IERR# (Internal Error) signal is asserted by a processor as the result of an internal error .

Assertion of IERR# is us ually acco mpanied by a SHUTDOWN transaction on the Pentium

II processor system bus. This tr ansaction may optionally be converted t o an external error

signal ( e .g., NMI) by system cor e logic. The pro cess or will kee p I ERR# asse r ted until the

asser tion of RESET #, BINIT#, or INIT#.

Table 41. Si gnal Desc ription (Sheet 4 o f 8)

Name T

e Descri

tion

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

78 Datasheet

IGNNE# I

The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to ignore a

numeric error and continue t o execute noncontrol fl oating-point instructions. If IGN NE# is

de as s erted, th e pr ocessor generates an exception on a noncontrol floating-poi nt instr uction

if a previous floating-point instruction ca used an error. IGNNE# has no effect whe n the NE

bit in contro l regis ter 0 is set.

IGNNE# is an asynch ronous signal. However, to ensure recognition of this signal following

an I/O write instruction, it must be valid along with the TRDY# assertion of the

corresponding I/O W r ite bus transaction.

During active RESET#, the Pentium II processor begins sampling the A20M#, IGNNE#,

and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock

frequency. See Table 9. On the active-to-inactive transition of RESET#, the Pentium II

pro ces s or latches these sign als and freezes the fr equency rat io inte rn ally. Syst em logic must

then release these signals for normal op eration.

INIT# I

The INIT# (Initialization) signal, when asserted, resets integer registers inside all proc essors

without af f ecting t heir inter nal (L1 or L2) caches or floating-p oint re gisters. Each processor

then begi ns execution at the power-on Res et vect or configured during powe r-o n

configuration. The processor continues to handle snoop requests during INI T# assertion.

INI T# is an asynchronous signal and mus t connect the ap propriate pi ns of all Pentium II

processor system bus agents.

If INIT# is sampled active on the active to inactive transition of RESET#, then the proc essor

execu te s its Built- in Self-Test (BIST).

LINT[1:0] I

The LINT[1:0] (Local APIC Int errupt) sign als must connect the appropriate pi ns of all

APIC B us ag ents, incl udin g all proce ssor s an d the co re l ogic or I/O APIC co mpon ent. When

the APIC is disabled, t he LINT0 signal becomes INTR, a mas kable interrupt request s ignal,

and LIN T1 becomes NMI, a nonmaskable int errupt. IN TR and NMI are b ackw ard

compatible with the signals of those names on the Pentium processor. Both signals are

asynchronous.

Both of these s ignals mus t be so f tware conf igured vi a BIO S pr ogramming of the API C

regis ter space to be used either as NMI/ I N TR or LIN T[1:0]. Because the APIC is en abled

by default after Reset, operation of the se pins as LINT[1:0] is the default configuration.

During active RESET#, the Pentium II processor begins sampling the A20M#, IGNNE#,

and LINT[1:0] values to determine the ratio of core-clock frequency to bus-clock

frequency. See Table 9. On the active-to-inactive transition of RESET#, the Pentium II

pro ces s or latches these sign als and freezes the fr equency rat io inte rn ally. Syst em logic must

then release these signals for normal op eration.

LOCK# I/O

The LOCK# sig nal in di cates to the syst em th at a transa ctio n must occ u r atomic a lly. T his

signal must connect the appropriate pins of all Pent ium II processor system bus agents. For

a locked sequence of trans actions , LOC K # is asserted from the beginning of the first

transaction end of the last transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of the Pentium II proc essor

system bus, it will wait until it observes LOCK# deasserted. This ena bles symme tric agents

to retain owne rshi p of the Pen tiu m II proce ssor syste m bus thro ugh out th e bus lock ed

operation and ensure the atomicity of lock.

PICCLK I The PICCLK (APIC Clock) signal is a n input clock to the processor and core logic or I/O

APIC which is re quired for operation of all processors, core log ic, and I/O APIC

components on the A PI C bus.

PICD[1:0] I/O The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing on the

APIC bus, and must connect the appropriate pins of all processors and core logic or I /O

APIC component s on t he A PI C bus.

PRDY# O The PRDY (Probe Ready) signal is a processor o utput use d by debug tools to determi ne

processor debug readiness.

PREQ# I The PREQ# (Probe Reque s t) signal is used by debug tools to request debug operation of the

processors.

Table 41. Signal Descri ption (She et 5 of 8)

Name T

e Descri

tion

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 79

PWRGOOD I

The PWRGOOD (Power Go od) signal is a 2.5 V tolerant proce ssor input. The pr ocessor

requires this signal to be a clean indication that the clocks and power supplies (VCCCORE,

etc. ) are stable and within their spec ifications. Clean implies that the s ignal w ill r emain low

(capable of s inking l eakage curr ent), wi thout gl itches, from the ti me that t he power s upplies

are turne d on until th e y come withi n spec ific a tion . The s igna l mus t then transition

monotonically to a high (2.5 V) state. The figure below illustrates the relationship of

PWRGOOD to other system signals. PWRGOOD can be driven inactive at any time, but

clocks and power must ag ain be stable before a subsequent rising edge of PWRGOOD. It

must also meet the minimu m pulse width specificati on in Table 14 and Table 15, an d be

foll owed by a 1 ms RESET# pulse.

The PWRGOOD signal must be sup pli ed to the p roces sor; it is used to protect internal

cir cuits agains t voltage sequencing issues. I t should be dri ven high thr oughout boundary

scan operation.

PWRGOOD Relationshi

at Pow er- On

REQ[4:0]# I/O The REQ [ 4:0]# (Request Command) signals must connect the appropriate pins of all

Penti um II proc es s or s ys tem bus agents . They are assert ed by the cur rent bus ow ner over

tw o clock cycl es to define the cu rren tly activ e trans a ctio n type.

RESET# I

Asserting th e RESET# signal resets all processors to known states and invalidates their L1

and L2 caches without writing back any of their contents. RESE T# must remain active for

one mi crose con d for a “warm” Re set; for a powe r-on Re set, RES ET# must stay act ive for at

least one mill isecond aft er VCCCORE and CLK have reached their pr oper specif ications. O n

observing active RESET#, all Pentium II processor system bus agents will deassert their

ou tp uts with in two cl ock s.

A numbe r of bu s s ignals are sampled at t he active-to-inactive transition o f RE SE T# for

power-on config uration. These configuration opti ons are desc r ibed in the P6 Family of

Processor s Ha rdware Developer’s Manual (Order Number 244001) for details.

The pr ocessor may have it s outputs tr istated via power-on con figuratio n. Otherwise , i f

INI T# is sam p led act iv e during the activ e -to -in acti ve tra nsi tio n of RESET #, the proces so r

wi ll exe cute its Buil t-in Se lf-Te st (BIST ) . Whet her or not BIST is exec uted , the pr oces sor

will begin program execution at th e powe r on Rese t vector (def ault 0_FFFF_FFF0h).

RESET# mus t connect t he appropriate pins of al l Pentium II processo r sys tem bus agents.

RP# I/O

The RP# ( Request Par it y) signal is driven by the request initiator, an d provides par ity

protection on AD S# and REQ [4:0] #. It must connect the appropri ate pins of all Pentium II

processor system bus agents.

A corr ect parity signal is high i f an even number of covered signals are low and low if an

odd number of covered signals are low. This definition allows parity to be high when all

cove r e d s ignals are hi gh.

RS[2:0]# I The RS[2: 0]# (Response Status) signals are driven by the response ag ent (the agen t

responsible for completion of the current transaction), and must connect the appropriate

pins of all Pentium II processor system bus agents.

Table 41. Si gnal Desc ription (Sheet 6 o f 8)

Name T

e Descri

tion

BCLK

PWRGOOD

RESET#

D0026-00

1 m sec

VIH,min

VCC,

VCCP,

VREF

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

80 Datasheet

RSP# I

The RSP# (Response Par ity) signal is driven by the response agent (the agent responsible

for completion of the current transaction) during assertion of RS[2:0]#, the signals for

which RSP# provides par ity protect ion. It must connect the appropri ate pins of all Pentium

II processor system bus agents.

A corr ect parity signal is high if an even number of covered signals are low and lo w if an

odd number of covered s ignals are low. While RS[2:0]# = 000, RSP# is also hi gh, sinc e this

indi cates it is not bein g driven by any agent guara nteeing correct p arity.

SLOTOCC# O

The SLOTOCC# signal is defined to allow a system design to detec t the presence of a

terminator card or processor in a S C 242 connector. Combined with the VID combination of

VID[4:0]= 1111 1 (see Section 2.6), a s ys tem can determin e if a SC 242 connector is

oc cupied, and whet her a proces s or core is present. Se e the ta ble below for states and val ues

for determining the ty pe of cartridge in th e SC 242 connector.

SLP# I

The SLP# (Sleep) signa l, w hen asserted in Stop- G r ant state, ca uses processors to enter the

Sleep state. Dur ing Sleep s tate, the pro ces s or stops provi ding internal clock signals to all

units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will

not recognize sn oops o r interr upts. The processor will recognize only as s ertions of the

SLP#, STPCLK#, and RESET# signals while in Sleep state. If SLP# is deasserted, the

processor exits Sleep state and returns to Stop-Grant state, rest arting its internal clock

signals to the bus and APIC processor core un its.

SMI# I

The SMI# (System Management Interrupt) signal is a sserted asynchronously by system

logi c. On accept ing a Syst em Management Int errupt, processors s ave the current stat e and

enter S ystem Manageme nt Mode (SMM). An SMI Acknowledge tra ns action is issued, and

the processor begins prog ram execution fro m the SMM handler.

STPCLK# I

The STPCLK # (Stop Cl ock) signal, when asserted, causes pr oces s ors to enter a low pow er

Stop-Grant s tate. The processor i s sues a Stop-Grant Ac knowledge transa ction, and stops

provi ding internal cl ock signals to all processor core units except the bus and APIC units.

The pr ocessor continues t o s noop bus trans actions and ser vice interrupts while i n Stop-

Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all

unit s and resumes execution. Th e as s ertion of STPCLK# has no effect on the bus clock;

STPCLK# is an asynchronous input.

TCK I The TCK (Test Clock) signal provides the clock input for the Pentium II processor Test Bus

(al s o known as the Test Acces s Port).

TDI I The TDI (Test Data In) signal transfers serial test da ta into the Pentium II processor . TDI

provi des the serial input needed for JTAG specif ication support.

TDO O The TDO (Test Data Out) signal transfers serial test data out of the Pentium II processor.

TDO provides the serial output needed for JTAG specification support.

TESTHI I The TESTHI signal must be connected to a 2.5 V power s ource through a 1 -100 kΩ resistor

for proper processor oper ation.

THERMDN O Thermal D iode Cathod e. Use d to calculate core t emperature. See Se ction 4. 1.

THERMDP I Thermal Diode Ano de. Used to calcul ate core temperature. See Section 4. 1.

Table 41. Signal Descri ption (She et 7 of 8)

Name T

e Descri

tion

SC 242 Occu

at io n Tr u t h Tabl e

nal Value Status

SLOTOCC#

VID[4:0]

Any thing other than

‘11111’ Process or with core in SC 242 connect or.

SLOTOCC#

VID[4:0] 0

11111 Termi nator cartr idge in SC 242 connector

(i.e., no core present).

SLOTOCC#

VID[4:0] 1

An y va l u e SC 242 connector no t occupied.

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 81

7.2 Si gnal Summaries

Table 42 through Table 45 list attributes of the Pentium II process or output, input, a nd I/O si gnals.

THERMTRIP# O

The processor protects itsel f from catastroph ic over heating by use of an in tern al thermal

sensor. This sen s or is set w ell ab ove the n or mal operating temperature to ensure that ther e

are no false trips. T he pr ocessor will s top all execution when th e ju nction temperature

exce eds approximate ly 135 °C. Th is is signaled to the s ys tem by t he THER MTRI P#

(Thermal Trip) pin. Once acti vated, the si gnal remain s lat ched, and the proc es s or s topped,

until RESET# goes active. There is no hysteresis built into the thermal sensor itself; as long

as the die temperature drops below the trip lev e l, a RES ET # pulse will res et the processor

an d exec ut io n will con tin u e. If the tempe ra tur e ha s not drop p ed belo w the trip level, the

pro cess o r will con tin ue to drive THER MTRIP# and rem ain sto pp ed.

TMS I The TMS ( Test Mode Sel ect) si gnal is a JTAG specif ication support si gnal used by debug

tools.

TRDY# I The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to

receive a write or implicit writeback data transfer. TRDY# must connect the appropri ate

pins of all Pentium II processor system bus agents.

TRST# I The TRST# (Test Reset) sign al resets the Test Access Port (TAP) logic. TRST # must be

dri ven low during power on Reset. This can be done with a 680 ohm pull- down resi s tor.

VID[4:0] O

The VID[4:0] ( Voltage ID) pins can be us ed to sup port auto matic selection of power supp ly

volt ages. These pins are n ot signals, but are eit her an o pen circuit or a short circuit to VSS

on the processor. Th e combination of opens and shorts defines the voltage requ ire d by the

processor. The VID pins are needed t o cleanly support voltage specification variat ions on

Pentium II proc essors. See Table 1 for definitions of these pi ns. The power supply must

supp ly th e voltage that is requested by these pins, or disable i tself.

Table 41. Si gnal Desc ription (Sheet 8 o f 8)

Name T

e Descri

tion

Table 42. Output Signals

Na m e Active L e ve l Cloc k Si

na l G rou

FERR# Low Asyn ch CMOS Output

IERR# Low Asyn ch CMOS Output

PRDY# Low BCLK AGTL+ Output

SLOTOCC# Low Asynch Power/Other

TDO High TCK JTAG Output

THERMTRIP# Lo w Asyn ch CMOS Output

VID[4:0] High Asynch Power/Other

Pentium® II Proce ssor at 350 MHz, 400 MHz, and 450 MHz

82 Datasheet

NOTE:

1. Synchronous as s ertion with act ive TDRY# ensur es s ynchron ization.

Table 43. Input Signals

Name Active Level Clock Si

nal Grou

Qualified

A20M # L ow Asynch CMOS Inp ut Al w ays1

BPRI# Low BCLK AGTL+ In put Alw ays

BR1# Low BCLK AGTL+ Input Always

BCLK High — Clock Always

DEFER# Low BCLK AGTL+ Input Always

FLU SH# Low Asynch CMOS Input Alwa ys1

IGNNE# Low Asynch CMOS Input Al ways1

INIT# Low Asynch CMOS Input Always1

INTR High Asynch CMOS Input APIC disabl ed mo de

LINT[1:0] High Asynch CMOS Input APIC enabled mode

NM I High Asynch CMOS Inp ut APIC disabled mo de

PICCLK High — APIC Clock Always

PREQ# Low Asynch CMOS Input Alw a y s

PWRGOOD High Asynch CMOS Input Always

RESET# Low BCLK AGTL+ Input Al ways

RS[2:0]# Low BCLK AGTL+ Input Always

RSP# Low BCLK AGTL+ Input Always

SLP# Low Asynch CMO S Input Duri ng Stop- Grant sta te

SMI# Low Asynch CMOS Input

STPCLK# Low Asynch CMOS Input

TCK High — JTAG Input

TDI High TCK JTAG Input

TESTHI High Asynch Power/Other Always

TMS High TCK JTAG Input

TRST# Low Asynch JTAG Input

TRDY# Low BCLK AGTL+ Input

Pentium® II Proces s or at 350 MHz, 400 MHz, and 450 MHz

Datasheet 83

Table 44. Input/Output Signals (Single Driver)

Name Active Level Clock Si

nal Grou

Qualified

100/66# Low Asynch Power/Other Always

A[35:3]# Low BCLK AGTL+ I/O ADS#, ADS#+1

ADS# Low BCLK AGTL+ I/O Always

AP[1:0]# Low BCLK AGTL+ I/O ADS #, ADS#+1

BR0# Low BCLK AGTL+ I/O Alwa ys

BP[3:2]# Low BCLK AGTL+ I/O Always

BPM[1:0]# Low BCLK AGTL+ I/O Always

D[63:0]# Low BCLK AGTL+ I/O DRDY#

DBSY# Low BCLK AGTL+ I/O Always

DEP[7:0]# Low BCLK AGTL+ I/O DRDY#

DRDY# Low BCLK AGTL+ I/O Always

LOCK# Low BCLK AGTL+ I/O Always

REQ[4:0]# Low BCLK AGTL+ I/O ADS#, ADS#+1

RP# Low BCLK AGTL+ I/O ADS#, ADS#+1

Table 45. Input/Output Signals (Multiple Driver)

Name Active Level Clock Si

nal Grou

Qualified

AERR# Low BCLK AGTL+ I/O ADS#+3

BERR# Low BCLK AGTL+ I/O Always

BNR# Low BCLK AGTL+ I/O Always

BINIT# Low BCLK AGTL+ I/O Always

HIT# Low BCLK AGTL+ I/O Always

HITM# Low BCLK AGTL+ I/O Always

PICD[1:0] High PICCLK APIC I/O Always