IRF2804STRL-7PPBF - International Rectifier

IRF2804S-7PPbF

HEXFET® Power MOSFET

VDSS = 40V

RDS(on) = 1.6mΩ

ID = 160A

07/22/10

www.irf.com 1

HEXFET® is a registered trademark of International Rectifier.

Description

This HEXFET® Power MOSFET utilizes the latest

processing techniques to achieve extremely low

on-resistance per silicon area. Additional features

of this design are a 175°C junction operating

temperature, fast switching speed and improved

repetitive avalanche rating. These features combine

to make this design an extremely efficient and

reliable device for use in a wide variety of

applications.

Features

lAdvanced Process Technology

lUltra Low On-Resistance

l175°C Operating Temperature

lFast Switching

lRepetitive Avalanche Allowed up to Tjmax

lLead-Free

Absolute Maximum Ratings

Parameter Units

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Silicon Limited) A

ID @ TC = 100°C Continuous Drain Current, VGS @ 10V (See Fig. 9)

ID @ TC = 25°C Continuous Drain Current, VGS @ 10V (Package Limited)

IDM Pulsed Drain Current

PD @TC = 25°C Maximum Power Dissipation W

Linear Derating Factor W/°C

VGS Gate-to-Source Voltage V

EAS Single Pulse Avalanche Energy (Thermally Limited)

EAS (tested) Single Pulse Avalanche Energy Tested Value

IAR Avalanche Current

EAR Repetitive Avalanche Energy

TJ Operating Junction and °C

TSTG Storage Temperature Range

Soldering Temperature, for 10 seconds

Mounting torque, 6-32 or M3 screw

Thermal Resistance

Parameter Typ. Max. Units

RθJC Junction-to-Case

––– 0.50 °C/W

RθCS Case-to-Sink, Flat, Greased Surface 0.50 –––

RθJA Junction-to-Ambient

––– 62

RθJA Junction-to-Ambient (PCB Mount, steady state)

––– 40

Max.

320

230

1360

160

10 lbf•in (1.1N•m)

330

2.2

± 20

630

1050

See Fig.12a,12b,15,16

300 (1.6mm from case )

-55 to + 175

S (Pin 2, 3 ,5,6,7)

G (Pin 1)

PD - 97057A

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Notes:

 Repetitive rating; pulse width limited by

max. junction temperature. (See fig. 11).

 Limited by TJmax, starting TJ = 25°C,

L=0.049mH, RG = 25Ω, IAS = 160A, VGS =10V.

Part not recommended for use above this value.

 Pulse width ≤ 1.0ms; duty cycle ≤ 2%.

Coss eff. is a fixed capacitance that gives the same

charging time as Coss while VDS is rising from 0 to

80% VDSS.

Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical

repetitive avalanche performance.

This value determined from sample failure population.

100% tested to this value in production.

This is applied to D2Pak, when mounted on 1" square PCB

( FR-4 or G-10 Material ). For recommended footprint and

soldering techniques refer to application note #AN-994.

Rθ is measured at TJ of approximately 90°C.

Static @ TJ = 25°C (unless otherwise specified)

Parameter Min. Typ. Max. Units

V(BR)DSS Drain-to-Source Breakdown Voltage 40 ––– ––– V

∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.028 ––– V/°C

RDS(on) SMD Static Drain-to-Source On-Resistance ––– 1.2 1.6 mΩ

VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V

gfs Forward Transconductance 220 ––– ––– S

IDSS Drain-to-Source Leakage Current ––– ––– 20 µA

––– ––– 250

IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA

Gate-to-Source Reverse Leakage ––– ––– -200

QgTotal Gate Charge ––– 170 260 nC

Qgs Gate-to-Source Charge ––– 63 –––

Qgd Gate-to-Drain ("Miller") Charge ––– 71 –––

td(on) Turn-On Delay Time ––– 17 ––– ns

trRise Time ––– 150 –––

td(off) Turn-Off Delay Time ––– 110 –––

tfFall Time ––– 105 –––

LDInternal Drain Inductance ––– 4.5 ––– nH Between lead,

6mm (0.25in.)

LSInternal Source Inductance ––– 7.5 ––– from package

and center of die contact

Ciss Input Capacitance ––– 6930 ––– pF

Coss Output Capacitance ––– 1750 –––

Crss Reverse Transfer Capacitance ––– 970 –––

Coss Output Capacitance ––– 5740 –––

Coss Output Capacitance ––– 1570 –––

Coss eff. Effective Output Capacitance ––– 2340 –––

Diode Characteristics

Parameter Min. Typ. Max. Units

ISContinuous Source Current ––– ––– 320

(Body Diode) A

ISM Pulsed Source Current ––– ––– 1360

(Body Diode)

c

VSD Diode Forward Voltage ––– ––– 1.3 V

trr Reverse Recovery Time –––4365ns

Qrr Reverse Recovery Charge ––– 48 72 nC

VDS = VGS, ID = 250µA

VDS = 40V, VGS = 0V

VDS = 40V, VGS = 0V, TJ = 125°C

Conditions

VGS = 0V, ID = 250µA

Reference to 25°C, ID = 1mA

VGS = 10V, ID = 160A

TJ = 25°C, IF = 160A, VDD = 20V

di/dt = 100A/µs

TJ = 25°C, IS = 160A, VGS = 0V

showing the

integral reverse

p-n junction diode.

VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz

VGS = 10V

MOSFET symbol

VGS = 0V

VDS = 25V

VGS = 0V, VDS = 32V, ƒ = 1.0MHz

Conditions

VGS = 0V, VDS = 0V to 32V

ƒ = 1.0MHz, See Fig. 5

RG = 2.6Ω

ID = 160A

VDS = 10V, ID = 160A

VDD = 20V

ID = 160A

VGS = 20V

VGS = -20V

VDS = 32V

VGS = 10V

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Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance

vs. Drain Current

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

ID, Drain-to-Source Current (A)

≤ 60µs PULSE WIDTH

Tj = 25°C

4.5V

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

2.0 3.0 4.0 5.0 6.0 7.0 8.0

VGS, Gate-to-Source Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ID, Drain-to-Source Current

(Α)

VDS = 20V

≤ 60µs PULSE WIDTH

TJ = 25°C

TJ = 175°C

0 20 40 60 80 100 120 140

ID, Drain-to-Source Current (A)

120

160

200

240

Gfs, Forward Transconductance (S)

TJ = 25°C

TJ = 175°C

VDS = 10V

380µs PULSE WIDTH

0.1 110 100

VDS, Drain-to-Source Voltage (V)

100

1000

10000

ID, Drain-to-Source Current (A)

≤ 60µs PULSE WIDTH

Tj = 175°C

4.5V

VGS

TOP 15V

10V

8.0V

7.0V

6.0V

5.5V

5.0V

BOTTOM 4.5V

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Fig 8. Maximum Safe Operating Area

Fig 6. Typical Gate Charge vs.

Gate-to-Source Voltage

Fig 5. Typical Capacitance vs.

Drain-to-Source Voltage

Fig 7. Typical Source-Drain Diode

Forward Voltage

110 100

VDS, Drain-to-Source Voltage (V)

2000

4000

6000

8000

10000

12000

14000

C, Capacitance (pF)

Coss

Crss

Ciss

VGS = 0V, f = 1 MHZ

Ciss = Cgs + Cgd, Cds SHORTED

Crss = Cgd

Coss = Cds + Cgd

0.0 0.4 0.8 1.2 1.6 2.0 2.4

VSD, Source-to-Drain Voltage (V)

0.1

1.0

10.0

100.0

1000.0

ISD, Reverse Drain Current (A)

TJ = 25°C

TJ = 175°C

VGS = 0V

0 50 100 150 200 250 300

QG Total Gate Charge (nC)

VGS, Gate-to-Source Voltage (V)

VDS= 32V

VDS= 20V

ID= 160A

0 1 10 100 1000

VDS , Drain-toSource Voltage (V)

0.1

100

1000

10000

ID, Drain-to-Source Current (A)

Tc = 25°C

Tj = 175°C

Single Pulse

1msec

10msec

OPERATION IN THIS AREA

LIMITED BY R DS(on)

100µsec

IRF2804S-7PPbF

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1E-006 1E-005 0.0001 0.001 0.01 0.1

t1 , Rectangular Pulse Duration (sec)

0.0001

0.001

0.01

0.1

Thermal Response ( Z

thJC )

0.20

0.10

D = 0.50

0.02

0.01

0.05

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

Fig 9. Maximum Drain Current vs.

Case Temperature

Fig 10. Normalized On-Resistance

vs. Temperature

-60 -40 -20 020 40 60 80 100 120 140 160 180

TJ , Junction Temperature (°C)

0.5

1.0

1.5

2.0

RDS(on) , Drain-to-Source On Resistance

(Normalized)

ID = 160A

VGS = 10V

Ri (°C/W) τi (sec)

0.1951 0.000743

0.3050 0.008219

τJ

τ1

τ2

R1R2

τC

Ci i/Ri

Ci= τi/Ri

25 50 75 100 125 150 175

TC , Case Temperature (°C)

100

150

200

250

300

350

ID , Drain Current (A)

LIMITED BY PACKAGE

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QGS QGD

Charge

10 V

Fig 13b. Gate Charge Test Circuit

Fig 13a. Basic Gate Charge Waveform

Fig 12c. Maximum Avalanche Energy

vs. Drain Current

Fig 12b. Unclamped Inductive Waveforms

Fig 12a. Unclamped Inductive Test Circuit

(BR)DSS

Fig 14. Threshold Voltage vs. Temperature

0.01

Ω

D.U.T

VDS

-V

DRIVER

15V

20V

VGS

VCC

DUT

25 50 75 100 125 150 175

Starting TJ, Junction Temperature (°C)

500

1000

1500

2000

2500

EAS, Single Pulse Avalanche Energy (mJ)

I D

TOP 21A

33A

BOTTOM 160A

-75 -50 -25 025 50 75 100 125 150 175

TJ , Temperature ( °C )

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

VGS(th) Gate threshold Voltage (V)

ID = 1.0A

ID = 1.0mA

ID = 250µA

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Fig 15. Typical Avalanche Current vs.Pulsewidth

Fig 16. Maximum Avalanche Energy

vs. Temperature

Notes on Repetitive Avalanche Curves , Figures 15, 16:

(For further info, see AN-1005 at www.irf.com)

1. Avalanche failures assumption:

Purely a thermal phenomenon and failure occurs at a

temperature far in excess of Tjmax. This is validated for

every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is

not exceeded.

3. Equation below based on circuit and waveforms shown in

Figures 12a, 12b.

4. PD (ave) = Average power dissipation per single

avalanche pulse.

5. BV = Rated breakdown voltage (1.3 factor accounts for

voltage increase during avalanche).

6. Iav = Allowable avalanche current.

7. ∆T = Allowable rise in junction temperature, not to exceed

Tjmax (assumed as 25°C in Figure 15, 16).

tav = Average time in avalanche.

D = Duty cycle in avalanche = tav ·f

ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]

EAS (AR) = PD (ave)·tav

1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01

tav (sec)

0.1

100

1000

10000

Avalanche Current (A)

0.05

Duty Cycle = Single Pulse

0.10

Allowed avalanche Current vs

avalanche pulsewidth, tav

assuming ∆Tj = 25°C due to

avalanche losses. Note: In no

case should Tj be allowed to

exceed Tjmax

0.01

25 50 75 100 125 150 175

Starting TJ , Junction Temperature (°C)

200

400

600

800

EAR , Avalanche Energy (mJ)

TOP Single Pulse

BOTTOM 1% Duty Cycle

ID = 160A

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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET® Power MOSFETs

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

P.W. Period

di/dt

Diode Recovery

dv/dt

Ripple ≤5%

Body Diode Forward Drop

Re-Applied

Voltage

Reverse

Recovery

Current

Body Diode Forward

Current

VGS=10V

VDD

ISD

Driver Gate Drive

D.U.T. ISD Waveform

D.U.T. VDS Waveform

Inductor Curent

D = P. W .

Period

* VGS = 5V for Logic Level Devices







RGVDD

• dv/dt controlled by RG

• Driver same type as D.U.T.

• ISD controlled by Duty Factor "D"

• D.U.T. - Device Under Test

D.U.T



VDS

90%

10%

VGS

d(on)

d(off)

VDS

Pulse Width ≤ 1 µs

Duty Factor ≤ 0.1 %

VGS

D.U.T.

10V

VDD

Fig 18a. Switching Time Test Circuit

Fig 18b. Switching Time Waveforms

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D2Pak - 7 Pin Package Outline

Dimensions are shown in millimeters (inches)

D2Pak - 7 Pin Part Marking Information

14

Notes:

1. For an Automotive Qualified version of this part please see http://www.irf.com/product-info/datasheets/data/ auirf2804s-7p.pdf

2. For the most current drawing please refer to IR website at http://www.irf.com/package/

IRF2804S-7PPbF

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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 07/2010

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.

Qualification Standards can be found on IR’s Web site.

D2Pak - 7 Pin Tape and Reel

IRF2804STRL-7P