FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• PERFORMANCE (1850 MHz)
♦ 27.5 dBm Output Power (P1dB)
♦ 17 dB Small-Signal Gain (SSG)
♦ 1.2 dB Noise Figure
♦ 42 dBm Output IP3
♦ 50% Power-Added Efficiency
♦ Evaluation Boards Available
♦ Available in Lead Free Finish: FPD1500SOT89E
• DESCRIPTION AND APPLICATIONS
The FPD1500SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25 x 1500 μm Schottky barrier Gate, defined by high-
resolution stepper-based photolithography. The recessed and offset Gate structure minimizes
parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a
range of bias conditions and input power levels. The FPD1500 is available in die form and in other
packages. Typical applications include drivers or output stages in PCS/Cellular base station high-
intercept-point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
• ELECTRICAL SPECIFICATIONS AT 22°C
Parameter Symbol Test Conditions Min Typ Max Units
RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
Power at 1dB Gain Compression P1dB VDS = 5.0V; IDS = 50% IDSS 26.0 27.5 dBm
Small-Signal Gain SSG VDS = 5.0V; IDS = 50% IDSS 15.5 17 dB
Power-Added Efficiency
POUT = P1dB
PAE VDS = 5.0V; IDS = 50% IDSS 50 %
Noise Figure NF VDS = 5.0V; IDS = 50% IDSS 1.2 1.5 dB
VDS = 5.0V; IDS = 50% IDSS
Matched for best P1dB
38 40
Output Third-Order Intercept Point
(from 15 to 5 dB below P1dB)
IP3
Matched for best IP3 at 50% IDSS 42
dBm
Saturated Drain-Source Current IDSS VDS = 1.3 V; VGS = 0 V 375 465 550 mA
Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 750 mA
Transconductance GMVDS = 1.3 V; VGS = 0 V 400 mS
Gate-Source Leakage Current IGSO VGS = -5 V 1 15 μA
Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 1.5 mA 0.7 1.0 1.3 V
Gate-Source Breakdown Voltage |VBDGS| IGS = 1.5 mA 12 16 V
Gate-Drain Breakdown Voltage |VBDGD| IGD = 1.5 mA 12 16 V
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• ABSOLUTE MAXIMUM RATINGS1
Parameter Symbol Test Conditions Min Max Units
Drain-Source Voltage VDS -3V < VGS < +0V 8 V
Gate-Source Voltage VGS 0V < VDS < +8V -3 V
Drain-Source Current IDS For VDS > 2V IDSS mA
Gate Current IGForward or reverse current 15 mA
RF Input Power2PIN Under any acceptable bias state 350 mW
Channel Operating Temperature TCH Under any acceptable bias state 175 ºC
Storage Temperature TSTG Non-Operating Storage -40 150 ºC
Total Power Dissipation PTOT See De-Rating Note below 2.3 W
Gain Compression Comp. Under any bias conditions 5 dB
Simultaneous Combination of Limits3
2 or more Max. Limits 80 %
1TAmbient = 22°C unless otherwise noted 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
• Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
• Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where:
P
DC: DC Bias Power
PIN: RF Input Power
POUT: RF Output Power
• Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 2.3W – (0.015W/°C) x TPACK
where TPACK = source tab lead temperature above 22
°
C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C source lead temperature: PTOT = 2.3W – (0.015 x (65 – 22)) = 1.66W
• HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• BIASING GUIDELINES
¾ Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD1500SOT89.
¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 2.6 Ω for a 50% of IDSS operating point.
¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%
to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3
performance.
• PACKAGE OUTLINE
(dimensions in mm)
PCB Foot Print
Units in inches
All information and specifications subject to change without notice.
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• TYPICAL TUNED RF PERFORMANCE
Power Transfer Characteristic
13.00
15.00
17.00
19.00
21.00
23.00
25.00
27.00
29.00
-2.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00
Input Power (dBm)
Output Power (dBm)
-.50
.00
.50
1.00
1.50
2.00
2.50
3.00
3.50
Gain Compression (dB)
Pout Comp Point
Drain E fficiency and PAE
.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
-2.00 0.00 2.00 4.00 6.00 8.00 10.00 12.00 14.00 16.00
Input Power (dBm)
PAE (%)
.00%
10.00%
20.00%
30.00%
40.00%
50.00%
60.00%
70.00%
Drain Efficiency (%)
PAE Eff.
Typical power, efficiency, and intermodulation performance is shown above. The devices were
biased nominally at VDS = 5V, IDS = 50% of IDSS, at a test frequency of 2 GHz. The test devices
were tuned (input and output tuning) for maximum output power at 1dB gain compression.
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
Typical Intermodulation Performance
VDS = 5V IDS = 50% IDSS at f = 1.85GHz
15.00
17.00
19.00
21.00
23.00
25.00
-1.00 1.00 3.00 5.00 7.00 9.00 11.00
Input Power (dBm)
Output Power (dBm)
-55.00
-50.00
-45.00
-40.00
-35.00
-30.00
-25.00
-20.00
-15.00
-10.00
3rd Oder IM Poroducts (dBc)
Pout Im3, dBc
Note: pHEMT devices exhibit non-classical intermodulation performance, with equivalent IPvalues
exceeding 14 dB above P1dB. This IMD enhancement is affected by the quiescent bias current, the
Drain-Source voltage, and the tuning or matching applied to the device.
Maximum Stable Gain & S21
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8
Frequency (GHz)
FPD1500SOT89 5V / 50%IDSS
0
5
10
15
20
25
30
35
Mag S21 & MSG
MSG
S21
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5V, IDS = 50% IDSS)
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
1850 MHz
Contours swept with a constant
input power, set so that nominal
P1dB is achieved at the point of
optimum output match.
Input (Source plane) Γs:
0.74 ∠ 168.2º
0.15 + j0.1 (normalized)
7.5 + j5.0 Ω
Nominal IP3 performance is
obtained with this input plane
match, and the output plane
match as shown.
900 MHz
Contours swept with a constant
input power, set so that nominal
P1dB is achieved at the point of
optimum output match.
Input (Source plane) Γs:
0.67 ∠ 103.6º
0.30 + j0.74 (normalized)
15 + j37.0 Ω
Nominal IP3 performance is
obtained with this input plane
match, and the output plane
match as shown.
01.
0
1.
0
-
1.
0
10
.0
1
0.0
-
10.0
5.
0
5
.0
-
5.0
2.
0
2.
0
-
2.
0
3.
0
3
.0
-
3.0
4.
0
4
.0
-
4.0
0.
2
0.2
-0.2
0.
4
0.4
-0.4
0.
6
0.
6
-
0.
6
0.
8
0.
8
-
0.
8
Swp Max
123
Swp Min
1
28dBm
26dBm
25dBm
24dBm
23dBm
22dBm
27dBm
01.
0
1.
0
-
1.
0
10
.0
1
0.0
-
10.0
5.
0
5
.0
-
5.0
2.
0
2.
0
-
2.
0
3.
0
3
.0
-
3.0
4.
0
4
.0
-
4.0
0.
2
0.2
-0.2
0.
4
0.4
-0.4
0.
6
0.
6
-
0.
6
0.
8
0.
8
-
0.
8
Swp Max
159
Swp Min
1
28dBm
26dBm
25dBm
24dBm
23dBm
22dBm
27dBm
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• TYPICAL SCATTERING PARAMETERS (50Ω SYSTEM)
See Website “More Info” for S-parameter design files.
0
1.0 1.0-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
FPD1500SOT89 5V / 50%IDSS
Swp Max
8GHz
Swp Min
0.5GHz
S11
1 GHz
1.5 GHz
2 GHz
2.5 GHz
3 GHz
3.5 GHz
4 GHz
5 GHz 6 GHz
7 GHz
01.
0
1.
0
-
1.
0
10
.0
1
0.0
-
10.0
5.
0
5
.0
-
5.0
2.
0
2.
0
-
2.
0
3.
0
3
.0
-
3.0
4.
0
4
.0
-
4.0
0.
2
0.2
-0.2
0.
4
0.4
-0.4
0.
6
0.
6
-
0.
6
0.
8
0.
8
-
0.
8
FPD1500SOT89 5V / 50%IDSS Swp Max
8GHz
Swp Min
0.5GHz
S22
1 GHz
2 GHz
3 GHz
4 GHz
5 GHz 6 GHz 7 GHz
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• TYPICAL I-V CHARACTERISTICS
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source
voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which
would normally distort the current measurement (this effect has been filtered from the I-V curves
presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements,
even in stabilized circuits.
Recommendation: Traditionally a device’s IDSS rating (IDS at VGS = 0V) was used as a predictor of
RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain
compression). For pHEMTs it can be shown that there is no meaningful statistical correlation
between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression
fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary
with the quiescent operating point IDS.
DC IV Curves FPD1500SOT89
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Source Voltage (V)
Drain-Source Current (A)
VG=-1.5V
VG-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.5V
VG=-0.25V
VG=0V
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• REFERENCE DESIGNS (0.9 & 1.85GHZ)
Frequency GHz 0.9 1.85
Gain dB 20 16
P1dB dBm 27 27
IP3 dBm 38 40
S11 dB -5 -9
S22 dB -15 -14
Vd V 5 5
Vg V -0.4 to -0.6 -0.4 to -0.6
Id mA 200 200
Component Values
Component 0.9GHz 1.85GHz
Lg 47nH 27nH
Ld 47nH 27nH
L1 12nH 1.5nH
L2 4.7nH 4.7nH
C1 5.6pF 2.2pF
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu
on both sides
● Negative gate voltage required to be established before drain bias
● Use test clips at the bias vias at the top and bottom of the board for biasing
Eval Board Layout
33pF
Lg
33pF L1
0.01uF 20O
L2
+1.0uF
Q1 C1
33pF
Ld
33pF
0.01uF +
Vg Vd
Eval board Schematic
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
CAP
C=
ID=33 pF
C1
CAP
C=
ID=C1 pF
C4
CAP
C=
ID=33 pF
C5
IND
L=
ID=L2 nH
L1
IND
L=
ID=Ld nH
L2
12
3
MTEE
W3=
W2=
W1=
ID=
105 mil
98 mil
98 mil
TL1
MLIN
L=
W=
ID=
30 mil
10 mil
TL4
12
3
MTEE
W3=
W2=
W1=
ID=
40 mil
98 mil
98 mil
TL5
MLIN
L=
W=
ID=
153 mil
35 mil
TL6
MLIN
L=
W=
ID=
60 mil
73 mil
TL2
DCVS
V=
ID=5 V
V1
CAP
C=
ID=33 pF
C2
CAP
C=
ID=33 pF
C6
IND
L=
ID=L1 nH
L3
IND
L=
ID=Lg nH
L4
MLIN
L=
W=
ID=
30 mil
10 mil
TL11
12
3
MTEE
W3=
W2=
W1=
ID=
40 mil
98 mil
98 mil
TL12
MLIN
L=
W=
ID=
95 mil
35 mil
TL13
DCVS
V=
ID=-0.5 V
V2
MLIN
L=
W=
ID=
60 mil
73 mil
TL7
MLIN
L=
W=
ID=
105 mil
98 mil
TL9
RES
R=
ID=20 Ohm
R1
1
2
SUBCKT
NET=
ID="FPD1500SOT89"
S1
PORT
Z=
P=50 Ohm
2
PORT
Z=
P=50 Ohm
1
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• REFERENCE DESIGNS (2.4 & 2.6GHZ)
Frequency GHz 2.4 2.6
Gain dB 12 11.5
P1dB dBm 28 27.5
IP3 dBm 41 40
S11 dB -6 -16
S22 dB -5 -5
Vd V 5 5
Vg V -0.4 to -0.6 -0.4 to -0.6
Id mA 200 200
Component Values
Component 2.4GHz 2.6GHz
Lg 22nH 18nH
Ld 22nH 18nH
L1 1.0nH Tab
L2 3.3nH 3.9nH
C1 1.8pF 1.0pF
C2 1.0pF 1.0pF
Eval board material - 31mil thick FR4 with 1/2 Ounce Cu
on both sides
● Negative gate voltage required to be established before drain bias
● Use test clips at the bias vias at the top and bottom of the board for biasing
Eval Board Layout
20O
33pF
C1
0.01uF
Lg
L1 33pF
C2
L2
33pF
Q1
33pF +
Ld
0.01uF +1.0uF
Vg Vd
Eval board Schematic
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
CAP
C=
ID=33 pF
C1
CAP
C=
ID=C2 pF
C4
CAP
C=
ID=33 pF
C5
IND
L=
ID=L2 nH
L1
IND
L=
ID=Ld nH
L2
12
3
MTEE
W3=
W2=
W1=
ID=
105 mil
98 mil
98 mil
TL1
MLIN
L=
W=
ID=
30 mil
10 mil
TL4
12
3
MTEE
W3=
W2=
W1=
ID=
40 mil
98 mil
98 mil
TL5
MLIN
L=
W=
ID=
153 mil
35 mil
TL6
MLIN
L=
W=
ID=
60 mil
73 mil
TL2
DCVS
V=
ID=5 V
V1
CAP
C=
ID=33 pF
C2
CAP
C=
ID=33 pF
C6
IND
L=
ID=L1 nH
L3
IND
L=
ID=Lg nH
L4
MLIN
L=
W=
ID=
30 mil
10 mil
TL11
12
3
MTEE
W3=
W2=
W1=
ID=
40 mil
98 mil
98 mil
TL12
MLIN
L=
W=
ID=
95 mil
35 mil
TL13
DCVS
V=
ID=-0.5 V
V2
MLIN
L=
W=
ID=
60 mil
73 mil
TL7
RES
R=
ID=20 Ohm
R1
12
3
MTEE
W3=
W2=
W1=
ID=
105 mil
98 mil
98 mil
TL3
CAP
C=
ID=C1 pF
C3
1
2
SUBCKT
NET=
ID="FPD1500SOT89"
S1
PORT
Z=
P=50 Oh
m
2
PORT
Z=
P=50 Ohm
1
Fax: +1 408 850-5766 Email: sales@filcsi.com
FPD1500SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMTT
• STATISTICAL SAMPLE OF RF PERFORMANCE
Sm all Sign al Ga i n
0
2000
4000
6000
8000
10000
12000
14000
13 14 15 16 17 18
Gain (dB)
Count
Noise Figur e
0
1000
2000
3000
4000
5000
6000
0.6 0.7 0.8 0.9 1 1.1 1.2 1.3
NF ( dB)
Count
Output Power at 1dB Gain Compression
0
2000
4000
6000
8000
10000
12000
14000
23 24 25 26 27 28
P1dB (dBm)
Count
Output 3rd-Order Intercept Point
0
1000
2000
3000
4000
5000
6000
30 32 34 36 38 40 42 44
IP3 (dBm)
Count
The histograms above represent a sample of over 20,000 representative devices. The devices were
tested by a high-speed automatic test system, in a matched circuit based on the EB1500SOT89AA
Evaluation Board design (see the Website for a schematic). This circuit is a dual-bias single-pole
lowpass topology, and the devices were biased at VDS = 4.5V, IDS = 120mA. The performance data is
summarized below:
Parameter Median Standard
Deviation
Test Limit CPK
Small-Signal Gain 15.5 0.20 14.5 1.7
Noise Figure 0.91 0.03 1.20 3.2
Output Power (P1dB) 25.2 0.25 24.5 0.93
3rd-Order Intercept 38.7 1.1 36.5 0.67
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised11/11/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
