Features 4.5 to 18 V Operating Range 5 A Peak Sink/Source at V DD = 12 V 4.3 A Sink / 2.8 A Source at V OUT = 6 V TTL Input Thresholds Tw o Versions of Dual Independent Drivers: Description Industry-Standard Pin Out Dual Inverting (FAN3213) Dual Non-Inverting (FAN3214) Internal Resistors Turn Driver Off If No Inputs MillerDriveTM Technology 12 ns / 9 ns Typical Rise/Fall Times w ith 2.2 nF Load Typical Propagation Delay Under 20 ns Matched w ithin 1 ns to the Other Channel Double Current Capability by Paralleling Channels Standard SOIC-8 Package Rated from -40C to +125C Ambient Automotive Qualified to AEC-Q100 (F085 Version) The FA N3213 and FAN3214 dual 4 A gate drivers are designed to drive N-channel enhancement- mode MOSFETs in low -side sw itching applications by providing high peak current pulses dur ing the short sw itching intervals. They are both available w ith TTL input thresholds. Internal circuitry provides an undervoltage lockout function by holding the output LOW until the supply voltage is w ithin the operating range. In addition, the drivers feature matched internal propagation delays betw een A and B channels for applications requir ing dual gate drives w ith critical timing, such as synchronous rectifiers. This also enables connecting tw o drivers in parallel to effectively double the current capability driving a single MOSFET. The FA N3213/14 drivers incorporate Miller DriveTM architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize sw itching loss, w hile providing railto-rail voltage sw ing and reverse current capability. The FAN3213 offers two inverting drivers and the FA N3214 offers tw o non-inverting drivers. Both are offered in a standard 8-pin SOIC package. Applications Sw itch-Mode Pow er Supplies High-Efficiency MOSFET Sw itching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control Automotive-Qualified Systems (F085 version) NC 1 INA 2 A GND 3 INB 4 B 8 NC NC 1 7 OUTA INA 2 6 VDD GND 3 5 OUTB INB 4 FAN3213 8 NC A 7 OUTA 6 VDD B 5 OUTB FAN3214 Figure 1. Pin Configurations (c) 2008 Semiconductor Components Industries, LLC. October-2017, Rev.2 Publication Order Number: FAN3214 /D FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers FAN3213 / FAN3214 Dual-4 A, High-Speed, Low-Side Gate Drivers Part Number Logic FAN3213TMX Dual Inverting Channels FAN3214TMX Dual Non-Inverting Channels (1) Dual Inverting Channels (1) Dual Non-Inverting Channels FAN3213TMX_F085 FAN3214TMX_F085 Input Threshold Package Packing Method Quantity per Reel TTL SOIC-8 Tape & Reel 2,500 Note: 1. Qualified to AEC-Q100 Package Outlines 1 8 2 7 3 6 4 5 Figure 2. SOIC-8 (Top View ) Thermal Characteristics(2) Package 8-Pin Small Outline Integrated Circuit (SOIC) JL(3) JT(4) JA(5) JB(6) JT(7) Unit 38 29 87 41 2.3 C/W Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3. Theta_JL (JL): Thermal resistance betw een the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 4. Theta_JT (JT): Thermal resistance betw een the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 5. Theta_JA (JA): Thermal resistance betw een junction and ambient, dependent on the PCB design, heat sinking, and airflow . The value given is for natural convection w ith no heatsink, using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 6. Psi_JB (JB): Thermal characterization parameter providing correlation betw een semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 5. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 7. Psi_JT (JT): Thermal characterization parameter providing correlation betw een the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 5. www.onsemi.com 2 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Ordering Information NC 1 INA 2 GND 3 INB 4 A B 8 NC NC 1 7 OUTA INA 2 6 VDD GND 3 5 OUTB INB 4 FAN3213 A B 8 NC 7 OUTA 6 VDD 5 OUTB FAN3214 Figure 3. Pin Configurations (Repeated) Pin Definitions Pin Name Pin Description 1 NC No Connect. This pin can be grounded or left floating. 2 INA Input to Channel A. 3 GND Ground. Common ground reference for input and output circuits. 4 INB Input to Channel B. 5 (FAN3213) OUTB Gate Drive Output B (inverted from the input): Held LOW unless required input is present and V DD is above UVLO threshold. 5 (FAN3214) OUTB Gate Drive Output B: Held LOW unless required input(s) are present and V DD is above UVLO threshold. 6 VDD Supply Voltage. Provides pow er to the IC. 7 (FAN3213) OUTA Gate Drive Output A (inverted from the input): Held LOW unless required input is present and V DD is above UVLO threshold. 7 (FAN3214) OUTA Gate Drive Output A: Held LOW unless required input(s) are present and V DD is above UVLO threshold. 8 NC No Connect. This pin can be grounded or left floating. Output Logic FAN3213 (x=A or B) INx INx OUTx 0 1 (9) 0 1 FAN3214 (x=A or B) 0 1 1 0 Note: 9. Default input signal if no external connection is made. www.onsemi.com 3 OUTx (9) FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Pin Configurations NC 1 8 NC INA 2 7 OUTA 100k 100k UVLO GND 3 6 VDD VDD_OK INB 4 5 OUTB 100k 100k Figure 4. FAN3213 Block Diagram NC 1 8 NC INA 2 7 OUTA 100k 100k UVLO GND 3 6 VDD VDD_OK INB 4 5 OUTB 100k 100k Figure 5. FAN3214 Block Diagram www.onsemi.com 4 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Block Diagrams Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.0 V V DD VDD to PGND V IN INA and INB to GND GND - 0.3 V DD + 0.3 V OUTA and OUTB to GND GND - 0.3 V DD + 0.3 V V OUT TL Lead Soldering Temperature (10 Seconds) TJ Junction Temperature TSTG Storage Temperature +260 C -55 +150 C -65 +150 C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet spec ifications. ON Semiconductor does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter V DD Supply Voltage Range V IN Input Voltage INA and INB TA Operating Ambient Temperature www.onsemi.com 5 Min. Max. Unit 4.5 18.0 V 0 V DD V -40 +125 C FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Absolute Maximum Ratings Unless otherw ise noted, V DD=12 V, TJ =-40C to +125C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit 18.0 V 0.70 0.95 mA Supply FAN321xT V DD Operating Range 4.5 IDD Supply Current, Inputs Not Connected V ON Turn-On Voltage INA=V DD, INB=0 V 3.5 3.9 4.3 V V OFF Turn-Off Voltage INA=V DD, INB=0 V 3.3 3.7 4.1 V 0.70 1.20 mA FAN321xTMX_F085 (Automotive-Qualified Versions) IDD V ON V OFF Supply Current, Inputs Not Connected (12) Turn-On Voltage (12) INA=V DD, INB=0 V 3.3 3.9 4.5 V Turn-Off Voltage (12) INA=V DD, INB=0 V 3.1 3.7 4.3 V 0.8 1.2 Inputs V IL_T INx Logic Low Threshold V IH_T INx Logic High Threshold 1.6 V 2.0 V FAN321xT IIN+ Non-Inverting Input IN from 0 to V DD -1.5 175.0 A IIN- Inverting Input IN from 0 to V DD -175.0 1.5 A 0.8 V 1.5 A V HYS_T TTL Logic Hysteresis Voltage 0.2 0.4 FAN321xTMX_F085 (Automotive-Qualified Versions) Non-inverting Input Current (12) IN=0 V IINx_T Non-inverting Input Current (12) IN=V DD 90 120 175 A IINx_T Inverting Input Current (12) IN=0 V -175 -120 -90 A Inverting Input Current (12) IN=V DD -1.5 1.5 A 0.8 V IINx_T IINx_T V HYS_T -1.5 (12) TTL Logic Hysteresis Voltage 0.1 0.4 Output ISINK OUT Current, Mid-Voltage, Sinking (10) ISOURCE OUT Current, Mid-Voltage, Sourcing IPK_SINK OUT Current, Peak, Sinking IPK_SOURCE IRVS TDEL.MATCH (10) (10) OUT Current, Peak, Sourcing (10) Output Reverse Current Withstand OUTx at V DD/2, CLOAD=0.22 F, f=1 kHz 4.3 A OUTx at V DD/2, CLOAD=0.22 F, f=1 kHz -2.8 A CLOAD=0.22 F, f=1 kHz 5 A CLOAD=0.22 F, f=1 kHz -5 A 500 mA (10) Propagation Matching Betw een Channels INA=INB, OUTA and OUTB at 50% Point 2 4 ns Continued on the following page... www.onsemi.com 6 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Electrical Characteristics Unless otherw ise noted, V DD=12 V, TJ =-40C to +125C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit FAN321xT tRISE tFALL tD1, tD2 Output Rise Time Output Fall Time (11) (11) Output Propagation Delay, TTL Inputs (11) CLOAD=2200 pF 12 20 ns CLOAD=2200 pF 9 17 ns 17 29 ns CLOAD=2200 pF 12 22 ns CLOAD=2200 pF 9 18 ns 17 32 ns 0 - 5 V IN, 1 V/ns Slew Rate 9 FAN321xTMX_F085 (Automotive-Qualified Versions) tRISE tFALL tD1, tD2 V OH V OL Output Rise Time Output Fall Time (11)(12) (11)(12) Output Propagation Delay, TTL Inputs 0 - 5 V IN, 1 V/ns Slew Rate 9 (12) V OH=V DD-V OUT, IOUT=-1 mA 15 35 mV (12) IOUT=1 mA 10 25 mV High Level Output Voltage Low Level Output Voltage (11)(12) Notes: 10. Not tested in production. 11. See Timing Diagrams of Figure 6 and Figure 7. 12. Apply only to Automotive Version(FAN321xTMX_F085) 90% 90% Output Output 10% Input 10% VINH Input VINL tD1 tD2 tRISE VINH VINL tD1 tFALL Figure 6. Non-Inverting Tim ing Diagram tD2 tFALL Figure 7. Inverting Tim ing Diagram www.onsemi.com 7 tRISE FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Electrical Characteristics (Continued) Typical characteristics are provided at TA=25C and V DD=12 V unless otherw ise noted. Figure 8. IDD (Static) vs. Supply Voltage (12) Figure 9. IDD (Static) vs. Tem perature (12) Figure 10. IDD (No Load) vs. Frequency Figure 11. IDD (2.2 nF Load) vs. Frequency Figure 12. Input Thresholds vs. Supply Voltage Figure 13. Input Thresholds vs. Tem perature www.onsemi.com 8 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25C and V DD=12 V unless otherw ise noted. UVLO Threshold vs. Tem perature Figure 14. Propagation Delay vs. Supply Voltage Figure 15. Propagation Delay vs. Supply Voltage Figure 16. Propagation Delays vs. Tem perature Figure 17. Propagation Delays vs. Tem perature www.onsemi.com 9 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25C and V DD=12 V unless otherw ise noted. Figure 18. Fall Tim e vs. Supply Voltage Figure 19. Rise Tim e vs. Supply Voltage Figure 20. Rise and Fall Tim es vs. Tem perature Figure 21. Rise/Fall Waveform s w ith 2.2 nF Load Figure 22. Rise/Fall Waveform s w ith 10 nF Load www.onsemi.com 10 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25C and V DD=12 V unless otherw ise noted. Figure 23. Quasi-Static Source Current (13) w ith V DD=12 V Figure 24. Quasi-Static Sink Current w ith V DD=12 V Figure 25. Quasi-Static Source Current (14) w ith V DD=8 V Figure 26. Quasi-Static Sink Current w ith V DD=8 V (13) (14) Notes: 13. For any inverting inputs pulled low , non-inverting inputs pulled high, or outputs driven high; static IDD increases by the current flow ing through the corresponding pull-up/dow n resistor show n in Figure 4 and Figure 5. 14. The initial spike in each current w aveform is a measurement artifact caused by the stray inductance of the current-measurement loop. Test Circuit VDD 470F Al. El. 4.7F ceramic Current Probe LECROY AP015 IN 1kHz IOUT 1F ceramic VOUT CLOAD 0.22F Figure 27. Quasi-Static IOUT / V OUT Test Circuit www.onsemi.com 11 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics VDD Input Thresholds The FAN3213 and the FAN3214 drivers consist of tw o identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. The input thresholds meet industry-standard TTL- logic thresholds independent of the V DD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels per mit the inputs to be driven from a range of input logic s ignal levels for w hich a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges w ith a slew rate of 6 V/s or faster, so a rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the dr iver input, causing erratic operation. Static Supply Current In the IDD (static) typical performance characteristics show n in Figure 8 and Figur e 9, each curve is produced w ith both inputs floating and both outputs LOW to indicate the low est static IDD current. For other states, additional current flow s through the 100 k resistors on the inputs and outputs show n in the block diagram of each part (see Figure 4 and Figure 5). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDriveTM Gate Drive Technology Input stage VOUT Figure 28. MillerDriveTM Output Architecture Under-Voltage Lockout The FAN321x startup logic is optimized to drive groundreferenced N-channel MOSFETs w ith an under-voltage lockout ( UVLO) function to ensure that the IC starts up in an orderly fashion. When V DD is rising, yet below the 3.9 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts dow n. This hysteresis helps prevent chatter w hen low V DD supply voltages have noise from the pow er sw itching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver w ould turn the P-channel MOSFET on w ith V DD below 3.9 V. FA N3213 and FA N3214 gate drivers incorporate the Miller DriveTM architecture show n in Figure 28. For the output stage, a combination of bipolar and MOS devices provide large currents over a w ide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT sw ings betw een 1/3 to 2/3 V DD and the MOS devices pull the output to the HIGH or LOW rail. VDD Bypass Capacitor Guidelines The purpose of the Miller DriveTM architecture is to speed up sw itching by providing high current during the Miller plateau region w hen the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the V DD supply to 5%. This is often achieved w ith a value 20 times the equivalent load capacitance CEQV, defined here as QGATE/V DD. Ceramic capacitors of 0.1 F to 1 F or larger are common choices, as are dielectrics, such as X5R and X7R, w ith good temperature characteristics and high pulse current capability. For applications w ith zero voltage sw itching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast sw itching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is sw itched ON. The output pin slew rate is determined by V DD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slow er rise or fall time at the MOSFET gate is needed. To enable this IC to turn a device ON quickly, a local high-frequency bypass capacitor, CBYP, w ith low ESR and ESL should be connected betw een the VDD and GND pins w ith minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 F to 47 F commonly found on driver and controller bias circuits. If circuit noise affects normal operation, the value of CBYP may be increased, to 50-100 times the CEQV, or CBYP may be split into tw o capacitors. One should be a larger value, based on equivalent load capacitance, and the other a s maller value, such as 1-10 nF mounted closest to the VDD and GND pins to carry the higherfrequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are sw itching simultaneously, the combined peak current sourced from the CBYP w ould be tw ice as large as w hen a single channel is sw itching. www.onsemi.com 12 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Applications Information The FA N3213 and FAN3214 gate dr ivers incorporate fast-reacting input circuits, short propagation delays, and pow erful output stages capable of delivering current peaks over 4 A to facilitate voltage transition times from under 10 ns to over 150 ns. The follow ing layout and connection guidelines are strongly recommended: Figure 30 show s the current path w hen the gate dr iver turns the MOSFET OFF. Ideally, the driver shunts the current directly to the source of the MOSFET in a s mall circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. VDD Keep high-current output and pow er ground paths separate from logic input signals and signal ground paths. This is especially critical for TTL-level logic thresholds at driver input pins. CBYP FAN321x Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed sw itching, w hile reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. If the inputs to a channel are not externally connected, the internal 100 k resistors indicated on block diagrams command a low output. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output sw itching. PWM Figure 30. Current Path for MOSFET Turn-Off Many high-speed pow er circuits can be susceptible to noise injected from their ow n output or other external sources, possibly causing output retriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts w ith long input or output leads. For best results, make connections to all pins as short and direct as possible. FAN3213 and FAN3214 are pin-compatible w ith many other industry-standard drivers. The turn-on and turn-off current paths should be minimized, as discussed in the follow ing section. Figure 29 show s the pulsed gate drive current path when the gate dr iver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flow s through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses w ithin this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. VDD VDS VDS CBYP FAN321x PWM Figure 29. Current Path for MOSFET Turn-On www.onsemi.com 13 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Layout and Connection Guidelines At pow er-up, the driver output remains LOW until the V DD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises w ith V DD until steady-state V DD is reached. The non-inverting operation illustrated in Figure 31 shows that the output remains LOW until the UVLO threshold is reached, then the output is in-phase w ith the input. The inverting configuration of startup w aveforms are show n in Figure 32. With IN+ tied to V DD and the input signal applied to IN-, the OUT pulses are inverted w ith respect to the input. At pow er-up, the inverted output remains LOW until the V DD voltage reaches the turn-on threshold, then it follow s the input w ith inverted phase. VDD VDD Turn-on threshold Turn-on threshold IN- IN- IN+ IN+ (VDD) OUT OUT Figure 31. Non-Inverting Startup Waveform s www.onsemi.com 14 Figure 32. Inverting Startup Waveform s FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Operational Waveforms Gate dr ivers used to sw itch MOSFETs and IGBTs at high frequencies can dissipate s ignificant amounts of pow er. It is important to deter mine the driver pow er dissipation and the resulting junction temperature in the application to ensure that the part is operating w ithin acceptable temperature limits. The total pow er dissipation in a gate dr iver is the sum of tw o components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) PGATE ( Gate Driving Loss): The most significant pow er loss results from supplying gate current (charge per unit time) to sw itch the load MOSFET on and off at the sw itching frequency. The pow er dissipation that results from dr iving a MOSFET at a specified gatesource voltage, V GS, w ith gate charge, QG, at sw itching frequency, f SW, is determined by: PGATE = QG * V GS * f SW * n (2) w here n is the number of driver channels in use (1 or 2). PDYNAMIC (Dynamic Pre- Drive / Shoot-through Current): A pow er loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-dow n resistors. The internal current consumption ( IDYNAMIC) can be estimated using the graphs in Figure 10 of the Typical Perfor mance Characteristics to deter mine the current IDYNAMIC draw n from V DD under actual operating conditions: PDYNAMIC = IDYNAMIC * V DD * n To give a numerical example, assume for a 12 V V DD (Vibas) system, the synchronous rectifier sw itches of Figure 33 have a total gate charge of 60 nC at V GS = 7 V. Therefore, tw o devices in parallel w ould have 120 nC gate charge. At a sw itching frequency of 300 kHz, the total pow er dissipation is: PGATE = 120 nC * 7 V * 300 kHz * 2 = 0.504 W (5) PDYNAMIC = 3.0 mA * 12 V * 1 = 0.036 W (6) PTOTAL = 0.540 W (7) The SOIC-8 has a junction-to-board ther mal characterization parameter of JB = 42C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along w ith airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150C; w ith 80% derating, TJ w ould be limited to 120C. Rearranging Equation 4 deter mines the board temperature required to maintain the junction temperature below 120C: TB,MAX = TJ - PTOTAL * JB (8) TB,MAX = 120C - 0.54 W * 42C/W = 97C (9) (3) where n is the number of driver ICs in use. Note that n is usually be one IC even if the IC has tw o channels, unless tw o or more.driver ICs are in parallel to driv e a large load. Once the pow er dissipated in the driver is deter mined, the driver junction rise w ith respect to circuit board can be evaluated using the follow ing ther mal equation, assuming JB w as determined for a similar ther mal design (heat sinking and air flow ): TJ = PTOTAL * JB + TB (4) w here: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total pow er dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. www.onsemi.com 15 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Thermal Guidelines VIN VOUT PWM Timing/ Isolation 1 8 2 7 3 6 4 5 FAN3214 Vbias A 2 3 GND FAN3214 4 Figure 33. High-Current Forw ard Converter w ith Synchronous Rectification VIN 8 1 Figure 34. QC QA QD QB 7 VDD 6 B 5 Center-Tapped Bridge Output w ith Synchronous Rectifiers FAN3214 PWM-A FAN3225C SR-1 PWM-B Secondary Phase Shift Controller SR-2 PWM-C FAN3225C PWM-D Figure 35. Secondary Controlle d Full Bridge w ith Current Doubler Output, Synchronous Rectifiers (Sim plified) www.onsemi.com 16 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Application Diagrams Type Related Products Part Num ber (15) Gate Drive (Sink/Src) Single 1 A FAN3111C +1.1 A / -0.9 A Single 1 A FAN3111E +1.1 A / -0.9 A Single 2 A FAN3100C +2.5 A / -1.8 A Single 2 A FAN3100T Single 2 A FAN3180 +2.5 A / -1.8 A +2.4 A / -1.6 A Input Threshold CMOS External (16) Logic Single Channel of Dual-Input/Single-Output Package SOT23-5, MLP6 Single Non-Inverting Channel with External Reference SOT23-5, MLP6 CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 TTL Single Non-Inverting Channel + 3.3 V LDO SOT23-5 Dual 2 A FAN3216T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8 Dual 2 A FAN3217T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8 Dual 2 A FAN3226C +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3226T TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3227C +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3227T TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3228C +2.4 A / -1.6 A Dual 2 A FAN3228T Dual 2 A FAN3229C +2.4 A / -1.6 A Dual 2 A FAN3229T Dual 2 A +2.4 A / -1.6 A +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 FAN3268T +2.4 A / -1.6 A TTL 20 V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables SOIC8 Dual 2 A FAN3278T +2.4 A / -1.6 A TTL 30 V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables SOIC8 Dual 4 A FAN3213T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8 Dual 4 A FAN3214T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8 Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3223T TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3224T TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 Dual 4 A FAN3225T TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 CMOS Single Inverting Channel + Enable SOIC8, MLP8 TTL Single Inverting Channel + Enable SOIC8, MLP8 CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 +2.4 A / -1.6 A +4.3 A / -2.8 A +4.3 A / -2.8 A +4.3 A / -2.8 A Single 9 A FAN3121C +9.7 A / -7.1 A Single 9 A FAN3121T +9.7 A / -7.1 A Single 9 A FAN3122C +9.7 A / -7.1 A Single 9 A FAN3122T +9.7 A / -7.1 A Dual 12 A FAN3240 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 0 SOIC8 Dual 12 A FAN3241 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 1 SOIC8 Notes: 15. Typical currents w ith OUTx at 6 V and V DD=12 V. 16. Thresholds proportional to an externally supplied reference voltage. www.onsemi.com 17 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Table 1. 4.900.10 0.65 A (0.635) 8 5 B 1.75 6.000.20 PIN ONE INDICATOR 5.60 3.900.10 1 4 1.27 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.1750.075 0.220.03 C 1.75 MAX 0.10 0.420.09 OPTION A - BEVEL EDGE (0.86) x 45 R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: 8 0 SEATING PLANE 0.650.25 (1.04) DETAIL A A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M E) DRAWING FILENAME: M08Arev16 SCALE: 2:1 Figure 36. 8-Lead Sm all Outline Integrated Circuit (SOIC) www.onsemi.com 18 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Physical Dimensions FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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