LP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 Over Voltage Protection and Lock Out for D OR P PACKAGE 12V,5V,3.3V (TOP VIEW) Under Voltage Protection and Lock Out for 5 V and 3.3 V Fault Protection Output With Open-Drain Output Stage Open-Drain Power Good Output Signal for Power Good Input, 3.3 V and 5 V 300-ms Power Good Delay 75-ms Delay for 5-V and 3.3-V Power Supply Short-Circuit Turnon Protection 2.3-ms PSON Control to FPO Turnoff Delay 38-ms PSON Control Debounce 73-us Width Noise Deglitches Wide Supply Voltage Range From 4 V to 15V description The TPS3510 is designed to minimize external components of personal-computer switching power supply systems. It provides protection circuits, power good indicator, fault protection output (FPO) and PSON control. Over voltage protection (OVP) monitors 3.3 V, 5 V, and 12 V (12-V signal detects via Vpp pin). Under voltage protection (UVP) monitors 3.3 V and 5 V. When an OV or UV condition is detected, the power good output (PGO) is set to low and FPO is latched high. PSON from low to high resets the protection latch. UVP function is enabled 73 ms after PSON is set low and debounced. Furthermore, there is a 2.3-ms delay (and an additional 38-ms debounce) at turnoff. There is no delay during turnon. Power good feature monitors PGI, 3.3 V and 5 V and Issues a power good signal when the output is ready. The TPS3510 is characterized for operation from 40C to 85C. typical application 5Vsp NAN PGI : e PGO = 42V vv 0.5V $ a Pcl pco| Drop GND Vpp Uv a Vsp FPO vss} o 5V PSON PSON VS33 f 3.3V (From Motherboard) cls Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.LP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 FUNCTION TABLE Pa PSON | asvorsw |@svsv,ort2y| FPO | PGO <0.95V L no no L L <0.95V L no yes H a <0.95V L yes na L L 0.95 V=PGIl<1.15 V L no no L L 0.95 V<-PGIl<1.15 V L no yes H L 0.95 V=PGl<1.15 V L yes no H L PGI > 1.15 V L no no L H PGI > 1.15 V L no yes H L PGI > 1.15 V L yes no H L x H x x H [. x = don't care FPO =L means: fault IS NOT latched FPO = H means: fault IS latched PGO =L means: fault PGO = H means: NO faultLP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 functional block diagram Band-Gap Reference 1.15V 150-us Debounce and 4.8-ms Delay PGI Band-Gap Reference 0.95 V | | VpD ! | | 12V OV ! | ; | | I POR | | 2 ; | | - VS5 b. | | | | | | R : | 5V OV _ ! 5 7 FPO | T 73-us | e|- Debounce | ? | | | | 2 = | VS33 | | 73-us 2.3-Mms | | Debounce Delay VDD | : | | | | 38-ms | - | Debounce ! PSON | | | | | | | | | | | | | | | | | | | . PGO | 150-us | Debounce | | | | | | | | | | | |TPS3510 PC POWER SUPPLY SUPERVISORS timing diagram SLVS312 JULY 2000 LP7510 FPO PGI 12V PGO VDD PSON 3.3V.5V OccurLP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 Terminal Functions TERMINAL NAME NO. HO DESCRIPTION FPO 3 O Inverted fault protection output, open drain output stage (SND 2 Ground PGI | | Power good input PGO iO O Power good output, open drain output stage PSON 4 | | ON/OFF control VDD t | Supply voltage/12 V over-voltage protection input pin VWS33 oO | 3.3 V over/under-voltage protection VS5 6 | 5 V over/under-voltage protection detailed description power good and power good delay APC power supply is commonly designed to provide a power-good signal, which is defined by the computer manufacturers. PGO is a power-good signal and should be asserted high by the PC power supply to indicate that the 5-V and 3.3-V outputs are above the under-voltage threshold limit. At this time the converter should be able to provide enough power to ensure continuous operation within the specification. Conversely, when either the 5-V or the 3.3-V output voltages fall below the under-voltage threshold, or when ac power has been removed for a time sufficiently long so that power supply operation is no longer ensured, PGO should be de-asserted to a low state. Figure 1 represents the timing characteristics of the power good (PGQO), dc enable (PSON), and the 5 V/3.3 V supply rails. 5-V/3.3-V Output PGO Figure 1. Timing of PSON and PGO Although there is no requirement to meet specific timing parameters, the following signal timings are recommended: 2ms < t2 < 20 ms, 100 ms < t3 < 2000 ms, t4> 1ms,t5<10ms Furthermore motherboards should be designed to comply with the previously recommended timing. If timings other than these are implemented or required, this information should be clearly specified. The TPS3510 family of power-supply supervisors provides a power-good output (PGO) for the 3.3-V and 5-V supply voltage rails and a separate power-good input (PGI). An internal timer is used to generate a 300-ms power-good delay. If the voltage signals at PGI, VS33, and VS5 rise above the under-voltage threshold, theLP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 open-drain power-good output (PGO) goes high after a delay of 300 ms. When the PGI voltage or either the 3.3-V and 5-V power rails drops below the under-voltage threshold, PGO Is disabled immediately (after 150-us debounce). power supply remote on/off (PSON) and fault protect output (FPO) since the latest personal computer generation focuses on easy turnon and power saving functions, the PC power supply requires two characteristics. One is a dc power supply remote on/off function, the other is standby voltage to achieve very low power consumption of the PC system. Thus the main power needs to be shut down. The power supply remote on/off (PSON) is an active low signal that turns on all of the main power rails including 3.3 V,5 V,-5 V, 12 V, and 12 V power rails. When this signal is held high by the PC motherboard or left open circuited, the signal of the fault protect output (FPO) also goes high. Thus, the main power rails should not deliver current and should be held at 0 V. When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs of the main power rails should not deliver current but are held at O V. Toggling the power supply remote on/off (PSON) from low to high resets the fault-protection latch. During this fault condition only the standby power Is not affected. When PSON goes from high to low or low to high, the 38-ms debounce block is active to avoid a glitch on the input that disables/enables the FPO output. During this period the under-voltage function Is disabled for 75 ms to prevent turnon failure. At turnoff, there is an additional delay of 2.3 ms from PSON to FPO. Power should be delivered to the rails only ifthe PSON signal is held at ground potential, thus FPO is active-low. The FPO pin can be connected to 5 V (or up to 15 V) through a pullup resistor. under-voltage protection The TPS3510 provides under-voltage protection (UVP) for the 3.3-V and 5-V rails. When an under voltage condition appears at either one of the 3.3-V (VS33) or 5-V (VS5) input pins for more than 146 us, the FPO output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or Vop is removed. The need for under voltage protection is often overlooked in off-line switching power supply system design. But it is very important in battery-powered or hand-held equipment since the TTL or CMOS logic often results in malfunction. In flyback or forward-type off-line switching power supplies, usually designed for low power, the over-load protection design is very simple. Most of these types of power supplies are only sensing the input current for an overload condition. The trigger point needs to be set much higher than the maximum load in order to prevent false turnon. However, this causes one critical problem. If the connected load is larger than the maximum allowable load but smaller than the trigger point, the system always becomes overheated with failure and damage occurring. over-voltage protection The over voltage protection (OVP) of TPS3510 monitors 3.3 V, 5 V, and 12 V (12 V is sensed via the Vpp pin). When an over-voltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73 us, the FPO output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or Vpp Is removed. During fault conditions, most power supplies have the potential to deliver higher output voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages to be high enough to cause internal or external damage of the system. To protect the system under these abnormal conditions, it is common practice to provide over-voltage protection within the power supply.LP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 Because TTL and CMOS circuits are very vulnerable to over-voltages, it is becoming industry standard to provide overvoltage protection on all 3.3-V and 5-V outputs. However, not only the 3.3-V and 5-V rails for the logic circuits on the motherboard need to be protected, but also the 12-V peripheral devices such as the hard disk, floppy disk, and CD-ROM players etc., need to be protected. short-circuit power supply turnon During safety testing the power supply might have tied the output voltage direct to ground. If this happens during the normal operating, this is called a short-circuit or over-current condition. When it happens before the power supply turns on, this is called a short-circuit power supply turn on. It can happen during the design period, in the production line, at quality control inspection or at the end user. The TP53510 provides an under-voltage protection function with a 7/5-ms delay after PSON Is set low. absolute maximum ratings over operating free-air temperature (unless otherwise noted)T supply Volfage, Vpp (S6G NOE1) cccscccswenccecnees watis Matis seu Se ae SRR Reema 16 V GuIpUIWOHROE NG EPO cnimcsscccmcananemammmann Matha Matin ste amee ce amEREIACMMeRUMaMEaRaTe 16 V BO) cs aure REC ERRR ERG CE UR Ce SO ee RARE 8V AIVOMER BINS (SER NOE erm csurauns SAREE EM CEN ee eae eee aa Rt 0.3Vto 16 V CGninOUS TOTAL DOWEr CISSIPGHOW ecccsccscecammeam oe oN Ue Some woe see Dissipation Rating Table Operating free-air temperature fange, Ta. cscscsscances oan saan esme come come acemeemen 40C to 85C storage temperattire range, letg scvosnccnswsaesawan cin wien sim eewe Hews RemONm ENE 65C to 150C SOMETINEGTEMPEIAUNG: ccmemerccnca eGR REGEN EN CNN He Soke cote ane 260C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximumrated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to GND. DISSIPATION RATING TABLE PACKAGE Ta = 25C DERATING FACTOR Ta = 70C Ta = 85C POWER RATING ABOVE Ta = 25C POWER RATING POWER RATING P 1092 mW 8./4 mWIPC 699 mW 368 mW D 730 mW 9.64 mW/PC 46/7 mW 3/9 mW recommended operating conditions at specified temperature range MIN NOM MAX | UNIT supply voltage, Vop 4 15 V PSON, VS5, VS33 7 Input voltage, V) Vpp + 0.3V V (max = / V) Output voltage, Vo a V PGO T | FPO 20 Output sink current, lO. sink BGO 0 mA supply voltage nsing time, t, See Note 2 | ms Operating free-air temperature range, Ta 40 65 C NOTE 2: Vpp rising and falling slew rate must be less than 14 V/ms.LP7510 PC POWER SUPPLY SUPERVISORS TPS3510 SLVS312 JULY 2000 electrical characteristics over recommended operating conditions (unless otherwise noted) over-voltage protection PARAMETER TEST CONDITIONS MIN TYP MAX] UNIT VS33 Sf 3.9 4 Over-voltage threshold VS5 of 6.1 6.5 V Vpp 13.2 138 144 KG Leakage current (FPO) V(EPO) =a 5 WA VOL Low-level output voltage (FPO) Vop=2V, Isink =20 mA Of V Noise deglitch time OVP Vpp=5V 39 {3 110 LS PGI and PGO PARAMETER TEST CONDITIONS MIN TYP MAX] UNIT VPGI Input threshold voltage (PGI) pen htt I V PGI2 09 0.95 1 ViIT Under-voltage threshold vee z ae en V WS5 3.3 3.5 Sot lKG Leakage current (PGO) PGO=5V a WA VoL Low-level output voltage (PGO) Vop=4V. Isink = 10 mA 0.4 V Short-circuit protection delay 3.3 V5 AQ 5 114 ms ta Delay time Eee - Vop=2aV a an ma ms PGI to FPO 3.2 48 i PGI to PGO og 150 229 Noise deglitch time PGI to FPO Vop=5V 180 296 445 LS UVP to FPO 82 146 220 PSON control PARAMETER TEST CONDITIONS MIN TYP MAX | UNIT lj Input pullup current PSON =0V 120 WA, VIH High-level input voltage 2.4 V VIL Low-level input voltage 12 V th Debounce time (PSON) Vpp =5V 24 38 57] ms tao Delay time (PSON to FPO) Vpop=3V tht1.1 tht+2.3 tht+4 ms total device PARAMETER TEST CONDITIONS MIN TYP MAX] UNIT Ipp Supply current PSON =5V | mALP7510 1TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 Ipp Supply Current-pA Vo_ Low-Level Output Voltage V 400 300 200 100 I ook =; 2 I ho S o 300 TYPICAL CHARACTERISTICS SUPPLY CURRENT VS SUPPLY VOLTAGE PGI=1.4V PSON=5V 0 2.5 7.4 10 12.5 15 Vpp Supply Voltage - V Figure 2 LOW-LEVEL OUTPUT VOLTAGE (FPO) VS LOW-LEVEL OUTPUT CURRENT (FPO) Vpp=4V PSON = GND T a Ta =40C Ta =0c 0 20 60 80 100 120 lo. Low-Level Output Current -mA Figure 4 1} -Input Current uA Vo_~ Low-Level Output Voltage mV INPUT CURRENT (PSON) VS INFUT VOLTAGE (PSON) 20 , , Vop=4V 0 | 20 40 -60 28 Tp = -40C A Ta =O0C 100 i Ta = 25C Tn = 85C ~120 14094 a a 6 7 V)} - Input Voltage -V Figure 3 LOW-LEVEL OUTPUT VOLTAGE (FPO) VS LOW-LEVEL OUTPUT CURRENT (FPO) 800 ) VDD =4V J 700+ PSON =GND Exploded View ie 600 Ta = 85C 500 400 J. oe 300 5 Ta = 25C er Ta = -40C 200 Ta = 0C 100 0 0 5 10 15 20 25 lo, Low-Level Output Current-mA Figure 5LP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 TYPICAL CHARACTERISTICS LOW-LEVEL OUTPUT VOLTAGE (PGO) LOW-LEVEL OUTPUT VOLTAGE (PGO) VS VS LOW-LEVEL OUTPUT CURRENT (PGO) LOW-LEVEL OUTPUT CURRENT (PGO) a | 600 | Vpp=4V Vpp=4V PSON = GND PSON = GND 500- Exploded View Ta = 85C 400 300 40C 200 Vo_ Low-Level Output Voltage V Vo_ Low-Level Output Voltage mV 100 Ta = 0C 0 25 50 f5 100 125 150 0 5 40 15 20 loL Low-Level Output Current -mA lo, Low-Level Output Current - mA Figure 6 Figure / NORMALIZED SENSE THRESHOLD VOLTAGE VS FREE-AIR TEMPERATURE AT Vpop 1.001 : Vpp =4V PSON = GND ff f 0.999 / 0.998 0.997 0.996 / 0.995 Normalized Input Threshold Voltage VIT(TA)/VIT(25 c) 099440 -15 10 35 60 85 Ta, Free-Air Temperature - C Figure 8 10LP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 D (R-PDSO-G**) 14 PINS SHOWN MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE 0.050 (1,27) 0.020 (0,51) tf 0.014 (0,35) |-|.9.010 (0,26) (My) , 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) cle 00) 0.150 (3,81) ue ) 4 T cae vane + E 0.010 (0,25) 0.044 (1,12) 0.016 (0,40) we eeeeeEeeeee| PE LE LL Ly aE Seating Plane S| } 0.010 (0,25) | >| 0.004 (0,10 0.069 (1,75) MAX 0.004 (0,10) PINS * ; 7 DIM 0.197 | 0.344 | 0.394 A MAX (5.00) | (8.75) | (10,00) 0.189 | 0337 | 0.386 A MIN (4.80) | (8.55) | (9,80) 4040047/D 10/96 NOTES: A. Alllinear dimensions are in inches (millimeters). OoW Falls within JEDEC M3S-012 This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).LP7510 TPS3510 PC POWER SUPPLY SUPERVISORS SLVS312 JULY 2000 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 0.400 (10,60) + 9355 (0.02) 0.355 (9, A sacl 0.260 (6,60) 0.240 ome 10) 1 7 _ 0.070 (1,78) MAX 0.020 (0,51) MIN soo eal | | [ 0.015 (0,38) 0.200 : 08) MAX Gage Plane EL Seating Plane t 7 ae ea 0.010 (0,25) NOM ane 4 0420 192-4 0.100 (2,54) 0.430 (10,92) 0.021 (0,53) S sie 0.015 (0,38) py 0.010 (0,25) (| 4040082/D 05/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 For the latest package information, go to http://www.ti-com/sc/docs/package/pkq_info.him | 12