LIS3DHH s) MEMS motion sensor: three-axis digital output accelerometer du Applications ct( Datasheet - production data Pr o Precision inclinometer Platform and antenna stabilization se Leveling instruments Description re lea Ceramic cavity LGA-16 (5x5x1.7 mm) The LIS3DHH is an ultra-high-resolution and lownoise three-axis linear accelerometer. The LIS3DHH has a full scale of 2.5 g and is capable of providing the measured accelerations to the application through an SPI 4-wire digital interface. re Features 3-axis, 2.5 g full-scale -P Ultra-low noise performance: 45 g/Hz The sensing element is manufactured using a dedicated micromachining process developed by STMicroelectronics to produce inertial sensors and actuators on silicon wafers. s) Excellent stability over temperature (<0.4 mg/C) and time 16-bit data output 12-bit temperature data output ro Embedded FIFO (depth 32 levels) du Embedded temperature sensor ct( SPI 4-wire digital output interface as eP High shock survivability Extended operating temperature range (-40 C to +85 C) Pr er ele ECOPACK(R), RoHS and "Green" compliant The IC interface is manufactured using a CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LIS3DHH is available in a high-performance (low-stress) ceramic cavity land grid array (CC LGA) package and can operate within a temperature range of -40 C to +85 C. Table 1. Device summary Order codes Temperature range [C] Package Packaging LIS3DHHTR -40 to +85 CC LGA-16 (5x5x1.7 mm) Tape and reel October 2017 This is information on a product in full production. DocID030220 Rev 3 1/29 www.st.com Contents LIS3DHH Contents Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 7 ct( s) 1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 se 2.3 Pr o du 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . 11 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 re 4.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 s) -P 4.2.1 ct( FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ro du 5.1 as eP 5 re lea 3 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pr er 7.1 ele 6 2/29 7.2 CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.3 INT1_CTRL (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.4 INT2_CTRL (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.5 CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.6 CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7 OUT_TEMP_L (25h), OUT_TEMP_H (26h) . . . . . . . . . . . . . . . . . . . . . . . 24 DocID030220 Rev 3 LIS3DHH STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.9 OUT_X (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.10 OUT_Y (2Ah - 2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.11 OUT_Z (2Ch - 2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.12 FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.13 FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ct( du Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 LGA-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 se 8.1 ele as eP ro du ct( s) -P re re lea Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pr er 9 s) 7.8 Pr o 8 Contents DocID030220 Rev 3 3/29 29 List of tables LIS3DHH List of tables as eP ro du ct( s) -P re re lea se Pr o du ct( s) Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 CTRL_REG1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 INT1_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 INT1_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 INT2_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 INT2_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CTRL_REG5 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 FIFO_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIFO_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIFO mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 FIFO_SRC example: OVR/FSS details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Outer dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pr er ele Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. 4/29 DocID030220 Rev 3 LIS3DHH List of figures List of figures ele as eP ro du ct( s) -P re re lea se Pr o du ct( s) Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External asynchronous trigger to FIFO for Continuous-to-FIFO mode . . . . . . . . . . . . . . . . 18 Bypass-to-Continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External asynchronous trigger to FIFO for Bypass-to-Continuous mode . . . . . . . . . . . . . . 19 Continuous mode: FTH/FSS details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ceramic cavity LGA-16: package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . 27 Pr er Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. DocID030220 Rev 3 5/29 29 Pin description 1 LIS3DHH Pin description &RQQHFWWR*1' RUOHDYHXQFRQQHFWHG -P s) ct( &RQQHFWWR*1' du ,17 re ',5(&7,212)7+( '(7(&7$%/( $&&(/(5$7,216 ,17 6', 7239,(: &6 63& 723 9,(: re lea &RQQHFWWR*1' Pr o &RQQHFWWR*1' &RQQHFWWR*1' RUOHDYHXQFRQQHFWHG 6'2 ; se = < &RQQHFWWR*1' RUOHDYHXQFRQQHFWHG Figure 1. Pin connections &RQQHFWWR*1' *1' 9'' 9'',2 Name 1 SPC Clock line for SPI 4-wire interface (SPC) 2 SDI Serial data input (SDI) line for SPI 4-wire interface 3 SDO Serial data output (SDO) line for SPI 4-wire interface 4 CS 5 INT2 6 INT1 7 Vdd_IO 8 du ct( Function ro SPI chip-select line (CS) as eP Programmable interrupt 2 generated according to a configurable FIFO threshold in a dedicated register Programmable interrupt 1 generated according to a configurable FIFO threshold in a dedicated register Power supply for I/O pins Recommended power supply decoupling capacitor (100 nF) Power supply Recommended power supply decoupling capacitors (100 nF ceramic in parallel with 10 F aluminum) GND 0 V power supply Reserved Connect to GND Reserved Connect to GND 12 Reserved Connect to GND 13 Reserved Connect to GND 14 Reserved Connect to GND or leave unconnected 15 Reserved Connect to GND or leave unconnected 16 Reserved Connect to GND or leave unconnected 10 11 6/29 Vdd Pr er 9 s) Pin# ele Table 2. Pin description DocID030220 Rev 3 LIS3DHH Mechanical and electrical specifications Mechanical and electrical specifications 2.1 Mechanical characteristics s) 2 ct( @ Vdd = 2.8 V, T = 25 C unless otherwise noted. Parameter Test condition Min. Typ.(1) Max. Unit Measurement range(2) 2.5 So Sensitivity(3) 0.076 mg/digit 0.7 % mg Off TCOff Sensitivity change vs. temperature From -40 C to +85 C, delta from 25C Zero-g level offset accuracy(4) 20 Zero-g level change vs. From -40 C to +85 C, delta from 25 C temperature(5) Non linearity Best-fit straight line Zgn Zero-g noise density FS = 2.5 g ODR Digital output data rate -P For both FIR and IIR filters Startup time For cold start condition ST Self-test positive difference(6) X, Y-axis Z-axis Top Operating temperature range ct( 45 g 0.4 mg/C 2 % FS 65 ug Hz 1.1 kHz 235 or 440 Hz 150 ms 75 75 650 1400 mg -40 +85 C ro 1. Typical specifications are not guaranteed. du StartT s) Bandwidth Bw -0.4 re NL re lea TCSo Pr o FS se Symbol du Table 3. Mechanical characteristics as eP 2. Sensor is designed with larger dynamic to avoid variation of FS limits in the operative bandwidth. Consequently to trim operations at factory final test. 3. Sensitivity range after MSL3 preconditioning. 4. Typical zero-g level offset value after MSL3 preconditioning. 5. Min/max at 3 sigma. Based on characterization data for a limited number of samples, not measured during final test for production. Pr er ele 6. Self-test positive difference is defined as: OUTPUT[mg](CTRL_REG4 (23h) ST2, ST1 bits = 01 ) - OUTPUT[mg](CTRL_REG4 (23h) ST2, ST1 bits = 00 ) in steady state. DocID030220 Rev 3 7/29 29 Mechanical and electrical specifications 2.2 LIS3DHH Electrical characteristics @ Vdd = 2.8 V, T = 25 C unless otherwise noted. 2.8 I/O pins supply voltage 1.71 Supply current VIH Digital high-level input voltage VIL Digital low-level input voltage High-level output voltage IOH = 4 mA Low-level output voltage Top Operating temperature range IOL = 4 SPI frequency Twait Time delay between Vdd_IO and Vdd(3) V Vdd+0.1 V 5 mA V 1. Typical specifications are not guaranteed. V V 0.2 V +85 C 10 MHz 0.01 100 ms 0 10 ms -40 4-wire interface Time for power supply rising 3.6 Vdd_IO - 0.2 mA(2) (3) Trise Unit 0.3*Vdd_IO (2) VOL SPI_Fr 0.7*Vdd_IO se VOH 2.5 Pr o Idd ct( 1.71 Max. du Supply voltage re lea Vdd_IO Typ.(1) Test condition re Vdd Min. Parameter -P Symbol s) Table 4. Electrical characteristics 5 s) 2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL. Pr er ele as eP ro du ct( 3. Please refer to Section 2.2.1: Recommended power-up sequence for more details. 8/29 DocID030220 Rev 3 LIS3DHH 2.2.1 Mechanical and electrical specifications Recommended power-up sequence ct( s) For the power-up sequence please refer to the following figure, where: Trise is the time for the power supply to rise from 10% to 90% of its final value Twait is the time delay between the end of the Vdd_IO ramp (90% of its final value) and the start of the Vdd ramp du In the power-down sequence Vdd and Vdd_IO can come down in any order. Figure 2. Recommended power-up sequence 9 9 7ULVH ct( Temperature sensor characteristics du @ Vdd = 2.8 V, T = 25 C unless otherwise noted. Table 5. Temperature sensor characteristics Parameter ro Symbol Temperature sensor output change vs. temperature Tn Temperature sensor noise (RMS) TODR Typ.(1) Max. 16 ele Ta Min. as eP TSDr Test condition Temperature accuracy -15 Temperature refresh rate equal to ODR/16 62.5 Pr er 2.3 s) -P re 9GG re lea 7ZDLW se 9GGB,2 Pr o 7ULVH TNL Temperature nonlinearity Best-fit straight line Top Operating temperature range digit/C 0.1 C +15 C Hz 5 -40 Unit % Top +85 C 1. Typical specifications are not guaranteed. DocID030220 Rev 3 9/29 29 Absolute maximum ratings 3 LIS3DHH Absolute maximum ratings Ratings Acceleration g for 0.2 ms ESD Vin Electrostatic discharge protection (HBM) Input voltage on any control pin (including CS, SPC, SDI, SDO) V -40 to +85 C 10,000 g 2 kV -0.3 to Vdd_IO +0.3 V re Supply voltage on any pin should never exceed 4.8 V. -P Note: Storage temperature range re lea Sg -0.3 to 4.8 se Vdd and Supply voltage Vdd_IO TSTG Unit Maximum value Pr o Symbol du Table 6. Absolute maximum ratings ct( s) Stresses above those listed as "Absolute maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. Pr er ele as eP ro du ct( s) This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. 10/29 DocID030220 Rev 3 LIS3DHH Communication interface characteristics Communication interface characteristics 4.1 SPI - serial peripheral interface s) 4 ct( Subject to general operating conditions for Vdd and Top. du Table 7. SPI slave timing values Value(1) Parameter Pr o Symbol Min tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time th(CS) CS hold time tsu(SI) SDI input setup time th(SI) SDI input hold time tv(SO) SDO valid output time th(SO) SDO output hold time tdis(SO) SDO output disable time 100 se Unit Max ns 10 MHz re lea 5 5 15 ns 50 5 50 s) -P re 20 ct( 1. Values are guaranteed at 10 MHz clock frequency for SPI 4 wires, based on characterization results, not tested in production Pr er ele as eP ro du Figure 3. SPI slave timing diagram Note: Measurement points are done at 0.2*Vdd_IO and 0.8*Vdd_IO, for both input and output ports. Note: The SPI state machine is reset each time the CS signal is de-asserted. DocID030220 Rev 3 11/29 29 Communication interface characteristics 4.2 LIS3DHH SPI bus interface The LIS3DHH SPI is a bus slave. The SPI allows writing and reading the registers of the device. ct( s) The serial interface interacts with the application using 4 wires: CS, SPC, SDI and SDO. du Figure 4. Read and write protocol Pr o &6 63& 6', se ', ', ', ', ', ', ', ', 5: $' $' $' $' $' $' $' re lea 6'2 '2 '2 '2 '2 '2 '2 '2 '2 -P re CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. du ct( s) Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. ro bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. as eP bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). ele In multiple read/write commands further blocks of 8 clock periods will be added. When the CTRL_REG1 (20h) (IF_ADD_INC) bit is `0' the address used to read/write data remains the same for every block. When CTRL_REG1 (20h)(IF_ADD_INC) bit is `1' the address used to read/write data is increased at every block. Pr er The function and the behavior of SDI and SDO remain unchanged. 12/29 DocID030220 Rev 3 LIS3DHH SPI read s) Figure 5. SPI read protocol ct( &6 du 63& 6', 5: Pr o $' $' $' $' $' $' $' 6'2 se '2 '2 '2 '2 '2 '2 '2 '2 re lea The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. re bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). -P bit 16-... : data DO(...-8). Further data in multiple byte reads. s) Figure 6. Multiple byte SPI read protocol (2-byte example) 6', 5: ro 63& du ct( &6 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 '2 ele 6'2 as eP $' $' $' $' $' $' $' Pr er 4.2.1 Communication interface characteristics DocID030220 Rev 3 13/29 29 Communication interface characteristics 4.2.2 LIS3DHH SPI write s) Figure 7. SPI write protocol ct( &6 du 63& 6', Pr o ', ', ', ', ', ', ', ', 5: se $' $' $' $' $' $' $' re lea The SPI write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. -P re bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writes. ct( s) Figure 8. Multiple byte SPI write protocol (2-byte example) du &6 ro 63& as eP 6', ', ', ', ', ', ', ', ', ',',',',',',', ', 5: Pr er ele $' $' $' $' $' $' $' 14/29 DocID030220 Rev 3 LIS3DHH 5 FIFO FIFO Pr o du ct( s) The LIS3DHH embeds 32 slots of 16-bit data FIFO for each of the accelerometer's three output channels, X, Y and Z. This allows consistent power saving for the system since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to five different modes: Bypass mode, FIFO mode, Continuous mode, Continuous-to-FIFO mode and Bypass-to-Continuous mode. Each mode is selected by the FMODE [2:0] bits in the FIFO_CTRL (2Eh) register. Programmable FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the FIFO_SRC (2Fh) register and can be set to generate dedicated interrupts on the INT1 and INT2 pins using the INT1_CTRL (21h) and INT2_CTRL (22h) registers. re lea se FIFO_SRC (2Fh)(FTH) goes to '1' when the number of unread samples (FIFO_SRC (2Fh) (FSS5:0)) is greater than or equal to FTH [4:0] in FIFO_CTRL (2Eh). If FIFO_CTRL (2Eh) (FTH[4:0]) is equal to 0, FIFO_SRC (2Fh)(FTH) goes to `0'. FIFO_SRC (2Fh)(OVRN) is equal to '1' if a FIFO slot is overwritten. re FIFO_SRC (2Fh)(FSS [5:0]) contains stored data levels of unread samples. When FSS [5:0] is equal to `000000', FIFO is empty. When FSS [5:0] is equal to `100000', FIFO is full and the unread samples are 32. -P The FIFO feature is enabled by writing '1' in CTRL_REG4 (23h) (FIFO_EN). ct( Bypass mode ro du In Bypass mode (FIFO_CTRL (2Eh)(FMODE [2:0]= 000), the FIFO is not operational, no data is collected in FIFO memory, and it remains empty with the only actual sample available in the output registers. as eP Bypass mode is also used to reset the FIFO when in FIFO mode. ele As described in Figure 9, for each channel only the first address is used. When new data is available the old data is overwritten. Pr er 5.1 s) To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded. empty xi,yi,zi Figure 9. Bypass mode x0 y0 z0 x1 y1 z1 x2 y2 z2 x31 y31 z31 DocID030220 Rev 3 15/29 29 FIFO 5.2 LIS3DHH FIFO mode s) In FIFO mode (FIFO_CTRL (2Eh) (FMODE [2:0] = 001) data from the output channels are stored in the FIFO memory until it is full, when 32 unread samples are stored in memory, data collecting is stopped. du ct( To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL (2Eh) (FMODE [2:0]) to '000'. After this reset command, it is possible to restart FIFO mode, writing FIFO_CTRL (2Eh) (FMODE [2:0]) to '001'. \ ] [ \ ] [ \ re ] \ ] -P [ s) [L\L]L re lea se Figure 10. FIFO mode Pr er ele as eP ro du ct( [ 16/29 Pr o A FIFO threshold interrupt can be enabled (INT1_OVR bit in INT1_CTRL (21h) or INT2_OVR bit in INT2_CTRL (22h)) in order to be raised when the FIFO is filled to the level specified by the FTH[4:0] bits of FIFO_CTRL (2Eh). DocID030220 Rev 3 LIS3DHH Continuous mode s) Continuous mode (FIFO_CTRL (2Eh) (FMODE[2:0] = 110) provides a continuous FIFO update: when 32 unread samples are stored in memory, as new data arrives the oldest data is discarded and overwritten by the newer. ct( A FIFO threshold flag FIFO_SRC (2Fh)(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to FIFO_CTRL (2Eh)(FTH4:0). Pr o du It is possible to route FIFO_SRC (2Fh)(FTH) to the INT1 pin by writing the INT1_FTH bit to `1' in register INT1_CTRL (21h) or to the INT2 pin by writing the INT2_FTH bit to `1' in register INT2_CTRL (22h). se A full-flag interrupt can be enabled (INT1_CTRL (21h) (INT_ FSS5)= '1' or INT2_CTRL (22h) (INT_ FSS5)= '1') when the FIFO becomes saturated and in order to read the contents all at once. If an overrun occurs, the oldest sample in FIFO is overwritten and the OVRN flag in FIFO_SRC (2Fh) is asserted. re lea In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_SRC (2Fh) (FSS[5:0]). x0 z0 y1 z1 y2 z2 x30 y30 z30 x31 y31 z31 x1 -P y0 s) xi,yi,zi re Figure 11. Continuous mode ele as eP ro du ct( x2 Pr er 5.3 FIFO DocID030220 Rev 3 17/29 29 FIFO 5.4 LIS3DHH Continuous-to-FIFO mode s) In Continuous-to-FIFO mode (FIFO_CTRL (2Eh)(FMODE [2:0] = 011), FIFO operates in Continuous mode and FIFO mode starts on the INT1 edge trigger event. When the FIFO is full, data collecting is stopped. z0 x1 y1 z1 x2 y2 z2 x30 y30 z30 x31 y31 z31 x0 y0 Pr o y0 du xi,yi,zi x0 z0 x1 y1 z1 x2 y2 z2 y31 z31 se -P Continuous Mode re re lea xi,yi,zi ct( Figure 12. Continuous-to-FIFO mode x31 FIFO Mode Trigger event Pr er ele as eP ro du ct( s) Figure 13. External asynchronous trigger to FIFO for Continuous-to-FIFO mode 18/29 DocID030220 Rev 3 LIS3DHH Bypass-to-Continuous mode s) In Bypass-to-Continuous mode (FIFO_CTRL (2Eh)(FMODE[2:0] = '100'), data measurement storage inside FIFO starts in Continuous mode on the INT1 edge trigger event, then the sample that follows the trigger is available in FIFO. z0 x1 y1 z1 x2 y2 z2 xi,yi,zi x0 y0 z0 y1 z1 x2 y2 z2 x30 y30 z30 y31 z31 x1 x31 y31 z31 re lea x31 du y0 Pr o empty x0 se xi,yi,zi ct( Figure 14. Bypass-to-Continuous mode Continuous Mode re Bypass Mode -P Trigger event ele as eP ro du ct( s) Figure 15. External asynchronous trigger to FIFO for Bypass-to-Continuous mode Pr er 5.5 FIFO DocID030220 Rev 3 19/29 29 Register mapping 6 LIS3DHH Register mapping ct( s) The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses. Table 8. Register mapping du Register address Default Reserved -- 00-0E -- WHO_AM_I r 0F 00001111 Reserved -- 10-1F -- CTRL_REG1 r/w 20 00100000 00000000 INT1_CTRL r/w 21 00100001 00000000 INT2_CTRL r/w 22 00100010 00000000 CTRL_REG4 r/w 23 00100011 00000000 CTRL_REG5 r/w 24 re lea Binary 00100100 00000000 OUT_TEMP_L r 25 00100101 output OUT_TEMP_H r 26 00100110 output STATUS r 27 00100111 output OUT_X_L_XL r s) Hex Pr o Type 28 00101000 output OUT_X_H_XL r 29 00101001 output OUT_Y_L_XL r ct( Name 2A 00101010 output r 2B 00101011 output r 2C 00101100 output r 2D 00101101 output FIFO_CTRL r/w 2E 00101110 00000000 FIFO_SRC r 2F 00101111 output -- 30-32 -- -- se re -P Reserved 00010001 -- ele Reserved as eP OUT_Z_H_XL du OUT_Z_L_XL ro OUT_Y_H_XL -- Note Reserved Reserved Pr er Registers marked as Reserved must not be changed. Writing to those registers may affect the correct behavior of the device. Their content is automatically restored when the device is powered up. 20/29 DocID030220 Rev 3 LIS3DHH 7 Register description Register description WHO_AM_I (0Fh) du 7.1 ct( s) The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration and temperature data. The register addresses, consisting of 7 bits, are used to identify them and to write the data through the serial interface. Pr o Device identification register. Table 9. WHO_AM_I register 1 0 0 se 0 CTRL_REG1 (20h) Control register 1. 0 1 NORM_ IF_ADD_ MOD_EN INC 0(1) BOOT -P 0(1) re Table 10. CTRL_REG1 register SW_RESET DRDY_ PULSE BDU s) 1. These bits must be set to `0' for the correct operation of the device. ct( Table 11. CTRL_REG1 register description Normal mode enable. Default value: 0 (0: power down; 1: enabled) IF_ADD_INC Register address automatically incremented during a multiple byte access with SPI serial interface. Default value: 1 (0: disabled; 1: enabled) BOOT Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content(1)) ro as eP ele SW_RESET DRDY_PULSE BDU du NORM_MOD_EN Pr er 7.2 0 re lea 0 Software reset. Default value: 0 With SW_RESET the values in the writable CTRL registers are changed to the default values. (0: normal mode; 1: reset device) This bit is cleared by hardware at the end of the operation. Data ready on INT1 pin. Default value: 0 (0: DRDY latched; 1: DRDY pulsed, pulse duration is 1/4 ODR) Block Data Update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB read) 1. Boot request is executed as soon as the internal oscillator is turned on. It is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode. DocID030220 Rev 3 21/29 29 Register description 7.3 LIS3DHH INT1_CTRL (21h) Table 12. INT1_CTRL register INT1_ BOOT INT1_ OVR INT1_ FSS5 0(1) INT1_FTH INT1_ EXT ct( INT1_ DRDY s) INT1 pin control register. du 1. These bits must be set to `0' for the correct operation of the device. 0(1) Table 13. INT1_CTRL register description Pr o Accelerometer data ready on INT1 pin. Default value: 0 INT1_DRDY (0: disabled; 1: enabled) (0: disabled; 1: enabled) re lea Overrun flag on INT1 pin. Default value: 0 (0: disabled; 1: enabled) INT1_OVR se Boot status available on INT1 pin. Default value: 0 INT1_ BOOT FSS5 full FIFO flag on INT1 pin. Default value: 0 INT1_ FSS5 (0: disabled; 1: enabled) re FIFO threshold flag on INT1 pin. Default value: 0 INT1_FTH (0: disabled; 1: enabled) -P INT1 pin configuration. Default value: 0 It configures the INT1 pad as output for FIFO flags or as external asynchronous INT1_ EXT s) input trigger to FIFO. INT2 pad is always available as output for FIFO flags. INT2_CTRL (22h) ro 7.4 du ct( (0: INT1 as output interrupt; 1: INT1 as input channel) as eP INT2 pin control register. INT2_DRDY INT2_BOOT Table 14. INT2_CTRL register INT2_OVR INT2_ FSS5 INT2_FTH 0(1) ele 1. These bits must be set to `0' for the correct operation of the device. Pr er INT2_DRDY INT2_ BOOT INT2_OVR INT2_ FSS5 INT2_FTH 22/29 Table 15. INT2_CTRL register description Accelerometer data ready on INT2 pin. Default value: 0 (0: disabled; 1: enabled) Boot status available on INT2 pin. Default value: 0 (0: disabled; 1: enabled) Overrun flag on INT2 pin. Default value: 0 (0: disabled; 1: enabled) FSS5 full FIFO flag on INT2 pin. Default value: 0 (0: disabled; 1: enabled) FIFO threshold flag on INT2 pin. Default value: 0 (0: disabled; 1: enabled) DocID030220 Rev 3 0(1) 0(1) LIS3DHH 7.5 Register description CTRL_REG4 (23h) Control register 4. DSP_BW_ SEL ST2 PP_OD_ INT2 ST1 PP_OD_ INT1 FIFO_EN 1(1) du 1. This bit must be set to `1' for correct operation of the device. ct( DSP_LP_ TYPE s) Table 16. CTRL_REG4 register Table 17. CTRL_REG4 register description Digital filtering selection. Default value: 0 (0: FIR Linear Phase; 1: IIR Nonlinear Phase) DSP_BW_SEL User-selectable bandwidth. Default value: 0 (0: 440 Hz typ.; 1: 235 Hz typ.) ST [2:1] Self-test enable. Default value: 00 (00: Self-test disabled; Other: See Table 18) PP_OD_INT2 Push-pull/open drain selection on INT2 pin. Default value: 0 (0: push-pull mode; 1: open drain mode) PP_OD_INT1 Push-pull/open drain selection on INT1 pin. Default value: 0 (0: push-pull mode; 1: open drain mode) FIFO_EN FIFO memory enable. Default value: 0 (0: disabled; 1: enabled) -P re re lea se Pr o DSP_LP_TYPE ST1 0 0 0 1 1 0 Normal mode du Positive sign self-test ro Negative sign self-test 1 Not allowed as eP 1 CTRL_REG5 (24h) ele Control register 5. 0(1) Pr er 7.6 Self-test mode ct( ST2 s) Table 18. Self-test mode selection 0(1) Table 19. CTRL_REG5 register 0(1) 0(1) 0(1) 0(1) 0(1) FIFO_SPI_HS_ON 1. These bits must be set to `0' for correct operation of the device. Table 20. CTRL_REG5 register description Enables the SPI high speed configuration for the FIFO block that is used to guarantee a minimum duration of the window in which writing operation of FIFO_SPI_HS_ON RAM output is blocked. This bit is recommended for SPI clock frequencies higher than 6 MHz. Default value: 0. (0: not enabled; 1: enabled) DocID030220 Rev 3 23/29 29 Register description 7.7 LIS3DHH OUT_TEMP_L (25h), OUT_TEMP_H (26h) s) Temperature data output register. L and H registers together express a 16-bit word in two's complement left-justified. Temp2 Temp1 Temp11 Temp10 Temp9 Temp0 0 0 0 Table 22. OUT_TEMP_H register Temp7 Temp6 Temp5 0 Temp4 Pr o Temp8 du Temp3 ct( Table 21. OUT_TEMP_L register Table 23. OUT_TEMP register description Temperature sensor output data. The value is expressed as two's complement sign. 0 LSB represents T=25 C ambient. STATUS (27h) Status register (r) re 7.8 re lea se Temp [11:0] Table 24. Status register ZOR YOR XOR -P ZYXOR ZYXDA ZDA YDA XDA s) Table 25. Status register description ct( ZYXOR Logic OR of the single X-, Y- and Z-axis data overrun. Default value: 0 (0: no overrun has occurred; 1: a new set of data has overwritten the previous set) Z-axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data) YOR Y-axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the Y-axis has overwritten the previous data) XOR X-axis data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for the X-axis has overwritten the previous data) as eP ro du ZOR ZYXDA Logic AND of the single X-, Y- and Z-axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Y-axis new data available. Default value: 0 (0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available) Pr er YDA Z-axis new data available. Default value: 0 (0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available) ele ZDA XDA 24/29 X-axis new data available. Default value: 0 (0: new data for the X-axis is not yet available; 1: new data for the X-axis is available) DocID030220 Rev 3 LIS3DHH 7.9 Register description OUT_X (28h - 29h) OUT_Y (2Ah - 2Bh) ct( 7.10 s) Linear acceleration sensor X-axis output register. The value is expressed as a 16-bit word in two's complement. 7.11 Pr o du Linear acceleration sensor Y-axis output register. The value is expressed as a 16-bit word in two's complement. OUT_Z (2Ch - 2Dh) FIFO_CTRL (2Eh) re FIFO control register. Table 26. FIFO_CTRL register FMODE0 FTH4 -P FMODE1 FTH3 FTH2 FTH1 FTH0 s) FMODE2 Table 27. FIFO_CTRL register description FIFO mode selection bits. Default value: 000 For further details refer to Table 28. FTH [4:0] FIFO threshold level setting. Default value: 0 0000 FMODE2 0 as eP ro du ct( FMODE [2:0] FMODE1 Table 28. FIFO mode selection FMODE0 Mode 0 0 Bypass mode. FIFO turned off 0 1 FIFO mode. Stops collecting data when FIFO is full. 1 0 Reserved 1 1 Continuous mode until trigger is asserted, then FIFO mode. 1 0 0 Bypass mode until trigger is asserted, then Continuous mode. 1 0 1 Reserved 1 1 0 Continuous mode. If the FIFO is full, the new sample overwrites the older sample. 1 1 1 Reserved 0 0 ele 0 Pr er 7.12 re lea se Linear acceleration sensor Z-axis output register. The value is expressed as a 16-bit word in two's complement. DocID030220 Rev 3 25/29 29 Register description 7.13 LIS3DHH FIFO_SRC (2Fh) FIFO status register. OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 ct( FTH s) Table 29. FIFO_SRC register du Table 30. FIFO_SRC register description FIFO threshold status. (0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level OVRN FIFO overrun status. (0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten) For further details refer to Table 31. FSS [5:0] Number of unread samples stored in FIFO. (000000: FIFO empty; 100000: FIFO full, 32 unread samples) For further details refer to Table 31. re lea se Pr o FTH Table 31. FIFO_SRC example: OVR/FSS details FSS5 FSS4 FSS3 Description FIFO empty 0 0 1 1 unread sample 0 0 0 0 32 unread samples 0 0 0 0 At least one sample has been overwritten 0 0 0 0 0 0 --(1) 0 1 0 (1) 1 1 0 0 ct( s) ... 0 FSS0 0 0 -- FSS1 0 0 (1) FSS2 re 0 OVRN -P FTH ro du 1. When the number of unread samples in FIFO is equal to or greater than the threshold level set in register FIFO_CTRL (2Eh), the FTH value is `1'. as eP The FSS is the FIFO stored data level of the unread samples. When it is equal to FTH, all data available in FIFO are read without additional read operations. The INT output is high when the number of samples to read is equal to or greater than FTH. Pr er ele Figure 16. Continuous mode: FTH/FSS details 26/29 DocID030220 Rev 3 LIS3DHH Package information 8 Package information LGA-16 package information Pr o 8.1 du ct( s) In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 17. Ceramic cavity LGA-16: package outline and mechanical data re lea se ) du ct( 8 s) -P re - B$ as eP Note: ro 3LQ LQGLFDWRU Top and bottom view: dimensions are expressed in mm ele Table 32. Outer dimensions Dimension [mm] Tolerance [mm] Length [L] 5 0.15 Width [W] 5 0.15 Height [H] 1.7 typ 0.15 Pad size 0.7 x 0.5 0.15 Pr er ITEM Note: General tolerance is 0.1 mm unless otherwise specified DocID030220 Rev 3 27/29 29 Revision history 9 LIS3DHH Revision history s) Table 33. Document revision history Revision Changes 23-Mar-2017 1 Initial release 09-May-2017 2 Updated VIH, VIL and added VOH, VOL to Table 4: Electrical characteristics 3 Updated Table 3: Mechanical characteristics Updated Table 4: Electrical characteristics Updated Figure 2: Recommended power-up sequence Updated Table 7: SPI slave timing values Updated Figure 6: Multiple byte SPI read protocol (2-byte example) and Figure 8: Multiple byte SPI write protocol (2-byte example) Added WHO_AM_I (0Fh) Updated bit 0 in CTRL_REG4 (23h) Pr er ele as eP ro du ct( s) -P re re lea 11-Oct-2017 se Pr o du ct( Date 28/29 DocID030220 Rev 3 ct( s) -P re re lea se Pr o du ct( s) LIS3DHH du IMPORTANT NOTICE - PLEASE READ CAREFULLY as eP ro STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. ele Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Pr er Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID030220 Rev 3 29/29 29