W25N01GVxxIG/IT
Publication Release Date: May 09, 2018
Revision L
3V 1G-BIT
SERIAL SLC NAND FLASH MEMORY WITH
DUAL/QUAD SPI
BUFFER READ & CONTINUOUS READ
W25N01GVxxIG/IT
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Table of Contents
1.GENERAL DESCRIPTIONS ............................................................................................................. 6
2.FEATURES ....................................................................................................................................... 6
3.PACKAGE TYPES AND PIN CONFIGURATIONS .......................................................................... 7
3.1Pad Configuration WSON 8x6-mm ...................................................................................... 7
3.2Pad Description WSON 8x6-mm .......................................................................................... 7
3.3Pin Configuration SOIC 300-mil ........................................................................................... 8
3.4Pin Description SOIC 300-mil ............................................................................................... 8
3.5Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 9
3.6Ball Description TFBGA 8x6-mm ......................................................................................... 9
4.PIN DESCRIPTIONS ...................................................................................................................... 10
4.1Chip Select (/CS) ................................................................................................................ 10
4.2Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) .................................. 10
4.3Write Protect (/WP) ............................................................................................................. 10
4.4HOLD (/HOLD) ................................................................................................................... 10
4.5Serial Clock (CLK) .............................................................................................................. 10
5.BLOCK DIAGRAM .......................................................................................................................... 11
6.FUNCTIONAL DESCRIPTIONS ..................................................................................................... 12
6.1Device Operation Flow ....................................................................................................... 12
6.1.1Standard SPI Instructions ..................................................................................................... 12
6.1.2Dual SPI Instructions ............................................................................................................ 12
6.1.3Quad SPI Instructions ........................................................................................................... 13
6.1.4Hold Function ........................................................................................................................ 13
6.2Write Protection .................................................................................................................. 14
7.PROTECTION, CONFIGURATION AND STATUS REGISTERS .................................................. 15
7.1Protection Register / Status Register-1 (Volatile Writable, OTP lockable) ......................... 15
7.1.1Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable .................. 15
7.1.2Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable ................................. 16
7.1.3Status Register Protect Bits (SRP1, SRP0) – Volatile Writa ble, O T P lockable ..................... 16
7.2Configuration Register / Status Register-2 (Volatile Writable) ........................................... 17
7.2.1One Time Program Lock Bit (OTP-L) – OTP lockable .......................................................... 17
7.2.2Enter OTP Access Mode Bit (OTP-E) – Volatile Writable ..................................................... 17
7.2.3Status Register-1 Lock Bit (SR1-L) – OTP lockable ............................................................. 17
7.2.4ECC Enable Bit (ECC-E) – Volatile Writable ......................................................................... 18
7.2.5Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable ..................................... 18
7.3Status Register-3 (Status Only) .......................................................................................... 19
7.3.1Look-Up Table Full (LUT-F) – Status Only ............................................................................ 19
7.3.2Cumulative ECC Status (ECC-1, ECC-0) – Status Only ....................................................... 19
7.3.3Program/Erase Failure (P-FAIL, E-FAIL) – Status Only ........................................................ 20
7.3.4Write Enable Latch (WEL) – Status Only .............................................................................. 20
7.3.5Erase/Program In Progress (BUSY) – Status Only ............................................................... 20
7.3.6Reserved Bits – Non Functional ........................................................................................... 20
7.4W25N01GV Status Register Memory Protection ............................................................... 21
W25N01GVxxIG/IT
Publication Release Date: May 09, 2018
- 2 - Revision L
8.INSTRUCTIONS ............................................................................................................................. 22
8.1Device ID and Instruction Set Tables ................................................................................. 22
8.1.1Manufacturer and Device Identification ................................................................................. 22
8.1.2Instruction Set Table 1 (Continuous Read, BUF = 0, xxIT Default Power Up Mode)(11) ........ 23
8.1.3Instruction Set Table 2 (Buffer Read, BUF = 1, xxIG Default Power Up Mode)(12) ................ 24
8.2Instruction Descriptions ...................................................................................................... 26
8.2.1Device Reset (FFh) ............................................................................................................... 26
8.2.2Read JEDEC ID (9Fh) .......................................................................................................... 27
8.2.3Read Status Register (0Fh / 05h) ......................................................................................... 28
8.2.4Write Status Register (1Fh / 01h) ......................................................................................... 29
8.2.5Write Enable (06h) ................................................................................................................ 30
8.2.6Write Disable (04h) ............................................................................................................... 30
8.2.7Bad Block Management (A1h) .............................................................................................. 31
8.2.8Read BBM Look Up Table (A5h) .......................................................................................... 32
8.2.9Last ECC Failure Page Address (A9h) ................................................................................. 33
8.2.10128KB Block Erase (D8h) ................................................................................................... 34
8.2.11Load Program Data (02h) / Random Load Program Data (84h) ......................................... 35
8.2.12Quad Load Program Data (32h) / Quad Random Load Program Data (34h) ...................... 36
8.2.13Program Execute (10h) ....................................................................................................... 37
8.2.14Page Data Read (13h) ........................................................................................................ 38
8.2.15Read Data (03h) ................................................................................................................. 39
8.2.16Fast Read (0Bh) ................................................................................................................. 40
8.2.17Fast Read with 4-Byte Address (0Ch)................................................................................. 41
8.2.18Fast Read Dual Output (3Bh) ............................................................................................. 42
8.2.19Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................ 43
8.2.20Fast Read Quad Output (6Bh) ............................................................................................ 44
8.2.21Fast Read Quad Output with 4-Byte Address (6Ch) ........................................................... 45
8.2.22Fast Read Dual I/O (BBh) ................................................................................................... 46
8.2.23Fast Read Dual I/O with 4-Byte Address (BCh) .................................................................. 47
8.2.24Fast Read Quad I/O (EBh) .................................................................................................. 48
8.2.25Fast Read Quad I/O with 4-Byte Address (ECh) ................................................................. 50
8.2.26Accessing Unique ID / Parameter / OTP Pages (OTP-E=1) ............................................... 52
8.2.27Parameter Page Data Definitions ....................................................................................... 53
9.ELECTRICAL CHARACTERISTICS............................................................................................... 54
9.1Absolute Maximum Ratings (1) .......................................................................................... 54
9.2Operating Ranges .............................................................................................................. 54
9.3Power-up Power-down Timing Requirements .................................................................... 55
9.3.1Power-up Timing and Voltage Levels ................................................................................... 55
9.3.2Power-up, Power-Down Requirement .................................................................................. 55
9.4DC Electrical Characteristics .............................................................................................. 56
9.5AC Measurement Conditions ............................................................................................. 57
9.6AC Electrical Characteristics(3) ........................................................................................... 58
9.7Serial Output Timing ........................................................................................................... 60
9.8Serial Input Timing .............................................................................................................. 60
9.9/HOLD Timing ..................................................................................................................... 60
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9.10/WP Timing ......................................................................................................................... 60
10.INVALID BLOCK MANAGEMENT .................................................................................................. 61
10.1Invalid blocks ...................................................................................................................... 61
10.2Initial invalid blocks ............................................................................................................. 61
11.PACKAGE SPECIFICATIONS ....................................................................................................... 62
11.18-Pad WSON 8x6-mm (Package Code ZE) ....................................................................... 62
11.216-Pin SOIC 300-mil (Package Code SF) .......................................................................... 63
11.324-Ball TFBGA 8x6-mm (Package Code TB, 5x5-1 Ball Array) ......................................... 64
11.424-Ball TFBGA 8x6-mm (Package Code TC, 6x4 Ball Array) ............................................ 65
12.ORDERING INFORMATION .......................................................................................................... 66
12.1Valid Part Numbers and Top Side Marking ........................................................................ 67
13.REVISION HISTORY ...................................................................................................................... 68
W25N01GVxxIG/IT
Publication Release Date: May 09, 2018
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Table of Figures
Figure 1a. W25N01GV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE) .............................. 7
Figure 1b. W25N01GV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF) .................................. 8
Figure 1c. W25N01GV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC) ................... 9
Figure 2. W25N01GV Flash Memory Architecture and Addressing ........................................................... 11
Figure 3. W25N01GV Flash Memory Operation Diagram .......................................................................... 12
Figure 4a. Protection Register / Status Register-1 (Address Axh) ............................................................. 15
Figure 4b. Configuration Register / Status Register-2 (Address Bxh) ........................................................ 17
Figure 4c. Status Register-3 (Address Cxh) ............................................................................................... 19
Figure 5. Device Reset Instruction .............................................................................................................. 26
Figure 6. Read JEDEC ID Instruction ......................................................................................................... 27
Figure 7. Read Status Register Instruction ................................................................................................. 28
Figure 8. Write Status Register-1/2/3 Instruction ........................................................................................ 29
Figure 9. Write Enable Instruction ............................................................................................................... 30
Figure 10. Write Disable Instruction ............................................................................................................ 30
Figure 11. Bad Block Management Instruction ........................................................................................... 31
Figure 12. Read BBM Look Up Table Instruction ....................................................................................... 32
Figure 13. Last ECC Failure Page Address Instruction .............................................................................. 33
Figure 14. 128KB Block Erase Instruction .................................................................................................. 34
Figure 15. Load / Random Load Program Data Instruction ........................................................................ 35
Figure 16. Quad Load / Quad Random Load Program Data Instruction .................................................... 36
Figure 17. Program Execute Instruction ..................................................................................................... 37
Figure 18. Page Data Read Instruction ....................................................................................................... 38
Figure 19a. Read Data Instruction (Buffer Read Mode, BUF=1) ................................................................ 39
Figure 19b. Read Data Instruction (Continuous Read Mode, BUF=0) ....................................................... 39
Figure 20a. Fast Read Instruction (Buffer Read Mode, BUF=1) ................................................................ 40
Figure 20b. Fast Read Instruction (Continuous Read Mode, BUF=0) ........................................................ 40
Figure 21a. Fast Read with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ............................... 41
Figure 21b. Fast Read with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ....................... 41
Figure 22a. Fast Read Dual Output Instruction (Buffer Read Mode, BUF=1) ............................................ 42
Figure 22b. Fast Read Dual Output Instruction (Continuous Read Mode, BUF=0) ................................... 42
Figure 23a. Fast Read Dual Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ........... 43
Figure 23b. Fast Read Dual Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) .. 43
Figure 24a. Fast Read Quad Output Instruction (Buffer Read Mode, BUF=1) ........................................... 44
Figure 24b. Fast Read Quad Output Instruction (Continuous Read Mode, BUF=0) .................................. 44
Figure 25a. Fast Read Quad Output with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ......... 45
Figure 25b. Fast Read Quad Output with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) . 45
Figure 26a. Fast Read Dual I/O Instruction (Buffer Read Mode, BUF=1) .................................................. 46
Figure 26b. Fast Read Dual I/O Instruction (Continuous Read Mode, BUF=0).......................................... 46
Figure 27a. Fast Read Dual I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1) ................. 47
Figure 27b. Fast Read Dual I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ........ 47
Figure 28a. Fast Read Quad I/O Instruction (Buffer Read Mode, BUF=1) ................................................. 48
Figure 28b. Fast Read Quad I/O Instruction (Continuous Read Mode, BUF=0) ........................................ 49
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Figure 29a. Fast Read Quad I/O with 4-Byte Address Instruction (Buffer Read Mode, BUF=1)................ 50
Figure 29b. Fast Read Quad I/O with 4-Byte Address Instruction (Continuous Read Mode, BUF=0) ....... 51
Figure 30a. Power-up Timing and Voltage Levels ...................................................................................... 55
Figure 30b. Power-up, Power-Down Requirement ..................................................................................... 55
Figure 31. AC Measurement I/O Waveform ................................................................................................ 57
Figure 32. Flow chart of create initial invalid block table ............................................................................ 61
W25N01GVxxIG/IT
Publication Release Date: May 09, 2018
- 6 - Revision L
1. GENERAL DESCRIPTIONS
The W25N01GV (1G-bit) Serial SLC NAND Flash Memory provides a storage solution for systems with
limited space, pins and power. The W25N SpiFlash family incorporates the popular SPI interface and the
traditional large NAND non-volatile memory space. They are ideal for code shadowing to RAM, executing
code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The device operates on a single
2.7V to 3.6V power supply with current consumption as low as 25mA active and 10µA for standby. All W25N
SpiFlash family devices are offered in space-saving packages which were impossible to use in the past for
the typical NAND flash memory.
The W25N01GV 1G-bit memory array is organized into 65,536 programmable pages of 2,048-bytes each.
The entire page can be programmed at one time using the data from the 2,048-Byte internal buffer. Pages
can be erased in groups of 64 (128KB block erase). The W25N01GV has 1,024 erasable blocks.
The W25N01GV supports the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI: Serial Clock,
Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to
104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz
(104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions.
The W25N01GV provides a new Continuous Read Mode that allows for efficient access to the entire
memory array with a single Read command. This feature is ideal for code shadowing applications.
A Hold pin, Write Protect pin and programmable write protection, provide further control flexibility.
Additionally, the device supports JEDEC standard manufacturer and device ID, one 2,048-Byte Unique ID
page, one 2,048-Byte parameter page and ten 2,048-Byte OTP pages. To provide better NAND flash
memory manageability, user configurable internal ECC, bad block management are also available in
W25N01GV.
2. FEATURES
New W25N Family of SpiFlash Memories
– W25N01GV: 1G-bit / 128M-byte
– Standard SPI: CLK, /CS, DI, DO, /WP,
/Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– Compatible SPI serial flash commands
Highest Performance Serial NAND Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/S continuous data transfer rate
– Fast Program/Erase performance
– More than 100,000 erase/program cycles(4)
– More than 10-year data retention
Efficient “Continuous Read Mode”(1)
– Alternative method to the Buffer Read
Mode
– No need to issue “Page Data Read”
between Read commands
– Allows direct read access to the entire
array
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 25mA active, 10µA standby current
– -40°C to +85°C operating range
Flexible Architecture with 128KB blocks
– Uniform 128K-Byte Block Erase
– Flexible page data load methods
Adv anced Features
– On chip 1-Bit ECC for memory array
– ECC status bits indicate ECC results
– bad block management and LUT(2) access
– Software and Hardware Write-Protect
– Power Supply Lock-Down and OTP protection
– 2KB Unique ID and 2KB parameter pages
– Ten 2KB OTP pages(3)
Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 16-pin SOIC 300-mil
– 24-ball TFBGA 8x6-mm
– Contact Winbond for other package options
Notes:
1. Only the Read command structures are different between
the “Continuous Read Mode (BUF=0)” and the “Buffer
Read Mode (BUF=1)”, all other commands are identical.
W25N01GVxxIG: Default BUF=1 after power up
W25N01GVxxIT: Default BUF=0 after power up
2. LUT stands for Look-Up Table.
3. OTP pages can only be programmed.
4. Endurance specification is based on the on-chip ECC or
1bit/528 byte ECC(Error Correcting Code)
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3. PACKA GE TYPES AND PIN CON FIG URATIONS
W25N01GV is offered in an 8-pad WSON 8x6-mm (package code ZE), a 16-pin SOIC 300-mil (package
code SF), and two 24-ball 8x6-mm TFBGA (package code TB & TC) packages as shown in Figure 1a-c
respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
Figure 1a. W25N01GV Pad Assignments, 8-pad WSON 8x6-mm (Package Code ZE)
3.2 Pad Description WSON 8x6-mm
PAD NO. PAD NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)(1)
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)(2)
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)(1)
6 CLK I Serial Clock Input
7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)(2)
8 VCC Power Supply
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
1
2
3
4
/CS
DO (IO1)
/WP (IO2)
GND
VCC
/HOLD (IO3)
DI (IO0)
CLK
Top View
8
7
6
5
W25N01GVxxIG/IT
Publication Release Date: May 09, 2018
- 8 - Revision L
3.3 Pin Configuration SOIC 300-mil
Figure 1b. W25N01GV Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
3.4 Pin Description SOIC 300-mil
PIN NO. PIN NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)(2)
2 VCC Power Supply
3 N/C No Connect
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1)(1)
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2)
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0)(1)
16 CLK I Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
1
2
3
4
/CS
DO (IO
1
)/WP (IO
2
)
GND
VCC
/HOLD (IO
3
)
DI (IO
0
)
CLK
Top View
NC
NC
NC
NC
NC
NC
NC
NC5
6
7
8
10
9
11
12
13
14
15
16
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3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Figure 1c. W25N01GV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code TB & TC)
3.6 Ball Description TFBGA 8x6-mm
BALL NO. PIN NAME I/O FUNCTION
B2 CLK I Serial Clock Input
B3 GND Ground
B4 VCC Power Supply
C2 /CS I Chip Select Input
C4 /WP (IO2) I/O Write Protect Input (Data Input Output 2)(2)
D2 DO (IO1) I/O Data Output (Data Input Output 1)(1)
D3 DI (IO0) I/O Data Input (Data Input Output 0)(1)
D4 /HOLD (IO3) I/O Hold Input (Data Input Output 3)(2)
Multiple NC No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions
2. IO0 – IO3 are used for Quad SPI instructions, /WP & /HOLD functions are only available for Standard/Dual SPI.
W25N01GVxxIG/IT
Publication Release Date: May 09, 2018
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4. PIN DESCRIPTIONS
4.1 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
30b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.
4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25N01GV supports standard SPI, Dual SPI and Quad SPI operation. Standard SPI instructions use
the unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising
edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read data
or status from the device on the falling edge of CLK.
Dual and Quad SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data
to the device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.
4.3 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect bits BP[3:0] and Status Register Protect SRP bits
SRP[1:0], a portion as small as 256K-Byte (2x128KB blocks) or up to the entire memory array can be
hardware protected. The WP-E bit in the Protection Register (SR-1) controls the functions of the /WP pin.
When WP-E=0, the device is in the Software Protection mode that only SR-1 can be protected. The /WP
pin functions as a data I/O pin for the Quad SPI operations, as well as an active low input pin for the Write
Protection function for SR-1. Refer to section 7.1.3 for detail information.
When WP-E=1, the device is in the Hardware Protection mode that /WP becomes a dedicated active low
input pin for the Write Protection of the entire device. If /WP is tied to GND, all “Write/Program/Erase”
functions are disabled. The entire device (including all registers, memory array, OTP pages) will become
read-only. Quad SPI read operations are also disabled when WP-E is set to 1.
4.4 HOLD (/HOLD)
During Standard and Dual SPI operations, the /HOLD pin allows the device to be paused while it is actively
selected. When /HOLD is brought low, while /CS is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When /HOLD is brought high, device operation can
resume. The /HOLD function can be useful when multiple devices are sharing the same SPI signals. The
/HOLD pin is active low.
When a Quad SPI Read/Buffer Load command is issued, /HOLD pin will become a data I/O pin for the
Quad operations and no HOLD function is available until the current Quad operation finishes. /HOLD (IO3)
must be driven high by the host, or an external pull-up resistor must be placed on the PCB, in order to avoid
allowing the /HOLD input to float.
4.5 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
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5. BLOCK DIAGRAM
Figure 2. W25N01GV Flash Memory Architecture and Addressing
Page
Structure
(2,112-Byte)
Sect or 0
512-Byte Sect o r 1
512-Byte Secto r 2
512-Byte Sect o r 3
512-Byte Spare 0
16-Byte Spare 1
16-Byte Spare 2
16-Byte S p are 3
16-Byte
Column
Address
000h -- 1FFh 200h -- 3FFh 400h -- 5FFh 600h -- 7FFh 800h -- 80Fh 810h -- 81Fh 820h -- 82Fh 830h -- 83Fh
Byte
Definition Bad Block
Marker Use r Data
II User Data
IECC for
Sect or 0 ECC f or
Spare
Byte
Address
0123456789ABCDEF
Main M emor y A r r ay (2, 048- Byte)
ECC Protected Spare Area (64-Byte)
No E CC
Protection ECC
Protected ECC for
Byte 4 to Byte D
1,024 Blocks X 64 Pages
(65,536 Pages)
Page Address PA[15:0]
AddressBits 313029282726252423222120191817161514131211109876543210
SpiFlash(upto128M‐Bit) XXXXXXXX
SpiFlash(upto32G‐Bit)
XXXX
XXXX Ext
SerialNAND(1G‐Bit) PageAddress(PA)[15:0] ColumnAddress(CA)[11:0]
128KBBlockAddr(1024Blocks) PageAddr(64Pages) ByteAddress(0‐2047Byte)
64KBBlockAddr(256Blocks) PageAddress(256Pages) ByteAddress(0‐255Byte)
64KBBlockAddress PageAddress(256Pages) ByteAddress(0‐255Byte)
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6. FUNCTIONAL DESCRIPTIONS
6.1 Device Operation Flow
Figure 3. W25N01GV Flash Memory Operation Diagram
6.1.1 Standard SPI Instructions
The W25N01GV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
6.1.2 Dual SPI Instructions
The W25N01GV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are ideal for
quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-critical
Power Up
(default BUF=1, ECC-E=1)
Initialization &
Default Page Load (00) ~500us
Load Page xx
tRD ~50us
Y
N
Start “Buffer Read” with column address
(Page 00 or Page xx)
Read
page 00?
Set BUF=0
Load Page yy
tRD ~50us
Start “Continuous Read” from column 0
(Page yy)
Power Up
(default BUF=0, ECC-E=1)
Initialization &
Default Page Load (00) ~500us
Load Page xx
tRD ~50us
Y
N
Start “Continuous Read” from column 0
(Page 00 or Page xx)
Read
page 00?
Set BUF=1
Load Page yy
tRD ~50us
Start “Buffer Read” with column address
(Page yy)
W25N01GVxxIG W25N01GVxxIT
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code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: IO0 and IO1.
6.1.3 Quad SPI Instructions
The W25N01GV supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)” and “Quad Program Data Load (32h/34h)”. These instructions allow
data to be transferred to or from the device four to six times the rate of ordinary Serial Flash. The Quad
Read instructions offer a significant improvement in continuous and random access transfer rates allowing
fast code-shadowing to RAM or execution directly from the SPI bus (XIP). When using Quad SPI
instructions the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become
IO2 and IO3 respectively.
6.1.4 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25N01GV operation to be paused
while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where the SPI
data and clock signals are shared with other devices. For example, consider if the page buffer was only
partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD function can
save the state of the instruction and the data in the buffer so programming can resume where it left off once
the bus is available again. The /HOLD function is only available for standard SPI and Dual SPI operation,
not during Quad SPI. When a Quad SPI command is issued, /HOLD pin will act as a dedicated IO pin (IO3).
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the rising
edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD condition
will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data Output (DO) is
high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (/CS)
signal should be kept active (low) for the full duration of the /HOLD operation to avoid resetting the internal
logic state of the device.
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6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25N01GV
provides several means to protect the data from inadvertent writes.
Device resets when VCC is below threshold
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (/WP pin) write protection using Protection Register (SR-1)
Lock Down write protection for Protection Register (SR-1) until the next power-up
One Time Program (OTP) write protection for memory array using Protection Register (SR-1)
Hardware write protection using /WP pin when WP-E is set to 1
Upon power-up or at power-down, the W25N01GV will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 30a). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Program Execute, Block Erase and the Write Status Register instructions. Note
that the chip select pin (/CS) must track the VCC supply level at power-up until the VCC-min level and tVSL
time delay is reached, and it must also track the VCC supply level at power-down to prevent adverse
command sequence. If needed a pull-up resister on /CS can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Program Execute, Block
Erase or Bad Block Management instruction will be accepted. After completing a program or erase
instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (TB, BP[3:0]) bits. These settings allow a portion
or the entire memory array to be configured as read only. Used in conjunction with the Write Protect (/WP)
pin, changes to the Status Register can be enabled or disabled under hardware control. See Protection
Register section for further information.
The WP-E bit in Protection Register (SR-1) is used to enable the hardware protection. When WP-E is set
to 1, bringing /WP low in the system will block any Write/Program/Erase command to the W25N01GV, the
device will become read-only. The Quad SPI operations are also disabled when WP-E is set to 1.
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7. PROTECTION, CONFIGURATION AND STATUS REGISTERS
Three Status Registers are provided for W25N01GV: Protection Register (SR-1), Configuration Register
(SR-2) & Status Register (SR-3). Each register is accessed by Read Status Register and Write Status
Register commands combined with 1-Byte Register Address respectively.
The Read Status Register instruction (05h / 0Fh) can be used to provide status on the availability of the
flash memory array, whether the device is write enabled or disabled, the state of write protection, Read
modes, Protection Register/OTP area lock status, Erase/Program results, ECC usage/status. The Write
Status Register instruction can be used to configure the device write protection features, Software/Hardware
write protection, Read modes, enable/disable ECC, Protection Register/OTP area lock. Write access to the
Status Register is controlled by the state of the non-volatile Status Register Protect bits (SRP0, SRP1), the
Write Enable instruction, and when WP-E is set to 1, the /WP pin.
7.1 Protection Register / Status Register-1 (Volatile Writable, OTP lockable)
Figure 4a. Protection Register / Status Register-1 (Address Axh)
7.1.1 Block Protect Bits (BP3, BP2, BP1, BP0, TB) – Volatile Writable, OTP lockable
The Block Protect bits (BP3, BP2, BP1, BP0 & TB) are volatile read/write bits in the status register-1 (S6,
S5, S4, S3 & S2) that provide Write Protection control and status. Block Protect bits can be set using the
Write Status Register Instruction. All, none or a portion of the memory array can be protected from Program
and Erase instructions (see Status Register Memory Protection table). The default values for the Block
Protection bits are 1 after power up to protect the entire array. If the SR1-L bit in the Configuration Register
(SR-2) is set to 1, the default values will the values that are OTP locked.
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7.1.2 Write Protection Enable Bit (WP-E) – Volatile Writable, OTP lockable
The Write Protection Enable bit (WP-E) is a volatile read/write bits in the status register-1 (S1). The WP-E
bit, in conjunction with SRP1 & SRP0, controls the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection, /WP pin functionality, and
Quad SPI operation enable/disable. When WP-E = 0 (default value), the device is in Software Protection
mode, /WP & /HOLD pins are multiplexed as IO pins, and Quad program/read functions are enabled all the
time. When WP-E is set to 1, the device is in Hardware Protection mode, all Quad functions are disabled
and /WP & /HOLD pins become dedicated control input pins.
7.1.3 Status Register Protect Bits (SRP1, SRP0) – Volatile Writable, OTP lockable
The Status Register Protect bits (SRP1 and SRP0) are volatile read/write bits in the status register (S0 and
S7). The SRP bits control the method of write protection: software protection, hardware protection, power
supply lock-down or one time programmable (OTP) protection.
Software Protection (Driven by Controller, Quad Program/Read is enabled)
SRP1 SRP0 WP-E /WP / IO2 Descriptions
0 0 0 X No /WP functionality
/WP pin will alw ays function as IO2
0 1 0 0 SR-1 cannot be changed (/WP = 0 during Write Status)
/WP pin will function as IO2 for Quad operations
0 1 0 1 SR-1 can be changed (/WP = 1 during Write Status)
/WP pin will function as IO2 for Quad operations
1 0 0 X Power Lock Down(1) SR-1
/WP pin will alw ays function as IO2
1 1 0 X Enter OTP mode to protect SR-1 (allow SR1-L=1)
/WP pin will alw ays function as IO2
Hardware Protection (System Circuit / PCB layout, Quad Program/Read is disabled)
SRP1 SRP0 WP-E /WP only Descriptions
0 X 1 VCC SR-1 can be changed
1 0 1 VCC Power Lock-Down(1) SR-1
1 1 1 VCC Enter OTP mode to protect SR-1 (allow SR1-L=1)
X X 1 GND All "Write/Program/Erase" commands are blocked
Entire device (SRs, Array, OTP area) is read-only
Notes:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state.
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7.2 Configuration Register / Status Register-2 (Volatile Writable)
Figure 4b. Configuration Register / Status Register-2 (Address Bxh)
7.2.1 One Time Program Lock Bit (OTP-L) – OTP lockable
In addition to the main memory array, W25N01GV also provides an OTP area for the system to store critical
data that cannot be changed once it’s locked. The OTP area consists of 10 pages of 2,112-Byte each. The
default data in the OTP area are FFh. Only Program command can be issued to the OTP area to change
the data from “1” to “0”, and data is not reversible (“0” to “1”) by the Erase command. Once the correct data
is programmed in and verified, the system developer can set OTP-L bit to 1, so that the entire OTP area
will be locked to prevent further alteration to the data.
7.2.2 Enter OTP Access Mode Bit (OTP-E) – Volatile Writable
The OTP-E bit must be set to 1 in order to use the standard Program/Read commands to access the OTP
area as well as to read the Unique ID / Parameter Page information. The default value after power up or a
RESET command is 0.
7.2.3 Status Register-1 Lock Bit (SR1-L) – OTP loc k able
The SR1-L lock bit is used to OTP lock the values in the Protection Register (SR-1). Depending on the
settings in the SR-1, the device can be configured to have a portion of or up to the entire array to be write-
protected, and the setting can be OTP locked by setting SR1-L bit to 1. SR1-L bit can only be set to 1
permanently when SRP1 & SRP0 are set to (1,1), and OTP Access Mode must be entered (OTP-E=1) to
execute the programming. Please refer to 8.2.26 for detailed information.
S7 S6 S5 S4 S3 S2 S1 S0
BUF
Reserved
Enter OTP Mode
(Volatile Writable)
Buffer Mode
(Volatile Writable)
OTP Data Pages Lock
(OTP Lock)
OTP-L OTP-E ECC-E
Enable ECC
(Volatile Writable)
(R) (R)SR1-L
Status Register-1 Lock
(OTP Lock)
(R)
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7.2.4 ECC Enable Bit (ECC-E) – Volatile Writable
W25N01GV has a built-in ECC algorithm that can be used to preserve the data integrity. Internal ECC
calculation is done during page programming, and the result is stored in the extra 64-Byte area for each
page. During the data read operation, ECC engine will verify the data values according to the previously
stored ECC information and to make necessary corrections if needed. The verification and correction status
is indicated by the ECC Status Bits. ECC function is enabled by default when power on (ECC-E=1), and it
will not be reset to 0 by the Device Reset command.
7.2.5 Buffer Read / Continuous Read Mode Bit (BUF) – Volatile Writable
W25N01GV provides two different modes for read operations, Buffer Read Mode (BUF=1) and Continuous
Read Mode (BUF=0). Prior to any Read operation, a Page Data Read command is needed to initiate the
data transfer from a specified page in the memory array to the Data Buffer. By default, after power up, the
data in page 0 will be automatically loaded into the Data Buffer and the device is ready to accept any read
commands.
The Buffer Read Mode (BUF=1) requires a Column Address to start outputting the existing data inside the
Data Buffer, and once it reaches the end of the data buffer (Byte 2,111), DO (IO1) pin will become high-Z
state.
The Continuous Read Mode (BUF=0) doesn’t require the starting Column Address. The device will always
start output the data from the first column (Byte 0) of the Data buffer, and once the end of the data buffer
(Byte 2,048) is reached, the data output will continue through the next memory page. With Continuous
Read Mode, it is possible to read out the entire memory array using a single read command. Please refer
to respective command descriptions for the dummy cycle requirements for each read commands under
different read modes.
For W25N01GVxxIG part number, the default value of BUF bit after power up is 1. BUF bit can be written
to 0 in the Status Register-2 to perform the Continuous Read operation.
For W25N01GVxxIT part number, the default value of BUF bit after power up is 0. BUF bit can be written
to 1 in the Status Register-2 to perform the Buffer Read operation.
BUF ECC-E Read Mode
(Starting from Buffer) ECC Status Data Output Structure
1 0 Buffer Read N/A 2,048 + 64
1 1 Buffer Read Page based 2,048 + 64
0 0 Continuous Read N/A 2,048
0 1 Continuous Read Operation based 2,048
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7.3 Status Register-3 (Status Only)
Figure 4c. Status Register-3 (Address Cxh)
7.3.1 Look-Up Table Full (LUT-F) – Status Only
To facilitate the NAND flash memory bad block management, the W25N01GV is equipped with an internal
Bad Block Management Look-Up-Table (BBM LUT). Up to 20 bad memory blocks may be replaced by a
good memory block respectively. The addresses of the blocks are stored in the internal Look-Up Table as
Logical Block Address (LBA, the bad block) & Physical Block Address (PBA, the good block). The LUT-F
bit indicates whether the 20 memory block links have been fully utilized or not. The default value of LUT-F
is 0, once all 20 links are used, LUT-F will become 1, and no more memory block links may be established.
7.3.2 Cumulative ECC Status (ECC-1, ECC-0) – Status Only
ECC function is used in NAND flash memory to correct limited memory errors during read operations. The
ECC Status Bits (ECC-1, ECC-0) should be checked after the completion of a Read operation to verify the
data integrity. The ECC Status bits values are don’t care if ECC-E=0. These bits will be cleared to 0 after a
power cycle or a RESET command.
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ECC Status Descriptions
ECC-1 ECC-0
0 0 Entire data output is successful, without any ECC correction.
0 1
Entire data output is successful, with 1~4 bit/page ECC corrections in either a
single page or multiple pages.
1 0
Entire data output contains more than 4 bits errors only in a single page
which cannot be repaired by ECC.
In the Continuous Read Mode, an additional command can be used to read out
the Page Address (PA) which had the errors.
1 1
Entire data output contains mor e than 4 bits errors/page in multiple pages.
In the Continuous Read Mode, the additional command can only provide the
last Page Address (PA) that had failures, the user cannot obtain the PAs for
other failure pages. Data is not suitable to use.
Notes:
1. ECC-1,ECC-0 = (1,1) is only applicable during Continuous Read operation (BUF=0).
7.3.3 Program/Erase Failure (P-FAIL, E-FAIL) – Status Only
The Program/Erase Failure Bits are used to indicate whether the internally-controlled Program/Erase
operation was executed successfully or not. These bits will also be set respectively when the Program or
Erase command is issued to a locked or protected memory array or OTP area. Both bits will be cleared at
the beginning of the Program Execute or Block Erase instructions as well as the device RESET instruction.
7.3.4 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following instructions: Write Disable, Program Execute, Block
Erase, Page Data Read, Program Execute and Bad Block Management for OTP pages.
7.3.5 Erase/Program In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is powering up or
executing a Page Data Read, Bad Block Management, Program Execute, Block Erase, Program Execute
for OTP area, OTP Locking or after a Continuous Read instruction. During this time the device will ignore
further instructions except for the Read Status Register and Read JEDEC ID instructions. When the
program, erase or write status register instruction has completed, the BUSY bit will be cleared to a 0 state
indicating the device is ready for further instructions.
7.3.6 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written
as “0”, but there will not be any effects.
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7.4 W25N01GV Status Register Memory Protection
STATUS REGISTER(1) W25N01GV (1G-BIT / 128M-BYTE) MEMORY PROTECTION(2)
TB BP3 BP2 BP1 BP0 PROTECTED
BLOCK(S)
PROTECTED
PAGE ADDRESS
PA[15:0]
PROTECTED
DENSITY PROTECTED
PORTION
X 0 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 1022 & 1023 FF80h - FFFFh 256KB Upper 1/512
0 0 0 1 0 1020 thru 1023 FF00h - FFFFh 512KB Upper 1/256
0 0 0 1 1 1016 thru 1023 FE00h - FFFFh 1MB Upper 1/128
0 0 1 0 0 1008 thru 1023 FC00h - FFFFh 2MB Upper 1/64
0 0 1 0 1 992 thru 1023 F800h - FFFFh 4MB Upper 1/32
0 0 1 1 0 960 thru 1023 F000h - FFFFh 8MB Upper 1/16
0 0 1 1 1 896 thru 1023 E000h - FFFFh 16MB Upper 1/8
0 1 0 0 0 768 thru 1023 C000h - FFFFh 32MB Upper 1/4
0 1 0 0 1 512 thru 1023 8000h - FFFFh 64MB Upper 1/2
1 0 0 0 1 0 & 1 0000h – 007Fh 256KB Lower 1/512
1 0 0 1 0 0 thru 3 0000h - 00FFh 512KB Lower 1/256
1 0 0 1 1 0 thru 7 0000h - 01FFh 1MB Lower 1/128
1 0 1 0 0 0 thru 15 0000h - 03FFh 2MB Lower 1/64
1 0 1 0 1 0 thru 31 0000h - 07FFh 4MB Lower 1/32
1 0 1 1 0 0 thru 63 0000h - 0FFFh 8MB Lower 1/16
1 0 1 1 1 0 thru 127 0000h - 1FFFh 16MB Lower 1/8
1 1 0 0 0 0 thru 255 0000h - 3FFFh 32MB Lower 1/4
1 1 0 0 1 0 thru 511 0000h - 7FFFh 64MB Lower 1/2
X 1 0 1 X 0 thru 1023 0000h - FFFFh 128MB ALL
X 1 1 X X 0 thru 1023 0000h - FFFFh 128MB ALL
Notes:
1. X = don’t care
2. If any Erase or Program command specifies a memory region that contains protected data portion, this command will be ignored.
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8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25N01GV consists of 27 basic instructions that are
fully controlled through the SPI bus (see Instruction Set Table1, 2). Instructions are initiated with the falling
edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code.
Data on the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in Figures 5 through
29. All read instructions can be completed after any clocked bit. However, all instructions that Write,
Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been clocked)
otherwise the instruction will be ignored. This feature further protects the device from inadvertent writes.
Additionally, while the device is performing Program or Erase operation, BBM management, Page Data
Read or OTP locking operations, BUSY bit will be high, and all instructions except for Read Status Register
or Read JEDEC ID will be ignored until the current operation cycle has completed.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID (MF7 - MF0)
Winbond Serial Flash EFh
Device ID (ID15 - ID0)
W25N01GV AA21h
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8.1.2 Instruction Set Table 1 (Continuous Read, BUF = 0, xxIT Default Power Up Mode)(11)
Commands OpCode Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Byte9
Device RESET FFh
JEDEC ID 9Fh Dummy EFh AAh 21h
Read Status Register 0Fh / 05h SR Addr S7-0 S7-0 S7-0 S7-0 S7-0 S7-0 S7-0
Write Status Register 1Fh / 01h SR Addr S7-0
Write Enable 06h
Write Disable 04h
BB Management
(Swap Blocks) A1h LBA LBA PBA PBA
Read BBM LUT A5h Dummy LBA0 LBA0 PBA0 PBA0 LBA1 LBA1 PBA1
Last ECC failure
Page Address A9h Dummy PA15-8 PA7-0
Block Erase D8h Dummy PA15-8 PA7-0
Program Data Load
(Reset Buffer) 02h CA15-8 CA7-0
Data-0 Data-1 Data-2 Data-3 Data-4 Data-5
Random Program
Data Load 84h CA15-8 CA7-0
Data-0 Data-1 Data-2 Data-3 Data-4 Data-5
Quad Program
Data Load (Reset Buffer) 32h CA15-8 CA7-0
Data-0 / 4 Data-1 / 4 Data-2 / 4 Data-3 / 4 Data-4 / 4 Data-5 / 4
Random Quad Program
Data Load 34h CA15-8 CA7-0
Data-0 / 4 Data-1 / 4 Data-2 / 4 Data-3 / 4 Data-4 / 4 Data-5 / 4
Program Execute 10h Dummy PA15-8 PA7-0
Page Data Read 13h Dummy PA15-8 PA7-0
Read 03h Dummy Dummy Dummy D7-0 D7-0 D7-0 D7-0 D7-0
Fast Read 0Bh Dummy Dummy Dummy Dummy D7-0 D7-0 D7-0 D7-0
Fast Read
with 4-Byte Address 0Ch Dummy Dummy Dummy Dummy Dummy D7-0 D7-0 D7-0
Fast Read Dual Output 3Bh Dummy Dummy Dummy Dummy D7-0 / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Dual Output
with 4-Byte Address 3Ch Dummy Dummy Dummy Dummy Dummy D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Quad Output 6Bh Dummy Dummy Dummy Dummy D7-0 / 4 D7-0 / 4 D7-0 / 4 D7-0 / 4
Fast Read Quad Output
with 4-Byte Address 6Ch Dummy Dummy Dummy Dummy Dummy D7-0 / 4 D7-0 / 4 D7-0 / 4
Fast Read Dual I/O BBh Dummy / 2 Dummy / 2 Dummy / 2 Dummy / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Dual I/O
with 4-Byte Address BCh Dummy / 2 Dummy / 2 Dummy / 2 Dummy / 2 Dummy / 2 D7-0 / 2 D7-0 / 2 D7-0 / 2
Fast Read Quad I/O EBh Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 D7-0 / 4 D7-0 / 4
Fast Read Quad I/O
with 4-Byte Address ECh Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 Dummy / 4 D7-0 / 4