To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-30333-3E MEMORY 5V-ONLY FLASH MEMORY CARD MB98A81063-15/MB98A81183-15/MB98A81273-15/ MB98A81373-15/MB98A81473-15/MB98A81573-15 1M/2M/4M/8M/16M/32M-BYTE 5V-ONLY FLASH ERASABLE AND PROGRAMMABLE MEMORY CARD DESCRIPTION The Fujitsu 5V-Only Flash memory cards are electrically erasable and programmable memory cards capable of storing and retrieving large amounts of data. The memory circuits are housed in a credit-card sized 68-pin package. Internal circuit is protected by two metal panels, one at the top and the other at the bottom of the card, that help to reduce chip damage from electrostatic discharge. A unique feature of the Fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus configuration. All cards are portable and operate on low power at high speed. In accordance with the Personal Computer Memory Card Internal Association (PCMCIA) and Japan Electrical Industry Development Association (JEIDA) industry standard specifications, Flash memory cards offer additional EEPROM memory that is used to store attribute data. The attribute memory is a Flash memory card option. (See page 3 for description of the three available options.) PRODUCT LINE & FEATURES * Meet PCMCIA and JEIDA industry standards for 68-pin memory card Type I : 85.6 mm x 54.0 mm x 3.3 mm * +5 V5% power supply program and erase * Command control for Automated Program / Automated Erase operation * Erase Suspend Read / Program Capability (Only Erase Suspend Read is possible for MB98A81063) * 128 KB Sector Erase (at x16 mode) * Any Combination of Sectors Erase and Full Chip Erase * Detection of completion of program/erase operation with Data Polling or Toggle bit. * Ready/Busy Output with R/B (Except for MB98A81063) * Reset Function with RESET pin (Except for MB98A81063) * Write protect function with WP switch * Low VCC Write Inhibit To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PACKAGE CRD-68P-M17 2 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 DESCRIPTIONS DESCRIPTION TABLE Common Memory Part Number Attribute Memory Organization (W x bit) Memory Device MB98A81063 4M bit Flash Memory x 2 1M x 8/512K x 16 MB98A81183 8M bit Flash Memory x 2 2M x 8/1M x 16 Access Time Memory Device 150 ns max. 16K bit EEPROM x 1 MB98A81273 16M bit Flash Memory x 2 4M x 8/2M x 16 MB98A81373 16M bit Flash Memory x 4 8M x 8/4M x 16 Organization Access (W x bit) Time 2K x 8 250 ns max. MB98A81473 16M bit Flash Memory x 8 16M x 8/8M x 16 MB98A81573 16M bit Flash Memory x 16 32M x 8/16M x 16 DIFFERENCES MB98A81063 MB98A81183 MB98A81273 MB98A81373 MB98A81473 MB98A81573 1MB 2MB 4MB 8MB 16MB 32MB 4M bit 8M bit 16M bit 2 2 2 4 8 16 Read 1 B unit Program 1 B unit Chip Erase 512 KB unit 1 MB unit 2 MB unit Sector Erase 64 KB unit 16 32 64 128 256 512 Erase Suspend Read Yes Yes Yes Yes Yes Yes Erase Suspend Program No Yes Yes Yes Yes Yes Address A0 to A19 A0 to A20 A0 to A21 A0 to A22 A0 to A23 A0 to A24 RESET No Yes Yes Yes Yes Yes R/B No Yes Yes Yes Yes Yes Density Memory Device Quantity Number of Sectors 3 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 DESCRIPTIONS (Continued) ADDRESS MAP (for x 16 mode, not contained A0) FFFFFFh chip15, 14 DFFFFFh chip13, 12 BFFFFFh chip11,10 9FFFFFh chip9, 8 7FFFFFh chip7, 6 chip7, 6 chip5, 4 chip5, 4 chip3, 2 chip3, 2 chip3, 2 chip1, 0 chip1, 0 chip1, 0 5FFFFFh 3FFFFFh 1FFFFFh 0FFFFFh 07FFFFh 000000h chip1, 0 chip1, 0 chip1, 0 MB98A81063 MB98A81183 MB98A81273 MB98A81373 MB98A81473 MB98A81573 4 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PIN ASSIGNMENTS Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol 1 GND 18 N.C. 35 GND 52 N.C. 2 D3 19 A16 36 CD1 53 A22/N.C.* 3 D4 20 A15 37 D11 54 A23/N.C.* 4 D5 21 A12 38 D12 55 A24/N.C.* 5 D6 22 A7 39 D13 56 N.C. 6 D7 23 A6 40 D14 57 N.C. 7 CE1 24 A5 41 D15 58 RESET/N.C. 8 A10 25 A4 42 CE2 59 N.C. 9 OE 26 A3 43 N.C. 60 N.C. 10 A11 27 A2 44 N.C. 61 REG 11 A9 28 A1 45 N.C. 62 BVD2 12 A8 29 A0 46 A17 63 BVD1 13 A13 30 D0 47 A18 64 D8 14 A14 31 D1 48 A19 65 D9 15 WE 32 D2 49 A20/N.C.* 66 D10 16 R/B/N.C.* 33 WP 50 A21/N.C.* 67 CD2 17 VCC 34 GND 51 VCC 68 GND * : See "DESCRIPTIONS". 5 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PIN DESCRIPTIONS Symbol Pin Name A0 to A24 Address Input D0 to D15 Data Input/Output CE1 CE2 Input/Output Input Function Address Inputs, A0 to A24. Input/Output Data Inputs/Outputs. This data bus size (8-bit or 16-bit) is selected with CE1 and CE2. Card Enable for Lower Byte Input Active Low. -Lower byte (D0 to D7) is selected for read/write/ erase function of flash memory cards. Card Enable for Upper Byte Input Active Low. -Upper byte (D8 to D15) is selected for read/write / erase function of flash memory cards. REG Attribute Memory Select Input Active Low. -Attribute memory is selected for read/write function of identification data of flash memory cards. (N.C. or "FF" data or attribute data.) OE Output Enable Input Active Low. -Output enable for flash memory cards. WE Write Enable Input Active Low. -Write enable for flash memory cards. CD1, CD2 Card Detect Output These pins detect if the card has been correctly inserted. Both pins are tied to GND internally. WP Write Protect Output Write controller for flash memory cards. This pin outputs the Protect/Non Protect status of "WP Switch". BVD1, BVD2 Battery Voltage Detect Output Both pins are tied to VCC internally. RESET Hardware Reset R/B Ready/Busy VCC Power Supply -- Power Supply Voltage. (+5.0 V 5%) GND Ground -- System Ground. N.C. Non Connection -- Input The card may be reset by driving the RESET pin to VIH. Output System can be detect the completion of program or erase operation. PIN LOCATIONS Fig. 1 - BOTTOM VIEW (CONNECTOR SIDE) Front Side 1 34 68 35 Back Side 6 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 BLOCK DIAGRAM MB98A81063, MB98A81183, MB98A81273 and MB98A81373 VCC Internal circuit GND Internal circuit Address Buffer I/O Buffer R/B*1 Decoder D0 to D15 WP Control VCC 100 K RESET CE1 WE CE2 OE REG CE WE Address I/O (EVEN BYTE) 4M Flash chip x 1 (81063) 8M Flash chip x 1 (81183) 16M Flash chip x 1 (81273) 16M Flash chip x 2 (81273 R/B WP OE RESET*1 Address RESET I/O WE 510 K OE CE (ODD BYTE) 4M Flash chip x 1 (81063) 8M Flash chip x 1 (81183) 16M Flash chip x 1 (81273) 16M Flash chip x 2 (81373) R/B VCC Address VCC WP Switch 10 K BVD1 WE Attribute memory I/O OE CE 16K EEPROM BVD2 CD1 CD2 *1: Not available for MB98A81063. Fig. 2.1 - Block Diagram 7 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 BLOCK DIAGRAM (Continued) MB98A81473 and MB98A81573 VCC Internal circuit GND Internal circuit R/B Control Buffer circuit I/O Buffer Address Decoder WP Control D0 to D15 VCC 100 K RESET CE1 WE CE2 OE CE REG WE Address I/O R/B (EVEN BYTE) 16M Flash chip x 4 (81473) 16M Flash chip x 8 (81573) WP OE RESET RESET Address I/O WE 510 K R/B OE CE (ODD BYTE) 16M Flash chip x 4 (81473) 16M Flash chip x 8 (81573) VCC Address VCC Attribute memory WP Switch 10 K WE OE 16K EEPROM BVD1 CE BVD2 CD1 CD2 Fig. 2.2 - Block Diagram 8 I/O To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 CHIP AND SECTOR DECODING * Chip can be selected with; - A0, A22, A23 and A24 for x 8-bit mode No.1. - A22, A23 and A24 for x 8-bit mode No.2 and x 16-bit mode. * Sector per each chip can be selected with A17, A18, A19, A20 and A21. ERASE SECTOR DECODING TABLE Sector 31 Sector 30 Sector 29 * * * Total 32 sectors*1*2 per 1 chip * * * Sector 2 Sector 1 Sector 0 A21*2 1 1 1 A20*1 1 1 1 Sector Address (SA) A19 1 1 1 A18 1 1 0 A17 1 0 1 * * * * * * * * * * * * * * * * * * * * * * * * * 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 *1: A20 is not available for MB98A81063. MB98A81063 has 8 sectors. *2: A21 is not available for MB98A81063 and MB98A81183. MB98A81063 has 8 sectors and MB98A81183 has 16 sectors. CARD CHIP / SECTOR CONFIGURATION D8 D15 UPPER BYTE D7 D0 LOWER BYTE EVEN ADDRESS BYTE ODD ADDRESS BYTE x 16 bit mode x 8 bit mode No. 1 Chip 1 (16M Flash Chip*1) Chip 15 Chip 14 Chip 13 Chip 12 Chip 11 Chip 10 * * * * * * Chip 5 Chip 0 (16M Flash Chip*1) Sector 31*2(64K x 8 bits) Sector 31*2(64K x 8 bits) * * * * * * * * * * * * Chip 4 Sector 2 (64K x 8 bits) Sector 2 (64K x 8 bits) Chip 3 Chip 2 Sector 1 (64K x 8 bits) Sector 1 (64K x 8 bits) Chip1 Chip 0 Sector 0 (64K x 8 bits) Sector 0 (64K x 8 bits) Card Chip Configuration for 32MB Card Sector Configuration for 2 Chips *1: 4M Flash Chip for MB98A81063. 8M Flash chip for MB98A81183. *2: Sector 7 for MB98A81063. Sector 15 for MB98A81183. 9 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 FUNCTION DESCRIPTIONS 1. Read Mode The data in the common and attribute memory can be read with "OE=VIL" and "WE=VIH". The address is selected with A0 to A24. And CE1 and CE2 select output mode (x 8/x 16 output mode, See "FUNCTION TRUTH TABLES".). The following 1) and 2) are the descriptions for Common Memory Read and Attribute Memory Read mode. (1) Common Memory Read - Two modes of Common Memory Read, reading the data in memory array and Intelligent ID are available. The card enter each Read mode by writing "Read Memory/Reset Command" or "Intelligent ID Read Command". The card automatically resets to the condition of Common Memory Read mode upon initial power-up. (2) Attribute Memory Read - The data on the attribute memory can be read with "REG=VIL", "OE=VIL" and "WE=VIH". - An address on attribute memory can be selected with A0 to A11 pin. And CE1 and CE2 select output mode. 2. Standby Mode - CE1 and CE2 at "VIH" place the card in Standby mode. D0 to D15 are placed in a high-Z state independent of the status "OE", "WE" and "REG". 3. Output Disable Mode - The outputs are disabled with OE and WE at "VIH". D0 to D15 are placed in high-Z state. 4. Write Mode (1) - Common Memory Write The card is in Write mode with "OE=VIH" and "WE and CE=VIL". Commands can be written at the Write mode. See "5.Command Definitions". Two types of the Write mode, "WE control" and "CE control" are available. (2) Attribute Memory Write - REG at L-level selects Attribute memory and "OE=VIH", "WE and CE=VIL" place it in write mode. Two types of the write mode, "WE control" and "CE control" are available. - Attribute memory is not controlled by writing Commands. And attribute memory has the Data polling function, which can detect whether the attribute memory status is in programming operation. When the read operation is executed at programming cycle, the opposite data is output from D7 (I7), and the same data (O7) as the written data is output from D7 pin at the completion of programming operation. 5. Command Definitions - User can select the card operation by writing the specific address and data sequences into the command register. If incollect address and data are written or improper sequence is done, the card is reseted to read mode. See "COMMAND DEFINISION TABLE". 6. Automated Program Capability - Programming operation can swich the data from "1" to "0". - The data is programmed on a byte-by-byte or word-by-word basis. - The card will automatically provide adequate internally generated programming pulses and verify the programmed cell margine by writing four bus cycle operation. The card returns to Common Memory Read mode automatically after the programming is completed. - Addresses are latched at falling edge of WE or CE and data is latched at rising edge of WE or CE. The fourth rising edge of WE or CE on the command write cycle begins programming operation. - We can check whether a byte (word) programming operation is completed successfully by sequence flug with R/B (Except for MB98A81063), Data Polling or Toggle Bit function. See "WRITE OPERATION STATUS". - Any commands written to the chip during programming operation will be ignored. 7. Automated Chip Erase Capability - We can execute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to preprogram prior to erase. Upon executing the Erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timing during these operations. - The card returns to Common Memory Read mode automatically after the chip erasing is completed. 10 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 FUNCTION DESCRIPTIONS (Continued) - Whether or not chip erase operation is completed successfully can be checked by sequence flug with R/B (Except for MB98A81063), Data Polling or Toggle Bit function. See "WRITE OPERATION STATUS". - Any commands written to the chip during programming operation will be ignored. 8. Automated Sector Erase Capability - We can execute the erase operation on any sectors by 6 bus cycle operation. - A time-out of 50 s (typ.) from the rising edge of the last Sector Erase command will initiate the Sector Erase command(s) for other sector than the sector that sector erase command have been valid. - Multiple sectors in a chip can be erased concurrently. This sequence is followed with writes of 30H to addresses in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 s, otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50 s (typ.) time out from the rising edge of WE pulse for the last Sector Erase command pulse. Whether the sector erase window is still open can be monitored with D3 and D11. - Sector Erase does not require the user to pre-program prior to erase. The chip automatically programs "0" to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any controls or timing during these operations. - The card returns to Common Memory Read mode automatically after the sector erasing is completed. - Whether or not sector erase operation is completed successfully can be checked by sequence flug with R/B, Data Polling or Toggle Bit function. The sequence flug must be read from the address of the sector involved in erase operation. See "WRITE OPERATION STATUS". 9. Erase Suspend - Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is possible for MB98A81063). This command is applicable only during the sector erase operation (including the sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the chip erase or programming operation. Writing this command during the time-out will result in immediate termination of the time-out period. The addresses are "don't cares" in wrinting the Erase Suspend or Resume commands in the chip. - When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase Suspend Read mode. User can read the data from other sectors than those in suspention. The read operation from sectors in suspention results D2/D10 toggling for MB98A81183 and MB98A8xx7x. User can program to non-busy sectors by writing program commands for MB98A81183 and MB98A8xx7x. - A read from a sector being erase suspended may result in invalid data. 10. Intelligent Identifier (ID) Read Mode - Each common memory can execute an Intelligent Identifier operation, initiated by writing Intelligent ID command (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code, and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is necessary to write Read/Reset command. Maker Code Device Code MB98A81063 Part Number 04 h / 0404 h A4 h / A4A4 h MB98A81183 04 h / 0404 h D5 h / D5D5 h MB98A81273/81373/1473/81573 04 h / 0404 h 3D h / 3D3D h 11. Hardware Reset (not applied for MB98A81063) - The Card may be reset by driving the RESET pin to VIH. The RESET pin must be kept High (VIH) for at least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 s after the RESET pin is driven High. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate. - When the RESET pin is high and the internal reset is complete, the Card goes to standby mode and cannot be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET pulse. Once the RESET pin is taken low, the Card requires 500 ns of wake up time until outputs are valid for read access. - If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be used after this. 11 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 FUNCTION DESCRIPTIONS (Continued) 12. Data Protection - The card has WP (Write Protect) switch for write lockout. - To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less than 3.2 V (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when VCC is above 3.2 V. - If VCC would be less than VLKO during program/erase operation, the operation will stop. And after that, the operation will not resume even if VCC returns recommended voltage level. Therefore, program command must be written again because the data on the address interrupted program operation is invalid. And regarding interrupting erase operation, there is possibility that the erasing sector(s) cannot be used. - Noise pulses of less than 5 ns (typical) on OE, CE or WE will not initiate a write cycle. FUNCTION TRUTH TABLE MAIN MEMORY FUNCTION*1 Mode Hardware Reset RESET*3 REG CE2 CE1 H Standby OE WE WP *2 D8 to D15 D0 to D7 X X X X X X High-Z X H H X X X X High-Z L Read (x8 No.1) High-Z H Read (x8 No.2) L Read (x16) H L H DOUT (Odd Byte) L Write (x8 No.1) L H H H L Write (x8 No.1) Output Disable H L H Output Disable L Write (x16) X L Output Disable X X X X High-Z L H Write (x8 No.2) High-Z H H DIN (Even Byte) NP High-Z P DIN (Odd Byte) NP H P L DIN (Odd Byte) H High-Z High-Z NP P L DIN NP H High-Z P X High-Z P or NP Notes: *1: H =VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect *2: L-level is output when WPSW = NP. H-level is output when WPSW = P. *3: Not available for MB98A81063. 12 P or NP DOUT L L DOUT (Odd Byte) X X WP SW DOUT (Even Byte) L H Output Disable Data Input/Output X Read (x8 No.1) Output Disable A0 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 FUNCTION TRUTH TABLE (Continued) ATTRIBUTE MEMORY FUNCTION*1 Mode RESET*3 REG CE2 CE1 Standby X Read (x8 No.1) Read (x8 No.1) Read (x8 No.2) H H H L L Read (x16) H L Write (x8 No.1) OE WE WP *2 X X X X L H H L L H D0 to D7 DOUT H P or NP High-Z DOUT L DIN NP H High-Z P INVALID DIN NP L H WP SW High-Z H Output Disable High-Z H H Write (x8 No.2) L H Output Disable L Write (x16) L X X X X H H P L INVALID DIN H High-Z L INVALID DIN X Output Disable Output Disable D8 to D15 X X L L Data Input/Output High-Z L Output Disable Write (x8 No.1) A0 NP High-Z P DIN NP H High-Z P X High-Z P or NP Notes: *1: H = VIH, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect *2: L-level is output when WPSW = NP. H-level is output when WPSW = P. *3: Not available for MB98A81063. 13 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 COMMAND DEFINITION TABLE Command table for 8-bit Mode Command Bus 1st Bus Cycle Write Cycle Read/Reset 1 2 Read/Reset 2 4 Read Intelligent ID Codes 4 Byte Program 4 Sector Erase 6 Chip Erase 6 Sector Erase Suspend 1 Sector Erase Resume 1 Write CA F0H Write 2nd Bus 4th Bus Write Write/Read 5th Bus Write 6th Bus Write Write/Read 3rd Bus Cycle Cycle Cycle Cycle Cycle Read RA Write RD Write RCMA1 AAH RCMA2 55H RCMA1 F0H Write Write Write ICMA1 AAH ICMA2 55H ICMA1 90H Write Write Write PCMA1 AAH PCMA2 55H PCMA1 A0H Write Write Write Read RA RD Read IA ID Write PA PD Write Write SCMA1 AAH SCMA2 55H SCMA1 80H SCMA1 AAH SCMA2 55H Write Write Write Write Write Write SA 30H Write CCMA1 AAH CCMA2 55H CCMA1 80H CCMA1 AAH CCMA2 55H CCMA1 10H Write CA B0H Write CA 30H Notes: CA: SA: PA: RA: IA: Chip Address. (address in chip selected by A0, A22, A23 and A24) Sector Address (address in 64 KB selected by A0, A17, A18, A19, A20, A21, A22, A23 and A24) Program Address (address to be programmed) Read Address (address to be read) Intelligent ID read address (Manufacture Code 0000H, Device Code 0002H) PD: Programming data RD: Read data ID: Intelligent Identifier (ID) Code CCMA1, CCMA2: SCMA1, SCMA2: PCMA1, PCMA2: RCMA1, RCMA2: ICMA1, ICMA2: 14 Command adddress for chip erase Command address for sector erase Command address for program Command address for Read/Reset Command address for intelligent ID read See "Command Address Table for 8-bit Mode" in page 16. To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 Command Table for 16-bit Mode*1 Command Bus 1st Bus Cycle Write Cycle Read/Reset 1 2 Read/Reset 2 4 Read Intelligent ID Codes 4 Byte Program 4 Sector Erase 6 Chip Erase 6 Sector Erase Suspend 1 Sector Erase Resume 1 Write -- F0F0H Write 2nd Bus Write/Read Cycle 3rd Bus Write Cycle 4th Bus Write/Read Cycle Write Read RA Write Write Write Write RA Write Write Write RD Read IA Write PCMA1 AAAAH PCMA2 5555H PCMA1 A0A0H Write Write RD ICMA1 AAAAH ICMA2 5555H ICMA1 9090H Write 6th Bus Write Cycle Read RCMA1 AAAAH RCMA2 5555H RCMA1 F0F0H Write 5th Bus Write Cycle ID Write PA PD Write SCMA1 AAAAH SCMA2 5555H SCMA1 8080H SCMA1 AAAAH SCMA2 5555H Write Write Write Write Write SA 3030H Write CCMA1 AAAAH CCMA2 5555H CCMA1 8080H CCMA1 AAAAH CCMA2 5555H CCMA1 1010H Write CA B0B0H Write CA 3030H Notes: CA: SA: PA: RA: IA: Chip Address. (address in chip selected by A22, A23 and A24) Sector Address (address in 128 KB selected by A17, A18, A19, A20, A21, A22, A23 and A24) Program Address (address to be programmed) Read Address (address to be read) Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H) PD: Programming data RD: Read data ID: Intelligent Identifier (ID) Code CCMA1, CCMA2: SCMA1, SCMA2: PCMA1, PCMA2: RCMA1, RCMA2: ICMA1, ICMA2: Command address for chip erase Command address for sector erase Command address for program Command address for Read/Reset Command address for intelligent ID read See "Command Address Table for 16-bit Mode" in page 16. *1: Address number is not contained "A0". 15 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 COMMAND DEFINITION TABLE (Continued) Command Address Table for 8-bit Mode MB98A81273, 81373, 81473, 81573 Command Address MB98A81063 CCMA1 (CA AND 000001h) OR AAAAh (CA AND 000001h) OR AAAh CA CCMA2 (CA AND 000001h) OR 5554h (CA AND 000001h) OR 554h CA SCMA1 (SA AND 000001h) OR AAAAh (SA AND 000001h) OR AAAh CA SCMA2 (SA AND 000001h) OR 5554h (SA AND 000001h) OR 554h CA PCMA1 (PA AND 000001h) OR AAAAh (PA AND 000001h) OR AAAh CA PCMA2 (PA AND 000001h) OR 5554h (PA AND 000001h) OR 554h CA RCMA1 (RA AND 000001h) OR AAAAh (RA AND 000001h) OR AAAh CA RCMA2 (RA AND 000001h) OR 5554h (RA AND 000001h) OR 554h CA ICMA1 (IA AND 000001h) OR AAAAh (IA AND 000001h) OR AAAh CA ICMA1 (IA AND 000001h) OR 5554h (IA AND 000001h) OR 554h CA MB98A81183 Command Address Table for 16-bit Mode 16 Command Address MB98A81063 MB98A81183 MB98A81273, 81373, 81473, 81573 CCMA1 5555h 555h CA CCMA2 2AAAh 2AAh CA SCMA1 5555h 555h CA SCMA2 2AAAh 2AAh CA PCMA1 5555h 555h CA PCMA2 2AAAh 2AAh CA RCMA1 5555h 555h CA RCMA2 2AAAh 2AAh CA ICMA1 5555h 555h CA ICMA1 2AAAh 2AAh CA To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 WRITE OPERATION STATUS Hardware Sequence Flag Table D7, D15 D6, D14 D5, D13 D3, D11 D2, D10*4 R/B*4 D7, D15 Toggle 0 0 1 0 0 Toggle 0 1 Toggle 0 (1) 1 1 0 0 *1 1 (2) Data Data Data Data Data 1 Erase Suspend*4 Program D7, D15 *2 0 0 *1, *3 0 Programming D7, D15 Toggle 1 0 1 0 0 Toggle 1 1 N/A 0 D7, D15 Toggle 1 0 N/A 0 Status Programming Erasing In Progress Exceeded Time Limits Erase Suspend Read Erasing Erase Suspend*4 Program Notes: (1): Erase Suspended Sector (2): Non-Erase Suspended Sector *1. Performing successive read operations from the erase-suspended sector will cause D2, D10 to toggle. *2. Performing successive read operations from any address will cause D6, D14 to toggle. *3. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the D2, D10 bit. However, successive reads from the erase-suspended sector will cause D2, D10 to toggle. *4. Not applied for MB98A81063. D7, D15 (Data Polling) The card features Data Polling as a method to indicate to the host that the Program/Erase Operation are in progress or completed. During the program operation an attempt to read the program address will produce the compliment of the data last written to D7/D15. Upon completion of the program operation, an attempt to read the program address will produce the true data last written to D7/D15. During the erase operation, an attempt to read the erase address will produce a "0" at the D7/D15 output. Upon completion of the erase operation an attempt to read the device will produce a "1" at the D7/D15 output. For Chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Even if the device has completed the operation and D7/D15 has a valid data, the data outputs on D0 to D6/D8 to D14 may be still invalid. The valid data on D0 to D7/D8 to D15 will be read on the successive read attempts. The Data Polling feature is only active during the programming operation, erase operation, sector erase timeout, Erase Suspend Read mode and Erase Suspend Program mode. D6, D14 (Toggle Bit l) The card also features the "Toggle Bit" as a method to indicate to the host system that the Program/Erase Operation are in progress or completed. During an Program or Erase cycle, successive attempts to read (OE or CE toggling) data from the card will result in D6/D14 toggling between one and zero. Once the Program or Erase cycle is completed, D6/D14 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is also active during the sector time out. Either CE or OE toggling will cause the D6/D14 to toggle. 17 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 D5, D13 (Exceeded Timing Limits) D5/D13 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under these conditions D5/D13 will produce a "1". This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of the card under this condition. If this failure condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation. The chip must be reset to use other sectors. Write the Reset command sequence to the chip, and then execute Program or Erase command sequence. This allows the system to continue to use the other active sectors in the chip. If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused). The D5/D13 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the card locks out and never completes the card operation. Hence, the system never reads a valid data on D7/D15 bit and D6/D14 never stops toggling. Once the card has exceeded timing limits, the D5/D13 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. D3, D11 (Sector Erase Timer) After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3/D11 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the card has been written with a valid erase command, D3/D11 may be used to determine if the sector erase timer window is still open. If D3/D11 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3/D11 is low ("0"), the card will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of D3/D11 prior to and following each subsequent sector erase command. If D3/D11 were high on the second status check, the command may not have been accepted. Refer to Table : Hardware Sequence Flags. D2, D10 (Toggle Bit ll, not applied for MB98A81063) This Toggle bit, along with D6, can be used to determine whether the card is in the Erase operation or in Erase Suspend. Successive reads from the erasing sector will cause D2 to toggle during the Erase operation. If the card is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause D2 to toggle. When the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic `1` at the D2 bit. D6 is different from D2 in that D6 toggles only when the standard Program or Erase, or Erase Suspend Program operation is in progress. R/B (Ready/Busy, not applied for MB98A81063) The card provides a R/B output pin as a way to indicate to the system that the program or erase operation are either in progress or has been completed. If the output is low, the card is busy with either a program or erase operation. If the card is placed in an Erase Suspend mode, the R/B output will be high. During programming, the R/B pin is driven low after the rising edge of the fourth WE pulse. During an erase operation, the R/B pin is driven low after the rising edge of the sixth WE pulse. The R/B pin will indicate a busy condition during the RESET pulse. 18 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART Fig. 3 - PROGRAM FLOWCHART START SET PA SET ADDRESS PCMA1,PCMA2*2 WRITE COMMAND (PCMA1/AAH or AAAAH)*2 WRITE COMMAND (PCMA2/55H or 5555H)*2 INCREMENT PA WRITE COMMAND (PCMA1/A0H/A0A0H)*2 WRITE DATA (PA/PD) DATA POLLING or TOGGLE BIT *1 NO LAST ADDRESS ? YES COMPLETED *1 See Fig. 7, 6, 9, 10. *2 See "COMMAND DEFINITION TABLE". Notes: PD : PROGRAM DATA PA : PROGRAM ADDRESS 19 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 4 - CHIP ERASE FLOWCHART START SET CA SET ADDRESS (CCMA1,CCMA2)*2 WRITE COMMAND (CCMA1/AAH or AAAAH)*2 WRITE COMMAND (CCMA2/55H or 5555H)*2 INCREMENT CA WRITE COMMAND (CCMA1/80H or 8080H)*2 WRITE COMMAND (CCMA1/AAH or AAAAH)*2 WRITE COMMAND (CCMA2/55H or 5555H)*2 WRITE COMMAND (CCMA1/10H or 1010H)*2 DATA POLLING or TOGGLE BIT *1 YES DESIRED OTHER CHIPS ERASE ? NO COMPLETED *1 See Fig. 7, 8, 9, 10. *2 See "COMMAND DEFINITION TABLE". Note: CA : CHIP ADDRESS 20 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 5 - SECTOR ERASE FLOWCHART START SET SA SET ADDRESS SCMA1,SCMA2*3 WRITE COMMAND (SCMA1/AAH or AAAAH)*3 WRITE COMMAND (SCMA2/55H or 5555H)*3 WRITE COMMAND (SCMA1/80H or 8080H)*3 WRITE COMMAND (SCMA1/AAH or AAAAH)*3 WRITE COMMAND (SCMA2/55H or 5555H)*3 WRITE COMMAND (SA/30H or 3030H) DESIRED OTHER SECTORS ERASE ? *2 YES WRITE COMMAND (SA/30H or 3030H) NO DATA POLLING or TOGGLE BIT *1 COMPLETED *1 See Fig.7, 8, 9, 10. *2 Possible for the sectors in a chip *3 See "COMMAND DEFINITION TABLE". Note: SA : SECTOR ADDRESS 21 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 6 - ERASE SUSPEND FLOWCHART EXECUTING SECTOR ERASE WRITE COMMAND (CA/B0H or B0B0H) READ DATA (SA)*1 Yes Toggle bit=Toggle?*1 No Read or Program*2 No STOP Erase Suspend mode? Yes WRITE COMMAND (CA/30H or 3030H) FINISHED *1 Detection whether suspend mode is valid can be done by Data Polling and R/B also. (MB98A81063 does not have R/B). *2 Only Read operation for MB98A81063. Notes: CA: CHIP ADDRESS SA: SECTOR ADDRESS RA: READ ADDRESS 22 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 7 - DATA POLLING FLOWCHART: x 8-bit mode No.1 START TIMER START *1 READ (VA) *2 D7=Data? Yes No No D5=1 or Time-up? Yes READ (VA) *2 D7=Data? Yes No ERROR COMPLETED *1 User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". *2 ProgramVA=PA Chip EraseVA=CA Sector EraseVA=SA 23 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 8 - TOGGLE BIT FLOWCHART: x 8-bit mode No.1 START TIMER START *1 READ (VA) *2 D6=Toggle? No Yes No D5=1 or Time-up? Yes READ (VA) *2 D6=Toggle? No Yes ERROR COMPLETED *1 User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". *2 Program VA=PA Chip Erase VA=CA Sector EraseVA=SA 24 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 9 - DATA POLLING FLOWCHART: x 16-bit mode START EF=0 *1 User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". TIMER START *1 *2 Program VA=PA Chip Erase VA=CA Sector EraseVA=SA READ (VA) *2 Notes: D7=Data? Yes No No EF: EF=0: EF=1: EF=2: EF=3: Error Flag Operation Completed Lower Byte Error Upper Byte Error Lower/Upper Byte Error D5=1 or Time-up? Yes 1 READ (VA) *2 D7=Data? READ (VA) *1 Yes Yes No D15=Data? EF=1 1 No No D13=1 or Time-up? Yes READ (VA) Yes D15=Data? No EF=EF+2 EF=0? No Yes COMPLETED ERROR 25 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM / ERASE FLOWCHART (Continued) Fig. 10 - TOGGLE BIT FLOWCHART: x 16-bit mode START EF=0 *1 User sets the time period referring to "PROGRAM AND ERASE PERFORMANCES". TIMER START *1 *2 Program VA=PA Chip Erase VA=CA Sector EraseVA=SA READ (VA) *2 Notes: D6=Toggle? No Yes No EF: EF=0: EF=1: EF=2: EF=3: Error Flag Operation Completed Lower Byte Error Upper Byte Error Lower/Upper Byte Error D5=1 or Time-up? Yes 1 READ (VA) READ (VA) *1 D6=Toggle? No No Yes D14=Toggle? EF=1 1 Yes No D13=1 or Time-up? Yes READ (VA) No D14=Toggle? Yes EF=EF+2 EF=0? No Yes COMPLETED 26 ERROR To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 ABSOLUTE MAXIMUM RATINGS (See WARNING) Parameter Symbol Value Unit Supply Voltage VCC -0.5 to +6.0 V Input Voltage VIN -0.5 to VCC +0.5 V Output Voltage VOUT -0.5 to VCC +0.5 V Temperature under Bias TA 0 to +60 C Storage Temperature TSTG -30 to +70 C WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. RECOMMENDED OPERATING CONDITIONS (Referenced to VSS) Parameter VCC Supply Voltage Ground Ambient Temperature Symbol Min. Typ. Max. Unit VCC 4.75 5.0 5.25 V GND -- 0 -- V TA 0 -- 55 C WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating conditions ranges Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. CAPACITANCE Parameter (TA = 25C, f = 1 MHz, VIN = VI/O = GND) Max. Unit Symbol Min. Input Capacitance *1 CIN -- 75 pF I/O Capacitance *2 CI/O -- 50 pF Notes: *1 This value does not apply to CE1, CE2, WE, REG and RESET. *2 This value does not apply to CD1, CD2, BVD1 and BVD2. 27 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 DC CHARACTERISTICS Parameter Test Conditons Value Min. Typ. Max. Unit VCC = VCC max., VIN = 0 V or VCC ILI -- 1.0 20 A Output Leakage Current *2 VCC = VCC max., VIN = 0 V or VCC ILO -- 1.0 20 A VCC = VCC max. CE1, CE2 = VCC VIN = 0 V or VCC ISB1 -- 0.5 1.7 mA VCC = VCC max., CE1, CE2 = VIH VIN = VIL or VIH ISB2 -- 4.0 8.0 mA Active Read Current VCC = VCC max., CE1, CE2 = VIL Cycle = 200 ns, IOUT = 0 mA ICC1 -- 100 160 mA Program Current Program in progress (x 16 mode) ICC2 -- -- 120 mA Erase Current Erase in progress (x 16 mode) ICC3 -- -- 120 mA Input Leakage Current *1 Standby Current Input Low Voltage -- VIL -0.3 -- 0.8 V Input High Voltage -- VIH 2.4 -- VCC+0.3 V Output Low Voltage IOL = 3.2 mA, VCC = VCC min. VOL -- -- 0.4 V Output High Voltage *3 IOH = 2.0 mA, VCC = VCC min. VOH 3.8 -- -- V 3.2 3.7 4.2 V -- 3.8 -- V Low VCC Lock-out Voltage Common Memory Attribute Memory Notes: *1 This value does not apply to CE1, CE2, WE and REG. *2 This value does not apply to BVD1, BVD2, CD1 and CD2. *3 This value does not apply to BVD1 and BVD2. 28 Symbol VLKO To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 AC TEST CONDITIONS Fig. 11 - AC TEST CONDITIONS * Input Pulse Levels: VIH = 2.6 V, VIL = 0.6 V * Output Load +5 V * Input Pulse Rise and Fall Times: 5 ns (Transient between 0.8 V and 2.4 V) R1 * Timing Reference Levels DOUT (I/O) R2 CL R1 R2 CL Load 1.8 K 990 100 pF Load 1.8 K 990 5 pF Input: VIL = 0.8 V, VIH = 2.4 V Output: VOL = 0.8 V, VOH = 2.0 V * Including jig and stray capacitance Parameter Measured All parameters except tCLZ, tOLZ, tCHZ, tOHZ, tRCLZ, tROLZ, tRCHZ and tROHZ tCLZ, tOLZ, tCHZ, tOHZ, tRCLZ, tROLZ, tRCHZ and tROHZ PROGRAM AND ERASE PERFORMANCES MAIN MEMORY PROGRAM / ERASE PERFORMANCE (MB98A81063) Parameter Min. Typ. Max. Unit Byte Program Time *1 -- 8 500 s Chip Programming Time *1 -- 4.2 25 Sec. Sector Erase Time *2 -- 1 15 Sec. Program/Erase Cycles 100,000 -- -- Cycles Min. Typ. Max. Unit Byte Program Time *1 -- 8 500 s Chip Programming Time *1 -- 8.4 50 Sec. Sector Erase Time *2 -- 1 15 Sec. Program/Erase Cycles 100,000 -- -- Cycles Notes: *1 Excludes system-level overhead. *2 Excludes 00H programming prior to erasure. (MB98A81183) Parameter Notes: *1 Excludes system-level overhead. *2 Excludes 00H programming prior to erasure. 29 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PROGRAM AND ERASE PERFORMANCES (Continued) (MB98A81273, 81373, 81473, 81573) Parameter Min. Typ. Max. Unit Byte Programming Time *1 -- 8 500 s Chip Programming Time *1 -- 16.8 100 Sec. Sector Erase Time *2 -- 1 15 Sec. Program/Erase Cycles 100,000 -- -- Cycles Min. Typ. Max. Unit -- -- 1 ms 100,000 -- -- Times Notes: *1 Excludes system-level overhead. *2 Excludes 00H programming prior to erasure. ATTRIBUTE MEMORY PROGRAM PERFORMANCE Parameter Byte Program Time Number of Program per Byte AC CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) MAIN MEMORY READ CYCLE*1 Parameter Symbol Min. Max. Unit Read Cycle Time tRC 150 -- ns Card Enable Access Time tCE -- 150 ns tACC -- 150 ns Output Enable Access Time tOE -- 75 ns Card Enable to Output in Low-Z*2 tCLZ 5 -- ns Card Disable to Output in High-Z*2 tCHZ -- 60 ns Output Enable to Output in Low-Z*2 tOLZ 5 -- ns Output Disable to Output in High-Z*2 tOHZ -- 60 ns Output Hold from Address, CE, or OE Change *3 tOH 5 -- ns Ready Time from RESET tRDY -- 20 ms Address Access Time Notes: *1 Rise/Fall time < 5 ns. *2 Transition is measured at the point of 500 mV from steady state voltage. This parameter is specified using Load ll in Fig. 11. *3 This parameter is specified from the rising edge of OE, CE1 or CE2, whichever occurs first. 30 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 AC CHARACTERISTICS (Continued) (Recommended operating conditions unless otherwise noted.) MAIN MEMORY PROGRAM / ERASE CYCLE*1 *2 Parameter Symbol Min. Typ. Max. Unit Write Cycle Time tWC 150 -- -- ns Address Setup Time tAS 20 -- -- ns Address Hold Time tAH 20 -- -- ns Data Setup Time tDS 50 -- -- ns Data Hold Time tDH 20 -- -- ns Read Recovery Time (WE control) tGHWL 10 -- -- ns Read Recovery Time (CE control) tGHEL 10 -- -- ns Output Enable Hold Time tOEH 10 -- -- ns Card Enable Setup Time tCS 20 -- -- ns Card Enable Hold Time tCH 0 -- -- ns Write Enable Pulse Width tWP 80 -- -- ns Write Enable Setup Time tWS 0 -- -- ns Write Enable Hold Time tWH 0 -- -- ns Card Enable Pulse Width tCP 100 -- -- ns Duration of Byte Program Operation (WE control) tWHWH1 -- 8 -- s Duration of Erase Operation *3 (WE control) tWHWH2 -- 1 15 s Duration of Byte Program Operation (CE control) tEHEH1 -- 8 -- s Duration of Erase Operation *3 (CE control) tEHEH2 -- 1 15 s VCC Setup Time *4 tVCS 50 -- -- s Reset Pulse Width tRP 500 -- -- ns tBSY 100 -- -- ns Busy Delay Time Notes: *1 Read timing parameters during Program/Erase operations are the same as those during read only operations. Refer to AC characteristics for Main Memory Read Cycle. *2 Rise/Fall time 5 ns. *3 These do not include the preprogramming time. *4 Not 100% tested. 31 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 AC CHARACTERISTICS (Continued) ATTRIBUTE MEMORY READ CYCLE *1 Parameter Symbol Min. Max. Unit Read Cycle Time tRRC 250 -- ns Address Access Time tRAA -- 250 ns Card Enable Access Time tRCE -- 250 ns Output Enable Access Time tROE -- 125 ns Output Hold from Address Change tROH 5 -- ns Card Enable to Output Low-Z *2 tRCLZ 5 -- ns Output Enable to Output Low-Z *2 tROLZ 5 -- ns Card Enable to Output High-Z *2 tRCHZ -- 60 ns Output Enable to Output High-Z *2*3 tROHZ -- 60 ns Notes: *1 Rise/Fall time < 5 ns. *2 Transition is measured at the point of 500 mV from steady state voltage. This parameter is specified using Load ll in Fig. 3. *3 This parameter is specified from the rising edge of OE, CE1 or CE2, whichever occurs first. ATTRIBUTE MEMORY PROGRAM CYCLE Parameter 32 Symbol Min. Max. Unit Address Setup Time tRAS 20 -- ns Card Enable Setup Time tRCS 0 -- ns Output Enable Setup Time tOES 20 -- ns Write Pulse Width tRWP 100 1000 ns Address Hold Time tRAH 50 -- ns Data Setup Time tRDS 50 -- ns Data Hold Time tRDH 20 -- ns Card Enable Hold Time tRCH 0 -- ns Output Enable Hold Time tROEH 20 -- ns Program Time tRWR -- 1 ms To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM MAIN / ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (WE = VIH, REG = VIH)*1 READ CYCLE 1: CE1 = OE = VIL, CE2 = VIH: x 8-bit No.1 Bus Organization tRC (tRRC) A0 to A24 (A0 to A11) VIH VIL tACC (tRAA) tOH (tROH) VOH D0 to D7 DATA VALID PREVIOUS DATA VALID VOL READ CYCLE 2: CE1 = VIH, CE2 = OE = VIL: x 8-bit No.2 Bus Organization CE1 = CE2 = OE = VIL: x 16-bit Bus Organization tRC (tRRC) A1 to A24 *2 (A1 to A11) VIH VIL tACC (tRAA) tOH (tROH) D8 to D15 or D0 to D15 VOH PREVIOUS DATA VALID DATA VALID VOL :Undefined Notes: *1 The addresses and parameters in ( ) are applied for attribute memory access. *2 A0 = Either VIH or VIL. 33 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN / ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM (Continued) (WE = VIH, REG = VIH)*1 READ CYCLE 3: CE2 = VIH: x 8-bit No.1 Bus Organization A0 to A24 (A0 to A11) VIH VIL tACC (tRAA) VIH CE1 VIL tCE tCHZ (tRCE) (tRCHZ) tCLZ (tRCLZ) VIH OE VIL tOE tOHZ (tROE) (tROHZ) tOLZ V OH High-Z (tROLZ) DATA VALID D0 to D7 VOL :Undefined Note: *1 The addresses and parameters in ( ) are applied for attribute memory access. 34 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN / ATTRIBUTE MEMORY READ CYCLE TIMING DIAGRAM(Continued)(WE = VIH, REG = VIH)*1 READ CYCLE 4: CE1 = VIH: x 8-bit No.2 Bus Organization A1 to A24 *2 (A1 to A11) VIH VIL tACC (tRAA) tCHZ (tRCHZ) CE2 VIH VIL tCE tCLZ (tRCE) tOHZ (tROHZ) (tRCLZ) OE VIH VIL tOE tOLZ (tROE) (tROLZ) D8 to D15 VOH High-Z DATA VALID VOL READ CYCLE 5: CE1 = CE2 = VIL: x 16-bit Bus Organization A1 to A24 *2 (A1 to A11) VIH VIL tACC (tRAA) tCHZ (tRCHZ) CE1=CE2 VIH VIL tCE tCLZ (tRCE) tOHZ (tROHZ) (tRCLZ) OE VIH VIL tOE tOLZ (tROE) (tROLZ) D0 to D15 VOH High-Z DATA VALID VOL :Undefined Notes: *1 The addresses and parameters in ( ) are applied for attribute memory access. *2 A0 = Either VIH or VIL. 35 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN MEMORY PROGRAM CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH) A0 to A24 *1 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle Data Polling Cycle PCMA1 *2 PCMA2 *2 PCMA1 *2 PA *2 PA *2 VIH VIL tRC tWC tAS tRC tAH VIH CE*1 VIL tCH tCS tOEH VIH OE VIL tWPH tGHWL tWHWH1 VIH WE VIL tBSY tDH tWP Data *1 VIH/OH tDS VIL/OL AAH (AAAAH) VOH 55H (5555H) A0H (A0A0H) PD *2 D7,D15 PD *2 Data tVCS R/B VOL VCC :Undefined Notes: *1 See "FUNCTION TRUTH TABLE". *2 PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See "COMMAND DEFINITION TABLE". 36 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN MEMORY PROGRAM CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH) A0 to A24 *1 VIH 1st Bus Cycle 2nd Bus Cycle 3rd Bus Cycle 4th Bus Cycle Data Polling Cycle PCMA1 *2 PCMA2 *2 PCMA1 *2 PA *2 PA *2 VIL tWC tRC tAS tRC tAH VIH WE VIL tWH tWS OE tOEH VIH VIL tGHEL tEHEH1 tCPH VIH CE*1 VIL tDH tBSY tCP Data *1 VIH/OH tDS VIL/OL AAH (AAAAH) VOH 55H (5555H) A0H (A0A0H) PD *2 D7,D15 PD *2 Data tVCS R/B VOL VCC :Undefined Notes: *1 See "FUNCTION TRUTH TABLE". *2 PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See "COMMAND DEFINITION TABLE". 37 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIH) A0 to A24 *1 1st Bus Cycle CCMA1/ SCMA1 *2 VIH VIL 2nd Bus Cycle CCMA2/ SCMA2 *2 3rd Bus Cycle CCMA1/ SCMA1 *2 4th Bus Cycle CCMA1/ SCMA1 *2 5th Bus Cycle CCMA2/ SCMA2 *2 6th Bus Cycle CCMA1/ SA *2 tWC tAS tAH VIH CE*1 VIL tCH tCS VIH OE VIL tWPH tGHWL VIH WE VIL tDH tWP Data *1 VIH/OH tDS VIL/OL AAH (AAAAH) 55H (5555H) 80H (8080H) AAH (AAAAH) 55H (5555H) 10H/30H (1010H/3030H) tVCS VCC :Undefined Notes: *1 See "FUNCTION TRUTH TABLE". *2 CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector Erase, SA = Sector Address. See "COMMAND DEFINITION TABLE". 38 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN MEMORY ERASE CYCLE TIMING DIAGRAM (CE = CONTROLLED, REG = VIH) A0 to A24 *1 1st Bus Cycle CCMA1/ SCMA1 *2 VIH VIL 2nd Bus Cycle CCMA2/ SCMA2 *2 3rd Bus Cycle CCMA1/ SCMA1 *2 4th Bus Cycle CCMA1/ SCMA1 *2 5th Bus Cycle CCMA2/ SCMA2 *2 6th Bus Cycle CCMA1/ SA *2 tWC tAS tAH VIH WE VIL tWH tWS VIH OE VIL tGHEL tCPH VIH CE*1 VIL tDH tCP Data *1 VIH/OH tDS VIL/OL AAH (AAAAH) 55H (5555H) 80H (8080H) AAH (AAAAH) 55H (5555H) 10H/30H (1010H/3030H) tVCS VCC :Undefined Notes: *1 See "FUNCTION TRUTH TABLE". *2 CCMA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector Erase, SA = Sector Address. See "COMMAND DEFINITION TABLE". 39 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN MEMORY DATA POLLING CYCLE TIMING DIAGRAM (REG = VIH) Command Write Cycle A0 to A24 *2 Data Polling Read Cycle VIH VA *1 VIL tWC CE*2 tACC VIH VIL tCHZ tCE OE VIH VIL tOEH WE tOE tOHZ VIH VIL *4 tWHWH1,2 (tEHEH1,2)*3 D7,D15 *2 D0 to D6 *2 D8 to D14 VIH/OH D7,D15 D7,D15 D7,D15 Valid Data VIL/OL VIH/OH VIL/OL D0 to D6, D8 to D14 D0 to D6, D8 to D14 Invalid Data D0 to D6, D8 to D14 Valid Data :Undefined Notes: *1 VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase. *2 See "FUNCTION TRUTH TABLE". *3 tEHEH1, 2 for CE Control. *4 Program/Erase operation is finished. 40 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 TIMING DIAGRAM (Continued) MAIN MEMORY TOGGLE BIT TIMING DIAGRAM (REG = VIH) Command Write Cycle A0 to A24 *2 VIH Toggle Bit Read Cycle VA *1 VA *1 VA *1 VA *1 VIL tRC CE*2 VIH VIL OE VIH VIL tOEH WE VIH VIL tOE Data *2 *3 VIH/OH *4 VIL/OL D6,D14 Toggle D6,D14 Toggle D6,D14 Stop Toggling Valid Data :Undefined Notes: *1 VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase. *2 See "FUNCTION TRUTH TABLE". *3 Program/Erase operation is finished. *4 PD, 10H (1010H) or 30H (3030H) 41 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 AC CHARACTERISTICS (Continued) (Recommended operating conditions unless otherwise noted.) ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) WRITE CYCLE 1: CE2 = VIH : x 8-bit No.1 Bus Organization VIH A0 to A11 VIL tRAS tRAH tRCH tRCS VIH CE1 VIL tROES tROEH VIH OE VIL tRWP VIH WE VIL tRDS VIH D0 to D7 tRDH High-Z High-Z DATA VALID VIL tRWR VOH High-Z D7 * 1 I7 O7 VOL : Undefined Note: *1 Data polling operation. 42 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 AC CHARACTERISTICS (Continued) (Recommended operating conditions unless otherwise noted.) ATTRIBUTE MEMORY WRITE CYCLE TIMING DIAGRAM (WE = CONTROLLED, REG = VIL) WRITE CYCLE 2: CE1 = CE2 : x 16-bit Bus Organization VIH A1 to A11 VIL tRAS tRAH tRCH tRCS VIH CE1=CE2 VIL tROES tROEH VIH OE VIL tRWP VIH WE VIL tRDS VIH D0 to D7 *1 tRDH High-Z High-Z DATA VALID VIL tRWR VOH D7 *2 High-Z I7 O7 VOL : Undefined Notes: *1 Inputs from D8 to D15 are not defined. *2 Data polling operation. 43 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 AC CHARACTERISTICS (Continued) (Recommended operating conditions unless otherwise noted.) R/B Timing Diagram During Program / Erase Operations (except for MB98A81063) CE WE Entire programming or erase operation R/B tRSY RESET Timing Diagram (except for MB98A81063) RESET Possible next operation tRP tRDY 44 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 UNIQUE FEATURES FOR FLASH MEMORY CARD 1. SPECIAL MONITORING PINS VCC 1.1 CD1, CD2: Card Detection Pins CD1 CD1 and CD2 are to detect whether or not the card has been correctly inserted. (See Fig. 12.) When the memory card has been correctly inserted, CD1 and CD2 are detected by the system. CD1, CD2 are tied to ground on the card side as shown in Fig. 12. (A) VCC CD2 (B) system side card side - Fig. 121.2 WP: Write Protect Pins This pin monitors the position of the Write Protect switch. As shown in Fig. 13, the Flash memory card has a Write Protect switch at the top of the card. To write to the card, the switch must be turned to the "Non Protect" position and the WE pin low. And at that time, L-level is output on the WP pin. To prevent writing to the card, the switch must be turned to the "Protect" position. At that time, H-level is output on the WP pin. WP Switch Flash Memory Card Non Protect Write Protect Switch Protect WP (output) - Fig. 13 - Protect H Non Protect L 45 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 CARD INFORMATION Memory Card have CIS (Card Information Structure) in Attribute memory. 1. CIS Address MB98A81063 MB98A81183 MB98A81273 MB98A81373 0000 h 01 h 0002 h 03 h 0004 h 53 h 0006 h 0D h 1D h 0E h FF h 000A h 15 h 000C h 1C h 000E h 04 h 0010 h 01 h 0012 h 46 h 0014 h 55 h 0016 h 4A h 0018 h 49 h 001A h 54 h 001C h 53 h 001E h 55 h 0020 h 00 h 0022 h 4D h 0024 h 42 h 0026 h 39 h 0028 h 38 h 002A h 41 h 002C h 38 h 002E h 30 h 0030 h 30 h 36 h MB98A81573 3E h 7E h 1E h 0008 h 0032 h MB98A81473 38 h 37 h 0034 h 33 h 0036 h 73 h 0038 h 65 h 003A h 72 h 003C h 69 h (Continued) 46 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 (Continued) Address MB98A81063 MB98A81183 MB98A81273 MB98A81373 003E h 65 h 0040 h 73 h 0042 h 00 h 0044 h FF h 0046 h 17 h 0048 h 03 h 004A h 41 h 004C h 01 h 004E h FF h 0050 h 18 h 0052 h 03 h 0054 h 04 h 0056 h A4 h D5 h FF h 005A h 1E h 005C h 07 h 005E h 02 h 0060 h 11 h 0062 h 01 h 0064 h 01 h 0066 h 01 h 0068 h 01 h 006A h FF h 006C h 10 h 006E h 06 h 0070 h CA h 0072 h FF h 0074 h 3C h 0076 h 00 h 02 h 45 h MB98A81573 3D h 0058 h 0078 h MB98A81473 9D h AD h 007A h FF h 007C h FF h CD h 0D h 47 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 2. Explanation for CIS Address MB98A81573 Attribute 0000 h 01 h Common memory device information tuple 0002 h 03 h Link to next tuple 0004 h 53 h Flash memory with 150 ns access time 0006 h 7E h 32MB device size 0008 h FF h End of list 000A h 15 h Level 1 version/product - information tuple 000C h 1C h Link to next tuple 000E h 04 h 0010 h 01 h 0012 h 46 h 0014 h 55 h 0016 h 4A h 0018 h 49 h 001A h 54 h 001C h 53 h 001E h 55 h 0020 h 00 h 0022 h 4D h 0024 h 42 h 0026 h 39 h 0028 h 38 h 002A h 41 h 002C h 38 h 002E h 30 h 0030 h 30 h 0032 h 37 h 0034 h 33 h 0036 h 73 h 0038 h 65 h 003A h 72 h 003C h 69 h 003E h 65 h 0040 h 73 h Conformed to JEIDA Ver.4.2/PCMCIA 2.1 Product/Maker Information for "FUJITSU MB98A80070 series" (Continued) 48 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 (Continued) Address MB98A81573 Attribute 0042 h 00 h 0044 h FF h End of list 0046 h 17 h Attribute memory device information tuple 0048 h 03 h Link to next tuple 004A h 41 h EEPROM with 250 ns access time 004C h 01 h 2 KB device size 004E h FF h End of list 0050 h 18 h JEDEC device ID tuple for common memory 0052 h 03 h Link to next tuple 0054 h 04 h Manufacture ID 0056 h 3D h Device ID 0058 h FF h End of list 005A h 1E h Device geometry information for common memory device tuple 005C h 07 h Link to next tuple 005E h 02 h System bus width is 2 Bytes 0060 h 11 h Erase block size is 64 KBytes 0062 h 01 h Read block size is 1 Byte 0064 h 01 h Program block size is 1 Byte 0066 h 01 h No special partitioning requirements 0068 h 01 h Non interleaved 006A h FF h End of list 006C h 10 h Checksum tuple 006E h 06 h Link to next tuple 0070 h CA h 0072 h FF h 0074 h 3C h 0076 h 00 h 0078 h 0D h Checksum 007A h FF h End of list 007C h FF h The end of chain tuple Offset to checksum area Length of check 49 To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 PACKAGE DIMENSIONS Dimention comform with PCMCIA/JEIDA. (PC CARD STANDARD) 68-PIN MEMORY CARD (CASE No.: CRD-68P-M17) 2-R1.00(.039) 1.600.05 (.063.002) 85.600.20(3.370.008) 10.50(.413) 1.000.05 (.039.002) 41.91 (1.650) REF 54.000.10 (2.126.004) 14.50 (.571) 1.000.05 (.039.002) "A" 10.50(.413) 1.000.05 (.039.002) 3.300.10(.130.004) Connector edge 3.300.20(.130.008) Base Details of "A" part 1.270.10(.050.004)TYP. 1PIN 1.270.10 (.050.004) C 50 1997 FUJITSU LIMITED K68017SC-3-3 Dimensions in mm (inches) To Top / Lineup / Index MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inhereut chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. http://www.fmap.com.sg/ F9811 FUJITSU LIMITED Printed in Japan 51