MC14020B 14-Bit Binary Counter The MC14020B 14-stage binary counter is constructed with MOS P-Channel and N-Channel enhancement mode devices in a single monolithic structure. This part is designed with an input wave shaping circuit and 14 stages of ripple-carry binary counter. The device advances the count on the negative-going edge of the clock pulse. Applications include time delay circuits, counter controls, and frequency-dividing circuits. http://onsemi.com MARKING DIAGRAMS Features * * * * * * * * Fully Static Operation Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range Buffered Outputs Available from stages 1 and 4 thru 14 Common Reset Line Pin-for-Pin Replacement for CD4020B These Devices are Pb-Free and are RoHS Compliant PDIP-16 P SUFFIX CASE 648 MC14020BCP AWLYYWWG 1 16 SOIC-16 D SUFFIX CASE 751B 14020BG AWLYWW 1 16 MAXIMUM RATINGS (Voltages Referenced to VSS) Parameter 16 14 020B ALYWG G TSSOP-16 DT SUFFIX CASE 948F Value Unit -0.5 to +18.0 V -0.5 to VDD + 0.5 V 1 Input or Output Current (DC or Transient) per Pin 10 mA 16 PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range -55 to +125 C Tstg Storage Temperature Range -65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C Symbol VDD Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. (c) Semiconductor Components Industries, LLC, 2011 June, 2011 - Rev. 7 1 SOEIAJ-16 F SUFFIX CASE 966 MC14020B ALYWG 1 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Indicator (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: MC14020B/D MC14020B PIN ASSIGNMENT TRUTH TABLE Q12 1 16 VDD Q13 2 15 Q11 Q14 3 14 Q10 Q6 4 13 Q8 Q5 5 12 Q9 Q7 6 11 R Q4 7 10 C VSS 8 9 Q1 Clock Reset Output State X 0 0 1 No Change Advance to Next State All Outputs are Low X = Don't Care LOGIC DIAGRAM Q1 Q4 9 Q5 7 Q12 1 5 Q13 2 Q14 3 CLOCK C 10 C R Q C Q C R Q C Q C R Q C Q C R Q C Q C R Q C Q C Q R RESET 11 Q6 = PIN 4 Q7 = PIN 6 Q8 = PIN 13 Q9 = PIN 12 Q10 = PIN 14 Q11 = PIN 15 VDD = PIN 16 VSS = PIN 8 ORDERING INFORMATION Package Shipping MC14020BCPG PDIP-16 (Pb-Free) 500 Units / Rail MC14020BDG SOIC-16 (Pb-Free) 48 Units / Rail MC14020BDR2G SOIC-16 (Pb-Free) 2500 Units / Tape & Reel MC14020BDTG TSSOP-16* 96 Units / Rail MC14020BFELG SOEIAJ-16 (Pb-Free) 2000 Units / Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 MC14020B ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) - 55_C Symbol "0" Level 25_C 125_C VDD Vdc Min Max Min Typ (Note 2) Max Min Max Unit VOL 5.0 10 15 - - - 0.05 0.05 0.05 - - - 0 0 0 0.05 0.05 0.05 - - - 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 - - - 4.95 9.95 14.95 5.0 10 15 - - - 4.95 9.95 14.95 - - - Vdc Input Voltage "0" Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 - - - 1.5 3.0 4.0 - - - 2.25 4.50 6.75 1.5 3.0 4.0 - - - 1.5 3.0 4.0 "1" Level VIH 5.0 10 15 3.5 7.0 11 - - - 3.5 7.0 11 2.75 5.50 8.25 - - - 3.5 7.0 11 - - - 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 - - - - - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 - - - - - 1.7 - 0.36 - 0.9 - 2.4 - - - - IOL 5.0 10 15 0.64 1.6 4.2 - - - 0.51 1.3 3.4 0.88 2.25 8.8 - - - 0.36 0.9 2.4 - - - mAdc Input Current Iin 15 - 0.1 - 0.00001 0.1 - 1.0 mAdc Input Capacitance (Vin = 0) Cin - - - - 5.0 7.5 - - pF Quiescent Current (Per Package) IDD 5.0 10 15 - - - 5.0 10 20 - - - 0.005 0.010 0.015 5.0 10 20 - - - 150 300 600 mAdc IT 5.0 10 15 Characteristic Output Voltage Vin = VDD or 0 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Source Sink Total Supply Current (Notes 3 & 4) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IOH Vdc Vdc mAdc IT = (0.42 mA/kHz)f + IDD IT = (0.85 mA/kHz)f + IDD IT = (1.43 mA/kHz)f + IDD 2. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 3. The formulas given are for the typical characteristics only at 25_C. 4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in mA (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.001. http://onsemi.com 3 mAdc MC14020B SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q1 tPHL, tPLH = (1.7 ns/pF) CL + 175 ns tPHL, tPLH = (0.66 ns/pF) CL + 82 ns tPHL, tPLH = (0.5 ns/pF) CL + 55 ns tPLH, tPHL VDD Vdc Min Typ (Note 6) Max 5.0 10 15 - - - 100 50 40 200 100 80 Unit ns ns Clock to Q14 tPHL, tPLH - (1.7 ns/pF) CL + 1735 ns tPHL, tPLH = (0.66 ns/pF) CL + 772 ns tPHL, tPLH = (0.5 ns/pF) CL + 535 ns 5.0 10 15 - - - 260 115 80 520 230 160 5.0 10 15 - - - 1820 805 560 3900 1725 1200 ns Propagation Delay Time Reset to Qn tPHL = (1.7 ns/pF) CL + 285 ns tPHL = (0.66 ns/pF) CL + 122 ns tPHL = (0.5 ns/pF) CL + 90 ns tPHL Clock Pulse Width Clock Pulse Frequency ns 5.0 10 15 - - - 370 155 115 740 310 230 tWH 5.0 10 15 500 165 125 140 55 38 - - - ns fmax 5.0 10 15 1.0 3.0 4.0 2.0 6.0 8.0 - - - MHz tTLH, tTHL 5.0 10 15 Reset Pulse Width tWL 5.0 10 15 3000 550 420 320 120 80 - - - ns Reset Recovery Time trec 5.0 10 15 - - - 65 25 15 130 50 30 ns Clock Rise and Fall Time - No Limit 5. The formulas given are for the typical characteristics only at 25_C. 6. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. http://onsemi.com 4 MC14020B VDD VDD 500 mF PULSE GENERATOR 0.01 mF CERAMIC ID C Q1 Q4 Qn R C Q1 Q4 Q R n 20 ns CL 20 ns CLOCK 20 ns 90% 50% 10% tWH 20 ns VDD tPLH VSS Figure 1. Power Dissipation Test Circuit and Waveform 4 8 16 tPHL 90% 50% 10% Q tTHL tTLH 2 CL CL CL 90% 50% 10% 50% DUTY CYCLE 1 CL VSS VSS CLOCK PULSE GENERATOR Figure 2. Switching Time Test Circuit and Waveforms 32 64 128 256 512 CLOCK RESET Q1 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Figure 3. Timing Diagram http://onsemi.com 5 1024 2048 4096 8192 16,384 CL MC14020B PACKAGE DIMENSIONS PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L DIM A B C D F G H J K L M S S -T- SEATING PLANE K H G D M J 16 PL 0.25 (0.010) M T A M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE A 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A A1 b 0.13 (0.005) c M 0.10 (0.004) http://onsemi.com 6 DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 MC14020B PACKAGE DIMENSIONS TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S EEE CCC CCC EEE K1 2X L/2 16 9 J1 SECTION N-N B -U- L J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 7 INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC14020B PACKAGE DIMENSIONS SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE K -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C -T- SEATING PLANE J M D DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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