INDUSTRIAL TEMPERATURE RANGE
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
1OCTOBER 2002
IDT5T9050
INDUSTRIAL TEMPERATURE RANGE
2.5V SINGLE DATA RATE
1:5 CLOCK BUFFER
TERABUFFER™ JR.
DESCRIPTION:
The IDT5T9050 2.5V single data rate (SDR) clock buffer is a single-ended
input to five single-ended outputs buffer built on advanced metal CMOS
technology. The SDR clock buffer fanout from a single input to five single-ended
outputs reduces the loading on the preceding driver and provides an efficient
clock distribution network. Multiple power and grounds reduce noise.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2002 Integrated Device Technology, Inc. DSC-5958/17
FEATURES:
• Optimized for 2.5V LVTTL
• Guaranteed Low Skew < 25ps (max)
• Very low duty cycle distortion < 300 (max)
• High speed propagation delay < 1.8ns. (max)
• Up to 200MHz operation
• Very low CMOS power levels
• Hot insertable and over-voltage tolerant inputs
• 1:5 fanout buffer
• 2.5V VDD
• Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
• Clock and signal distribution
GL
G
A
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
OUTPUT
CONTROL
Q1
Q2
Q3
Q4
Q5
INDUSTRIAL TEMPERATURE RANGE
2
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
TSSOP
TOP VIEW
PIN CONFIGURATION
GL GND
VDD VDD
GND GND
GND
G
VDD VDD
Q1Q2
Q5
GND
GND
Q3
A
Q4
VDD VDD
GND GND
GND
VDD
VDD
VDD
NC NC
19
15
16
17
18
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
Symbol Description Max Unit
VDD Power Supply Voltage –0.5 to +3.6 V
VIInput Voltage –0.5 to +3.6 V
VOOutput Voltage –0.5 to VDD +0.5 V
TSTG Storage Temperature –65 to +165 °C
TJJunction Temperature 1 5 0 °C
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol Parameter Min Typ. Max. Unit
CIN Input Capacitance —6—pF
CAPACITANCE(1) (TA = +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
Symbol Description Min. Typ. Max. Unit
TAAmbient Operating Temperature –40 +25 +85 °C
VDD Internal Power Supply Voltage 2.3 2.5 2.7 V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol I/O Type Description
A I LVTTL Clock input
GI LVTTL Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously
disabled to the level designated by GL(1).
GL I LVTTL Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW.
Qn O LVTTL Clock outputs
VDD PWR Power supply for the device core, inputs, and outputs
GND PWR Power supply return for power
NOTE:
1. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt
pulses or be able to tolerate them in down stream circuitry.
INDUSTRIAL TEMPERATURE RANGE
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
3
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2 . Voltage required to maintain a logic HIGH.
3. Voltage required to maintain a logic LOW.
4. Typical values are at VDD = 2.5V, +25°C ambient.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol Parameter Test Conditions Min. Typ.(4) Max Unit
IIH Input HIGH Current VDD = 2.7V VI = VDD/GND — — ±5 µA
IIL Input LOW Current VDD = 2.7V VI = GND/VDD ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 +3.6 V
VIH DC Input HIGH(2) 1.7 — V
VIL DC Input LOW(3) — 0.7 V
VOH Output HIGH Voltage IOH = -12mA VDD - 0.4 — V
IOH = -100µAVDD - 0.1 — V
VOL Output LOW Voltage IOL = 12mA — 0.4 V
IOL = 100µA — 0.1 V
INPUT AC TEST CONDITIONS
Symbol Parameter Value Units
VIH Input HIGH Voltage VDD V
VIL Input LOW Voltage 0V
VTH Input Timing Measurement Reference Level(1) VDD/2 V
tR, tFInput Signal Edge Rate(2) 2 V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions(1) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current VDD = Max., Reference Clock = LOW 1 1.5 mA
Outputs enabled, All outputs unloaded
IDDD Dynamic VDD Power Supply VDD = Max., CL = 0 pF 100 150 µA/MHz
Current per Output
ITOT Total Power VDD Supply Current VDD = 2.5V., FREFERENCE CLOCK = 100MHz, CL = 15pF 50 65 mA
VDD = 2.5V., FREFERENCE CLOCK = 200MHz, CL = 15pF 75 100
NOTE:
1. The termination resistors are excluded from these measurements.
INDUSTRIAL TEMPERATURE RANGE
4
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(4)
Symbol Parameter Min. Typ. Max Unit
Skew Parameters
tSK(O) Same Device Output Pin-to-Pin Skew(1) ——25 ps
tSK(P) Pulse Skew(2) ——300 ps
tSK(PP) Part-to-Part Skew(3) ——300 ps
Propagation Delay
tPLH Propagation Delay A to Qn ——1.8 ns
tPHL
tROutput Rise Time (20% to 80%) 3 5 0 —850 ps
tFOutput Fall Time (20% to 80%) 3 5 0 —850 ps
fOFrequency Range ——200 MHz
Output Gate Enable/Disable Delay
tPGE Output Gate Enable to Qn ——3.5 ns
tPGD Output Gate Enable to Qn Driven to GL Designated Level —— 3ns
NOTES:
1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device.
2 . Skew measured is the difference between propagation delay times tPHL and tPLH of any output under identical input and output transitions and load conditions on any one device.
3 . Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD levels
and temperature.
4. Guaranteed by design.
Propagation and Skew Waveforms
NOTE: Pulse Skew is calculated using the following expression:
tSK(P) = | tPHL - tPLH |
where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not
valid measurements for this calculation because they are not taken from the same pulse.
AC TIMING WAVEFORMS
tPLH tPHL
tSK(O) tSK(O)
Qn
Qm
VOH
VTH
VOL
VOH
VTH
VOL
A
VIH
VTH
VIL
tWtW
1/fo
INDUSTRIAL TEMPERATURE RANGE
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
5
NOTE:
As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their G signal to avoid this problem.
tPLH
GL
G
Qn
VIH
VTH
VIL
VIH
VTH
VIL
VOH
VTH
VOL
tPGD tPGE
A
VIH
VTH
VIL
Gate Disable/Enable Showing Runt Pulse Generation
INDUSTRIAL TEMPERATURE RANGE
6
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
Test Circuit for Input/Output
INPUT/OUTPUT TEST CONDITIONS
Symbol VDD = 2.5V ± 0.2V Unit
VTH VDD / 2 V
R1 100 Ω
R2 100 Ω
CL15 pF
VDD
D.U.T.
CL
VDD
R1
R2
QnA
Pulse
Generator
VIN 3 inch, ~5 0Ω
Transmission Line
VDD
R1
R2
TEST CIRCUIT AND CONDITIONS
INDUSTRIAL TEMPERATURE RANGE
IDT5T9050
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER JR.
7
ORDERING INFORMATION
IDT XXXXX Package
Device Type
5T9050 2.5V S ingle Data Rate 1:5 C lock Buffe r
Terabuffer Jr.
Thin Shrink Small O utline Package
PG
XX
Package
X
-40°C to +85°C (Industrial)
I
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com
Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459
www.idt.com
