Winbond
ExpressCard™
Power Interface Switch
W83L351 Series
W83L351 Series
W83L351 Series
Data Sheet Revision History
NO PAGES DATES VERSION VERSION
ON WEB MAIN CONTENTS
1. All Apr. /07 1.0 N.A All versions before 1.0 are preliminary
versions.
2 28 July 5, 2007 1.1 Update the ordering information and add
the taping spec.
3
4
5
6
7
Publication Date: July 5, 2007
-I- Revision 1.10
W83L351 Series
Table of Contents-
1. FEATURES ................................................................................................................................. 1
2. PIN CONFIGURATION AND DESCRIPTION ............................................................................ 2
3. APPLICATION CIRCUIT.............................................................................................................5
4. INTERNAL BLOCK DIAGRAM ................................................................................................... 6
5. ABSOLUTE MAXIMUM RATINGS ............................................................................................. 7
6. RECOMMENDED OPERATING CONDITIONS ......................................................................... 8
7. ELECTRICAL CHARACTERISTICS........................................................................................... 9
8. SWITCHING CHARACTERISTICS .......................................................................................... 12
9. FUNCTIONAL TRUTH TABLES ............................................................................................... 13
10. TYPICAL OPERATING WAVEFORMS .................................................................................... 15
11. EXPRESSCARD TIMING DIAGRAMS ..................................................................................... 20
12. PACKAGE DIMENSION ........................................................................................................... 24
13. ORDERING INFORMATION .................................................................................................... 28
14. TOP MARKING SPECIFICATION ............................................................................................ 29
-II-
W83L351 Series
1. FEATURES
•
•
•
•
•
•
•
•
•
Meets the ExpressCard™ Standard (ExpressCard|34 or ExpressCard|54)
Compliant with the ExpressCard™ Compliance Checklists
ExpressCard Compliance ID: EC100098 (W83L351G), EC100115 (W83L351YG/YCG)
Fully Satisfies the ExpressCard™ Implementation Guidelines
Supports System with WAKE Function
TTL-Logic Compatible Inputs
Short Circuit and Thermal Protection
0℃ to 70℃ Ambient Operating Temperature Range
Available in a 20-pin TSSOP or a 20-pin QFN
Publication Date: July 5, 2007
-1- Revision 1.10
W83L351 Series
2. PIN CONFIGURATION AND DESCRIPTION
W83L351G
(Top View) W83L351YG
W83L351YCG
(
To
p
View
)
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
AUXOUT
NC
NC
1.5VIN
1.5VOUT
STBY#
3.3VIN
3.3VOUT
NC
NC
CPPE#
CPUSB#
PERST#
GND
SYSRST#
NC
AUXIN
RCLKEN
OC#
SHDN#
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SYSRST#
SHDN#
STBY#
3.3VIN
3.3VIN
3.3VOUT
3.3VOUT
PERST#
NC
GND
OC#
RCLKEN
AUXIN
AUXOUT
1.5VIN
1.5VIN
1.5VOUT
1.5VOUT
CPPE#
CPUSB#
PIN
SYMBOL G YG
YCG
I/O FUNCTION
SYSRST# 1 6 I(*)
System Reset input – active low, logic level signal. Internally pulled
up to AUXIN. This input is driven by the host system and directly
affects PERST#. Asserting SYSRST# (logic low) forces PERST# to
assert. RCLKEN is not affected by the assertion of SYSRST#.
SHDN# 2 20 I(*)
Shutdown input – active low, logic level signal. Internally pulled up
to AUXIN. When asserted (logic low), this input instructs the power
switch to turn off all voltage outputs and the discharge FETs are
activated.
-2-
W83L351 Series
Continued
PIN
SYMBOL G YG
YCG
I/O FUNCTION
STBY# 3 1 I(*)
Standby input – active low, logic level signal. Internally pulled up to
AUXIN. When asserted (logic low) after the card is inserted, this
input places the power switch in standby mode by turning off the
3.3V and 1.5V power switches and keeping the AUX switch on. If
the signal is asserted prior to the card being present, STBY#
places the power switch in OFF Mode by turning off the AUX, 3.3V,
and 1.5V power switches.
PERST# 8 8 O
A logic level power good (with delay). When powered up, this
output remains asserted (logic level low) until all power rails are
within the tolerance. Once all power rails are within the tolerance
and RCLKEN has been released (logic high), PERST# is de-
asserted (logic high) after a time delay, as shown in the parametric
table. When powered down, this output is asserted whenever any
of the power rails drops below their voltage tolerance.
The PERST# signal is an output from the host system and an input
to the ExpressCard module. This signal is only used by PCI
Express-based modules and its function is to place the
ExpressCard module in a reset state.
During power up, power down, or whenever power to the
ExpressCard module is not stable or not within voltage tolerance
limits, the ExpressCard standard requires that PERST# be
asserted. As a result, this signal also serves as a power-good
indicator to the ExpressCard module, and the relationship between
the power rails and PERST# are explicitly defined in the
ExpressCard standard.
The host can also place the ExpressCard module in a reset state
by asserting a system reset SYSRST#. This system reset
generates a PERST# signal to the ExpressCard module without
disrupting the voltage rails. This is normally called a warm reset.
However, in a cold start situation, the system reset can also be
used to prolong the assertion time of PERST#.
CPUSB# 11 9 I(*)
Card Present input for USB cards. Internally pulled up to AUXIN. A
logic low level on this input indicates that the card present supports
the USB functions. When a card is inserted, CPUSB# is physically
connected to ground if the card supports USB functions.
CPPE# 12 10 I(*)
Card Present input for PCI Express cards. Internally pulled up to
AUXIN. A logic low level on this input indicates that the card
present supports the PCI Express functions. When a card is
inserted, CPPE# is physically connected to ground if the card
supports PCI Express functions.
Publication Date: July 5, 2007
-3- Revision 1.10
W83L351 Series
Continued
PIN
SYMBOL
G YG
YCG
I/O FUNCTION
RCLKEN 19 18 I(*)/O
Reference Clock Enable signal. As an output, it is a logic level
power good to the host (no delay – open drain). As an input, if the
signal is kept inactive (low) by the host, PERST# will be prevented
from being de-asserted. Internally pulled up to AUXIN. This pin
serves both as an input and an output. When powered up, a
discharge FET keeps this signal at a low state as long as any of the
output power rails is out of their tolerance range. Once all output
power rails are within the tolerance, the switch releases RCLKEN,
allowing it to transit to a high state (internally pulled up to AUXIN).
The transition of RCLKEN from a low to a high state starts an
internal timer for the purpose of de-asserting PERST#. As an input,
RCLKEN can be kept low to delay the start of the PERST# internal
timer. Because RCLKEN is internally connected to a discharge
FET, this pin can only be driven low and should never be driven
high as a logic input. When an external circuit drives this pin low,
RCLKEN becomes an input; otherwise, this pin is an output.
OC# 20 19 OD
Over current status output (open drain). This pin is an open-drain
output. When any of the three power switches (AUX, 3.3V, and
1.5V) is in an over current condition, OC# is asserted (logic low) by
an internal discharge FET with a deglitch delay. Otherwise, the
discharge FET is open, and the pin can be pulled up to a power
supply through an external resistor.
3.3VIN 4, 5 2 I Primary voltage source, 3.3V input for 3.3VOUT
1.5VIN 15,16 12 I Secondary voltage source, 1.5V input for 1.5VOUT
AUXIN 18 17 I Auxiliary voltage source, AUX input for AUXOUT and chip power.
3.3VOUT 6, 7 3 O Switched output that delivers 0V, 3.3V or high impedance to the
card.
1.5VOUT 13,
14 11 O Switched output that delivers 0V, 1.5V or high impedance to the
card.
AUXOUT 17 15 O
Switched output that delivers 0V, AUX or high impedance to the
card.
GND 10 7 Ground
NC 9
4, 5,
13,
14,
16
No connection
Notice: (*) Be aware that no input pins can be driven HIGH before the Auxiliary voltage is VALID.
-4-
W83L351 Series
3. APPLICATION CIRCUIT
C12
22U
PERST#
1.5VOUT
SY SRST#
AUXOUT
C3
0.1U
C7
0.1U
C1
0.1U
1.5VOUT
3.3VIN
STBY#
3.3VOUT
C8
22U
C9
0.1U
CPUSB#
AUXOUT
C6
4.7U
C5
0.1U
C4
22U
1.5VIN
U1
W83L351G
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SYSRST#
SHDN#
STBY#
3.3VIN
3.3VIN
3.3VOUT
3.3VOUT
PERST#
NC
GND
OC#
RCLKEN
AUXIN
AUXOUT
1.5VIN
1.5VIN
1.5VOUT
1.5VOUT
CPPE#
CPUSB#
AUXIN
SHDN#
AUXIN
CPPE#
C10
4.7U
3.3VIN
C11
0.1U
3.3VOUT
R1
2K
1.5VIN
RCLKEN
AUXIN
C2
4.7U
C1
0.1U
AUXOUT
C12
22U
CPUSB#
1.5VOUT
3.3VIN
AUXOUT
R1
2K
C8
22U
RCLKEN
C2
4.7U
C7
0.1U
U1
W83L351YG/YCG
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
20
19
18
17
16
STBY#
3.3VIN
3.3VOUT
NC
NC
SYSRST#
GND
PERST#
CPUSB#
CPPE#
AUXOUT
NC
NC
1.5VIN
1.5VOUT
SHDN#
OC#
RCLKEN
AUXIN
NC
CPPE#
SHDN#
3.3VOUT
1.5VIN
C10
4.7U
C5
0.1U
AUXIN
C11
0.1U
STBY #
C4
22U
3.3VIN
C9
0.1U
SYSRST#
PERST#
3.3VOUT
1.5VOUT1.5VIN
C3
0.1U
AUXIN
C6
4.7U
Publication Date: July 5, 2007
-5- Revision 1.10
W83L351 Series
4. INTERNAL BLOCK DIAGRAM
Control Logic
Current Limit
Thermal protection
Detctor
SW1
SW2
SW3
SW4
SW5
SW6
POWER_GOOD_ALL
3.3VIN
AUXIN
CPUSB #
CPPE #
STBY #
SHDN #
1.5VI N
GND
AUXOUT
3.3VOUT
1.5VOUT
OC #
RCLKEN
PERST #
SYSRST #
AUXIN
AUXIN
-6-
W83L351 Series
5. ABSOLUTE MAXIMUM RATINGS
ITEM SYMBOL RATING UNIT
VI(3.3VIN) -0.3 to 6 V
VI(1.5VIN) -0.3 to 6 V
Input Voltage
VI(AUXIN) -0.3 to 6 V
Logic Input/Output Voltage -0.3 to 6 V
VO(3.3VOUT) -0.3 to 6 V
VO(1.5VOUT) -0.3 to 6 V
Output Voltage
VO(AUXOUT) -0.3 to 6 V
IO(3.3OUT) Internally limited
IO(1.5OUT) Internally limited
Output Current
IO(AUXOUT) Internally limited
Operating Temperature Range Topt 0 to 70 ℃
Human Body Mode ±2 kV
Machine Mode ±200 V
Electrostatic discharge protection
Latch-Up ±100 mA
Publication Date: July 5, 2007
-7- Revision 1.10
W83L351 Series
6. RECOMMENDED OPERATING CONDITIONS
ITEM MIN MAX UNIT
VI(3.3VIN) 3.3VIN is only required for its respective
functions 3 3.6
VI(1.5VIN) 1.5VIN is only required for its respective
functions 1.35 1.65
Input Voltage
VI(AUXIN) AUXIN is required for all circuit operations 3 3.6
V
IO(3.3VOUT) 0 1.3 A
IO(1.5VOUT) 0 650 mA
Continuous output
current
IO(AUXOUT)
TJ=120℃
0 275 mA
-8-
W83L351 Series
7. ELECTRICAL CHARACTERISTICS
TA = 25℃, VI (3.3VIN) = VI (AUXIN) = 3.3 V, VI (1.5VIN) = 1.5 V, VI (SHDN#), VI (STBY#) = 3.3 V, VI (CPPE#) = VI
(CPUSB#) = 0 V, VI (SYSRST) = 3.3 V, OC# and RCLKEN and PERST# are open, all voltage outputs
unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TA = 25°C, I = 1305 mA
each 90
3.3VIN to 3.3VOUT with
two switches on for dual TA = 70°C, I = 1305 mA
each 105
TA = 25°C, I = 660 mA each 90
1.5VIN to 1.5VOUT with
two switches on for dual TA = 70°C, I = 660 mA each 110
TA = 25°C, I = 285 mA each 110
Power
switch
resistance
AUXIN to AUXOUT with
two switches on for dual TA = 70°C, I = 285 mA each 126
mΩ
IOS(3.3VOUT) (steady-state
value)
1.3
5 1.7 2.5 A
IOS(1.5VOUT) (steady-state
value)
0.6
7 1.1 1.3 A
IOS
Short –
circuit
output
current IOS(AUXOUT) (steady-state
value)
Output powered into a short
275 400 600 mA
Rising temperature, not in
over current condition 155
Trip point, TJ
Over current condition 130
Thermal
Shutdown
Hysteresis 10
℃
II(AUXIN) 140 210
II(3.3VIN)
10.
5 15
Normal
operation
II(1.5VIN)
Outputs are unloaded
(include CPPE# and
CPUSB# logic pull-up
currents) 2.2 10
uA
II(AUXIN) 170 270
II(3.3VIN) 6 10
Shutdown
mode
II(1.5VIN)
CPUSB# = CPPE# = 0 V
SHDN# = 0 V (discharge
FETs are on) (include
CPPE# and CPUSB# logic
pull-up currents and SHDN#
pull-up current)
2.2 10
uA
II(AUXIN) 170 270
II(3.3VIN) 6 10
Standby
mode (1)
II(1.5VIN)
CPUSB# = CPPE# = 0 V
STBY# = 0 V (include
CPPE# and CPUSB# logic
pull-up currents and STBY#
pull-up current) 2.2 10
uA
II(AUXIN) 160 210
II(3.3VIN) 0 0.1
II
Total input
quiescent
current
(Note: 1)
Standby
mode (2)
II(1.5VIN)
CPUSB# = CPPE# = 0 V
3.3VIN = 0 V (include
CPPE# and CPUSB# logic
pull-up currents) 2.2 10
uA
Publication Date: July 5, 2007
-9- Revision 1.10
W83L351 Series
Continued
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
II(AUXIN) 160 210
II(3.3VIN) 6 10
Standby
mode (3)
II(1.5VIN)
CPUSB# = CPPE# = 0 V
1.5VIN = 0 V (include
CPPE# and CPUSB# logic
pull-up currents) 0 0.1
uA
II(AUXIN) 22 50
II(3.3VIN) 0 50
Ilkg(FWD)
Forward
leakage
current II(1.5VIN)
SHDN# = 3.3 V, CPUSB# =
CPPE# = 3.3 V (no card
present, discharge FETs are
on);current measured at
input pins, includes RCLKEN
pull- up current
0 50
uA
LOGIC SECTION (SYSRST, SHDN#, STBY#, PERST#, RCLKEN , OC#, CPUSB#, CPPE#)
SYSRST# = 3.6 V, sinking 0
I(SYSRS#) Input
SYSRST# = 0 V, sourcing 10 17.
5 30 uA
SHDN# = 3.6 V, sinking 0
I(SHDN#) Input
SHDN# = 0 V, sourcing 10 17.
5 30 uA
STBY# = 3.6 V, sinking 0
I(STBY#) Input
STBY# = 0 V, sourcing 10 17.
5 30 uA
I(RCLKEN ) Input RCLKEN = 0 V, sourcing 10 18 30 uA
CPUSB# or CPPE# = 0 V,
sinking 0
Logic input
supply
current
I(CPUSB#) or
I(CPPE#) inputs CPUSB# or CPPE# = 3.6 V,
sourcing 10 17.
5 30
uA
High level 2
Logic input
voltage Low level 0.8 V
RCLKEN output low
voltage Output IO(RCLKEN) = 60 µA 0.4 V
3.3VOUT falling 2.7 3
AUXOUT falling 2.7 3
PERST# assertion threshold of output
voltage (PERST# asserted when any
output voltage falls below the
threshold) 1.5VOUT falling 1.2 1.5
V
PERST# assertion delay from output
voltage
3.3VOUT, AUXOUT,
1.5VOUT falling 500 ns
PERST# de-assertion delay from
output voltage
3.3VOUT, AUXOUT, or
1.5VOUT rising within
tolerance
1 20 ms
-10-
W83L351 Series
Continued
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PERST# assertion delay from
SYSRST#
Max time from SYSRST
asserted 25 500 ns
tW(PERST#) PERST# minimum pulse width
3.3VOUT, AUXOUT, or
1.5VOUT falling out of
tolerance or triggered by
SYSRST#
100 340 us
PERST# output low voltage 0.4 V
PERST# output high voltage
IO(PERST#) = 500 µA
2.4 V
OC# output low voltage IO(OC#) = 2 mA 0.4 V
OC# deglitch Falling into or out of an over
current condition 20 ms
UNDERVOLTAGE LOCKOUT (UVLO)
3.3VIN UVLO
3.3VIN level, below which
3.3VIN and 1.5VIN switches
are off
2.6 2.9
1.5VIN UVLO
1.5VIN level, below which
3.3VIN and 1.5VIN switches
are off
1.0 1.25
AUXIN UVLO AUXIN level, below which all
switches are off 2.6 2.9
V
UVLO hysteresis 100 mV
Note 1: In the Shutdown mode or the Standby mode (1), the AUXIN quiescent current includes a normal operation current,
SHDN# or STBY# internal pull-up current and RCLKEN internal pull-up current. In the Standby modes (2) & (3), the
AUXIN quiescent current includes a normal operation current and a RCLKEN internal-up current.
Publication Date: July 5, 2007
-11- Revision 1.10
W83L351 Series
8. SWITCHING CHARACTERISTICS
TA = 25℃, VI (3.3VIN) = VI (AUXIN) = 3.3 V, VI (1.5VIN) = 1.5 V, VI (SHDN#), VI (STBY#) = 3.3 V, VI (CPPE#) = VI
(CPUSB#) = 0 V, VI (SYSRST) = 3.3 V, OC# and RCLKEN and PERST# are open, all voltage outputs
unloaded (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.3VIN to 3.3VOUT CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A 0.1 6
AUXIN to AUXOUT CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A 0.1 6
1.5VIN to 1.5VOUT CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A 0.1 6
3.3VIN to 3.3VOUT CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A 0.1 6
AUXIN to AUXOUT CL(AUXVOUT)=100uF,
RL=VI(AUXININ)/0.250A 0.1 6
tr
Output rise times
1.5VIN to 1.5VOUT CL(1.5VOUT)=100uF,
RL=VI(1.5VIN)/0.500A 0.1 6
ms
3.3VIN to 3.3VOUT CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A 10 150
AUXIN to AUXOUT CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A 10 150
1.5VIN to 1.5VOUT CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A 10 150
us
3.3VIN to 3.3VOUT CL(3.3VOUT)=20uF, IO(3.3VOUT)=0A 5 30
AUXIN to AUXOUT CL(AUXVOUT)=20uF, IO(AUXOUT)=0A 5 30
tf
Output fall times
when card
removed (both
CPUSB# and
CPPE# de-
asserted) 1.5VIN to 1.5VOUT CL(1.5VOUT)=20uF, IO(1.5VOUT)=0A 5 30
ms
3.3VIN to 3.3VOUT CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A 10 150
AUXIN to AUXOUT CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A 10 150
1.5VIN to 1.5VOUT CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A 10 150
us
3.3VIN to 3.3VOUT CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A 0.1 3
AUXIN to AUXOUT CL(AUXVOUT)=100uF,
RL=VI(AUXININ)/0.250A 0.1 3
tf
Output fall times
when SHDN#
asserted (card is
present)
1.5VIN to 1.5VOUT CL(1.5VOUT)=100uF,
RL=VI(1.5VIN)/0.500A 0.1 3
ms
3.3VIN to 3.3VOUT CL(3.3VOUT)=0.1uF, IO(3.3VOUT)=0A 0.1 6
AUXIN to AUXOUT CL(AUXVOUT)=0.1uF, IO(AUXOUT)=0A 0.1 6
1.5VIN to 1.5VOUT CL(1.5VOUT)=0.1uF, IO(1.5VOUT)=0A 0.1 6
3.3VIN to 3.3VOUT CL(3.3VOUT)=100uF, RL=VI(3.3VIN)/1A 0.1 6
AUXIN to AUXOUT CL(AUXVOUT)=100uF,
RL=VI(AUXININ)/0.250A 0.1 6
Tpd(on)
Turn on
propagation
delay
1.5VIN to 1.5VOUT CL(1.5VOUT)=100uF,
RL=VI(1.5VIN)/0.500A 0.1 6
ms
-12-
W83L351 Series
9. FUNCTIONAL TRUTH TABLES
Truth Table for Voltage Outputs
VOLTAGES INPUTS (1) LOGIC INPUTS VOLTAGE OUTPUTS(2)
AUXIN 3.3VIN 1.5VIN SHDN# STBY# CP# (4) AUXOUT 3.3VOUT 1.5VOUT
MODE(3)
Off X X X X X Off Off Off Off
On Off Off 1 1 X Off Off Off Off
On On On 1 0 0 Off Off Off Off(5)
On On On 1 0 X Off Off Off Off(6)
On X X 0 X X GND GND GND Shutdown
On X X 1 X 1 GND GND GND No Card
On On On 1 0 0 On Off Off Standby
On On →
Off
On →
Off 1 1 0 On Off Off Standby(7)
On On On 1 1 0 On On On Card
Inserted
(1) For input voltages, On means the respective input voltage is higher than its turn on threshold voltage; otherwise, the
voltage is Off (for AUX input, Off means the voltage is close to zero volt).
(2) For output voltages, On means the respective power switch is turned on so the input voltage is connected to the output;
Off means the power switch and its output discharge FET are both off; Gnd means the power switch is off but the output
discharge FET is on so the voltage on the output is pulled down to 0 V.
(3) Mode assigns each set of input conditions and respective output voltage results to a different name. These modes are
referred to as input conditions in the following Truth Table for Logic Outputs.
(4) CP# = CPUSB# and CPPE# equal to 1 when both CPUSB# and CPPE# signals are logic high, or equal to 0 when either
CPUSB# or CPPE# is low.
(5) STBY# is asserted (logic low) prior to the card being present.
(6) STBY# is asserted (logic low) prior to the voltage inputs being present.
(7) The card is inserted prior to the removal of the Primary or Secondary power (either 3.3VIN or 1.5VIN or both) at the input
of the ExpressCard power switch, then only the primary and secondary power (both 3.3VOUT and 1.5VOUT) are
removed and the auxiliary power is sent to the ExpressCard slot.
Publication Date: July 5, 2007
-13- Revision 1.10
W83L351 Series
Truth Table for Logic Outputs
INPUT CONDITIONS LOGIC OUTPUTS
MODE SYSRST# RCLKEN (1) PERST# RCLKEN (2)
Off
Shutdown
No Card
Standby
X X 0 0
0 Hi - Z 0 1
0 0 0 0
1 Hi - Z 1 1
Card Inserted
1 0 0 0
(1) RCLKEN as a logic input in this column. RCLKEN is an I/O pin and it can be driven low externally, left open, or
connected to high-impedance terminals, such as the gate of a MOSFET. It must not be driven high externally.
(2) RCLKEN as a logic output in this column.
-14-
W83L351 Series
10. TYPICAL OPERATING WAVEFORMS
Fig.1 Output Voltage When Card Is Inserted
Fig.2 RCLKEN and PERST# Voltage During Power Up
CH1 CPPE#
CH2 3.3VOUT
CH3 1.5VOUT
CH4 AUXOUT
CH1 3.3VOUT
CH2 RCLKEN
CH3 PERST#
Publication Date: July 5, 2007
-15- Revision 1.10
W83L351 Series
Fig.3 RCLKEN and PERST# Voltage During Power Down
Fig.4 PERST# Asserted by SYSRST# When Power Is On
CH1 AUXOUT
CH2 RCLKEN
CH3 PERST#
CH1 SYSRST#
CH2 PERST#
-16-
W83L351 Series
Fig.5 PERST# De-Asserted by SYSRST# When Power Is On
Fig.6 Output Voltage When 3.3VIN Is Removed
CH1 SYSRST#
CH2 PERST#
CH1 3.3VIN
CH2 3.3VOUT
CH3 1.5VOUT
CH4 AUXOUT
Publication Date: July 5, 2007
-17- Revision 1.10
W83L351 Series
Fig.7 Output Voltage When 1.5VIN Is Removed
Fig.8 OC# Response When AUXOUT Power Into A Short
CH1 1.5VIN
CH2 3.3VOUT
CH3 1.5VOUT
CH4 AUXOUT
CH1 OC#
CH2 AUXOUT
-18-
W83L351 Series
Fig.9 OC# Response When 3.3VOUT Power Into A Short
Fig.10 OC# Response When 1.5VOUT Power Into A Short
CH1 OC#
CH2 1.5VOUT
CH1 OC#
CH2 3.3VOUT
Publication Date: July 5, 2007
-19- Revision 1.10
W83L351 Series
11. EXPRESSCARD TIMING DIAGRAMS
Tpd Min Max Units
a System
dependent
b 100 us
c 10 ms
d 100 us
e 1 20 ms
Fig.12 Host Power Is On Prior To Card Insertion (Note.2)
Fig.11 Card Present Before Host Power (Note.1)
Tpd Min Max Units
a 100 us
b 10 ms
c 1 20 ms
-20-
W83L351 Series
Publication Date: July 5, 2007
-21- Revision 1.10
Fig.13 Host System In Standby Prior to Card Insertion
Tpd Min Max Units
a System
dependent
b Load
dependent
c 500 ns
d 500 ns
Fig.14 Host Controlled Power Down (Note.3)
W83L351 Series
-22-
Tpd Min Max Units
a System
dependent
b System
dependent
c Load
dependent
d 500 ns
e 500 ns
Fig.15 Controlled Power Down When SHDN# Asserted (Note.4)
Tpd Min Max Units
a Load
dependent
b 500 ns
c 500 ns
Fig.16 Surprise Card Removal
W83L351 Series
Note.1: According to the electrical specifications of ExpressCard Standard, the minimum propagation
delay time of e (Power stable to PERST# inactive) is 1ms.
Note.2: RCLKEN could be treated as a power good signal when card power is over 86% of nominal
voltage.
Note.3: The propagation delay time of c is SYSRST# assertion to PERST# assertion. The propagation
delay time of d is card power is under 86% of nominal voltage to RCLKEN de-assertion.
Note 4: RCLEKN de-assertion is prior to PERST# assertion when card power lost in any situation.
Publication Date: July 5, 2007
-23- Revision 1.10
W83L351 Series
12. PACKAGE DIMENSION
W83L351G - TSSOP20
-24-
W83L351 Series
W83L351YG - QFN20, Thermal Pad Dimension: 2.0mm X 2.0mm
Publication Date: July 5, 2007
-25- Revision 1.10
W83L351 Series
W83L351YCG - QFN20, Thermal Pad Dimension: 2.7mm X 2.7mm
-26-
W83L351 Series
¾ Taping Specification
20 Pin TSSOP Package 20 Pin QFN Package
Publication Date: July 5, 2007
-27- Revision 1.10
W83L351 Series
13. ORDERING INFORMATION
PART
NUMBER PACKAGE TYPE SUPPLIED AS PRODUCTION FLOW
W83L351G 20PIN TSSOP (Pb-free
package)
E Shape: 74 units/Tube
T Shape: 2,500
units/T&R
Commercial, 0℃ to +70
℃
W83L351YG 20PIN QFN (Pb-free package)
Thermal Pad Size: 2.0X2.0 ㎜²
E Shape: 490
units/Tray
T Shape: 4,000
units/T&R
Commercial, 0℃ to +70
℃
W83L351YCG 20PIN QFN (Pb-free package)
Thermal Pad Size: 2.7X2.7 ㎜²
E Shape: 490
units/Tray
T Shape: 4,000
units/T&R
Commercial, 0℃ to +70
℃
-28-
W83L351 Series
14. TOP MARKING SPECIFICATION
W83L351G
212345678
606XARA
Winbond
351YG
636XARB
Winbond
351YCG
636XARB
1st line: Winbond – company name
2nd line: 351YG/351YCG – the part number
3rd line: Tracking code 636 X ARB
636: Packages assembled in Year 06’, week 36
X: Assembly house ID
ARB: The IC version
Left line: Winbond logo
1st line: W83L351G – the part number
2nd line: Chip lot no
3rd line: Tracking code 606 X ARA
606: Packages assembled in Year 06’, week 06
X: Assembly house ID
ARA: The IC version
Publication Date: July 5, 2007
-29- Revision 1.10
W83L351 Series
-30-
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics (H.K.) Ltd.
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
FAX: 852-27552064
Unit 9-15, 22F, Millennium City,
TEL: 852-27513100
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
Winbond Electronics (Shanghai) Ltd.
200336 China
FAX: 86-21-62365998
27F, 2299 Yan An W. Rd. Shanghai,
TEL: 86-21-62365999
Winbond Electronics Corporation Japan
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
FAX: 81-45-4781800
7F Daini-ueno BLDG, 3-7-18
TEL: 81-45-4781881
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
