9 \-362- T9AI- SAB Sh Eb microelectronics group Lucent Technologies Bell Labs Innovations ATT3000 Series Field-Programmable Gate Arrays Features s High performance: Up to 270 MHz toggle rates 4-input LUT delays < 3ns s User-programmable gate arrays a Flexible array architecture: Compatible arrays, 2000 to 9000 gate logic complexity Extensive register and \/O capabilities Low-skew clock nets High fan-out signal distribution Internal 3-state bus capabilities TTL or CMOS input thresholds On-chip oscillator amplifier Standard product availability: Low-power 0.6 um CMOS, static memory technology Pin-for-pin compatible with Xilinx XC3000 and XC3100 families Cost-effective, high-speed FPGAs 100% factory pretested Selectable configuration modes a ORCA Foundry for ATT3000 Development System support a All FPGAs processed on a QML-certified line Extensive packaging options Description The CMOS ATT3000 Series Field-Programmable Gate Array (FPGA) family provides a group of high- density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O blocks, a core array of logic blocks, and resources for interconnection. The general struc- ture of an FPGA is shown in Figure 1. The ORCA Foundry for ATT3000 development sys- tem provides automatic place and route of netlists. Logic and timing simulation are available as design verification alternatives. The design editor is used for interactive design optimization and to compile the data pattern which represents the configuration pro- gram. The FPGAs user-logic functions and interconnec- tions are determined by the configuration program data stored in internal static memory cells. The pro- gram can be loaded in any of several modes to accommodate various system requirements. The program data resides externally in an EEPROM, EPROM, or ROM on the application circuit board, or on a floppy disk or hard disk. On-chip initialization logic provides for optional automatic loading of pro- gram data at powerup. A serial configuration PROM can provide a very simple serial configuration pro- gram storage. Table 1. ATT3000 Series FPGAs Logic . ;, | Configurable Program epaa | Capacity) Logic | USE") Data (Available V/Os : Blocks (Bits) Gates) ATT3020 2000 64 64 14779 ATT3030 3000 100 80 22176 ATT3042 4200 144 96 | 30784 ATT3064 6400 224 120} 46064 ATT3090 9000 320 144; 64160 The ATT3000 series FPGAs are an enhanced family of field-programmable gate arrays, which provide a variety of logic capacities, package styles, tempera- ture ranges, and speed grades. 9.9909a4 ATT3000 Series FPGAs FPGA Data Book Table of Contents Contents Page Contents Page FOAtUIOS ...ccesceccceccecesseeccnereenessesvacseceseesssaeeneesens 2-293 Special Configuration Functions ........... ee 2-319 De@SCTIDTION .......esecseseeeeeeseceeeeeseneneneaeneeeeensenaneees 2-293 Input TRrESHONS oo. ee cece ects cteeeesenseeeeeees 2-319 ArchiteCture ........ccccccseseccesecsecescneeseeesesstsesneeeees 2-295 REAMDACK oo... eececceseecesceseeneceeeeecerceeeeneteneeeeenenees 2-319 Configuration MeMory .....---- essere 2-296 REPFOGTAM oo..ceeceeecetseeesceteseeesenseneeneeseseneees 2-319 VO BIOCK ...cececcscessesseeeseeersecesecsessseenneeeseeseenae 2-297 DONE PUull-Up oo... eee eeeeeeseeeereeereeressseeersenenens 2-320 Summary of I/O Options ....... cece 2-298 DONE Timing 20.0... eceeecesseseseseeeteneneeseseeneeees 2-320 Configurable Logic BIOCK 0... ceteris 2-299 RESET Timing ......eccceecseseeseeseseeseeeresssussaneveuas 2-320 Programmable INtETCONNECLH ........cccccccccccceceseeeees 2-301 Crystal Oscillator DIVISION oo... ee eeseseseeee ree 2-320 General-Purpose Interconnect 0.0... 2-302 P@rfOrManCe ooo... eeceeceseseeeneeeseesseeteeesesseeeeeeeeseeenea 2-321 Direct InterCONMect 0.0... cece seeteseteeerereenes 2-303 Device Performance ou... cesses eeenseseeeeeerees 2-321 LONG LIM@S .....seeseesseesecstessteesseesesseenecneesnesseanens 2-305 Logic Block Performance .........cccceecesseeseees 2-322 Internal BUSES ........ccccsesessesescneteceenceeceeseenestaees 2-306 Interconnect Performance ........ccceeecseeeeeeees 2-322 Crystal OSCIIAtOr oo. tecssceseseeseseenesseseeeeseens 2-308 POWES oo. eecccececeeeeeeeeneesseeneesneeeeecesseaseaeesneeeereaenens 2-324 PLOGrAMIMING .......ssseseserceeesteeeteneeesseeeeteeeeeee nents 2-309 Power Distribution ..........:esceceeeeeeseeeeeeteeeeeeees 2-324 Initialization PHASE .......c.sceseseeceessceeseeneeseenees 2-309 Power Dissipation .........::eseeeenseeeeeeeeeeeey 2-325 Configuration Data 00.0... cscs: 2-311 Pin INfOrMALION oo. eects eeeeseceeseeesesateenesesseneres 2-327 Master Mode ou... cee cee ecssccssecceesseessssseeeeeenaes 2-314 Pin ASSIQNMEMS 00... eee eeeeeeeeereteeensessessesereeens 2-332 Peripheral MOE oo... sessssssseeeeeseeseeseeeseeenens 2-316 Package Thermal Characteristics.................000 2-343 Slave MOde .......cceccesceeceesscessceseeeseeecseesenereneees 2-317 Package Coplanarity 0.0... eceeesesseneteesseneeeees 2-344 Daisy Chain oe. eesscesesseteseeecsesesesenensnens 2-318 Package Parasitics 0.0... eceeceseseceeesseeneeeesenees 2-344 Absolute Maximum RatingS 0.0.00... 2-346 Electrical CharacteristicS 00.0... eeeceeeeeeee eee 2-347 Ordering INfOrmation ......eceesssseseeeseeeeeseeesenes 2-361 op tn Ine.FPGA Data Book ATT3000 Series FPGAs Architecture The perimeter of configurable I/O blocks (IOBs) pro- yides a programmable interface between the internal logic array and the device package pins. The array of configurable logic blocks (CLBs) performs user- specified logic functions. The interconnect resources are programmed to form networks, carrying logic signals among blocks, analogous to printed-circuit board traces connecting MSI/SSI packages. The blocks logic functions are implemented by programmed look-up tables. Functional options are implemented by program-controlied multiplexers. interconnecting networks between blocks are Cr Cal a VO BLOCKS 4 4. Ie THREE-STATE SUFFERS WITH ACCESS TO HORIZONTAL LONG LINES foo) o 0 4+#_- INTERCONNECT AREA U implemented with metal segments joined by program- controlled pass transistors. These functions of the FPGA are established by a configuration program which is loaded into an internal, distributed array of configuration memory cells. The configuration program is loaded into the FPGA at powerup and may be reloaded on command. The FPGA includes logic and control signals to implement automatic or passive configuration. Pragram data may be either bit serial or byte parallel. The ORCA Foundry for ATT3000 Devel- opment System generates the configuration program bit stream used to configure the FPGA. The memory loading process is independent of the user logic func- tions. CONFIGURABLE LOGIC BLOCKS eee fo . Avon Ere pe fe Figure 1. Field-Programmable Gate Array Structure Lucent Technologies Inc. 2-295ATT3000 Series FPGAs 4 FPGA Data Book Configuration Memory The static memory cell used for the configuration mem- ory in the FPGA has been designed specifically for high reliability and noise immunity. Integrity of the FPGA configuration memory based on this design is ensured even under various adverse conditions. Com- pared with other programming alternatives, static mem- ory is believed to provide the best combination of high density, high performance, high reliability, and compre- hensive testability. As shown in Figure 2, the basic memory cell consists of two CMOS inverters plus a pass transistor used for writing and reading cell data. The cell is only written to during configuration and only read from during read- back. During normal operation, the cell provides contin- uous contro! and the pass transistor is off and does not affect cell stability. This is quite different from the opera- tion of conventional memory devices, in which the cells are frequently read and rewritten. The memory cell outputs Q and Q use full Ground and Vcc levels and provide continuous, direct control. The additional capacitive load and the absence of address decoding and sense amplifiers provide high stability to the cell. Due to their structure, the configuration mem- ory cells are not affected by extreme power supply excursions or very high levels of alpha particle radia- tion. Soft errors have not been observed in reliability testing. Two methods of loading configuration data use serial data, while three use byte-wide data. The internal con- figuration logic utilizes framing information, embedded in the program data by the ORCA Foundry Develop- ment System, to direct memory cell loading. The serial data framing and length count preamble provide pro- gramming compatibility for mixes of various Lucent pro- grammable gate arrays in a synchronous, serial, daisy- chain fashion. READ OR WRITE Td } FLY DATA Q CONFIGURATION _ CONTROL Se 5-3101(F} Figure 2. Static Configuration Memory Cell 9.2905 | ucent Technologies Inc- 4 pGA Data Book ATT3000 Series FPGAs (0 Block Each user-configurable I/O block (OB), shown in Figure 3, provides an interface between the external package pin of the device and the internal user logic. Each 1OB includes both registered and direct input paths and a programmable 3-state output buffer which may be driven by a registered or direct output signal. Configuration options allow each |OB an inversion, a controlled slew rate, and a high-impedance pull-up. Each input circuit also provides input clamping diodes to provide electrostatic protection and circuits to inhibit latch-up produced by input currents. The input buffer portion of each IOB provides threshold detection to translate external signals applied to the package pin to internal logic levels. The global input- buffer threshold of the IOB can be programmed to be compatible with either TTL or CMOS levels. The buff- ered input signal drives the data input of a storage element which may be configured as a positive edge- triggered D flip-flop or a low-level transparent latch. The sense of the clock can be inverted (negative edge/high transparent) as long as all |OBs on the same clock net use the same clock sense. Clock/load signals (IOB pins ik and .ok) can be selected from either of two die edge metal lines. /O storage elements are reset during con- figuration or by the active-low chip RESET input. Both direct input (from I/O block pin .i) and registered input (from IOB pin .q) signals are available for interconnect. PROGRAM-CONTROLLED MEMORY CELLS a Vec oo s OUT 3-STATE ouTpuT| | sLew | |PASSIVE INVERT INVERT SELECT! | RATE | [PULL-UP 3-STATE itt LL OUTPUT ENABLE 4 e 0 ne y output OUT BUFFER FLIP- FLOP Pp @{/0 PAD j [ DIRECT IN ~ REGISTERED IN +4 QOD <q FLIP- TTILOR FLOP CMOS OR INPUT LATCH THRESHOLD a R ol) jk + (GLOBAL RESET) { (+ CK1 = PROGRAM - CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT OR PIP -3102(F) Figure 3. Input/Output Block lucent Technologies Inc. 2-297ATT3000 Series FPGAs FPGA Data Book I/O Block (continued) For reliable operation, inputs should have transition times of less than 100 ns and should not be left float- ing. Floating CMOS input-pin circuits might be at threshold and produce oscillations. This can produce additional power dissipation and system noise. A typical hysteresis of about 200 mV reduces sensitivity to input noise. Each user IOB includes a programmable high-impedance pull-up resistor which is selected by the program to provide a constant high for otherwise undriven package pins. Normal CMOS handling precautions should be observed. Flip-flop loop delays for the {OB and logic block flip- flops are approximately 3 ns. This short delay provides good performance under asynchronous clock and data conditions. Short loop delays minimize the probability of a metastable condition which can result from asser- tion of the clock during data transitions. Because of the short loop delay characteristic in the FPGA, the |OB flip-flops can be used to synchronize external signals applied to the device. When synchronized in the IOB, the signals can be used internally without further con- sideration of their clock relative timing, except as it applies to the internal logic and routing path delays. Output buffers of the IOBs provide CMOS-compatible 4 mA source-or-sink drive for high fan-out CMOS or TTL compatible signal levels. The network driving |OB pin .o becomes the registered or direct data source for the output buffer. The 3-state control signal (IOB pin t) can contro! output activity. An open-drain type output may be obtained by using the same signal for driving the output and 3-state signal nets so that the buffer out- put is enabled only for a LOW. Configuration program bits for each IOB control features such as optional output register, logical signal inversion, and 3-state and slew rate control of the out- put. The program-controlled memory cells in Figure 3 control the following options: au Logical inversion of the output is controlled by one configuration program bit per IOB. u Logical 3-state control of each 1OB output buffer is determined by the states of configuration program bits which turn the buffer on or off or select the output buffer 3-state control interconnection (IOB pin .t). When this 1OB output control signal is high, a logic 1, the buffer is disabled and the package pin is high impedance. When this [OB output control signal is low, a logic 0, the buffer is enabled and the package pin is active. Inversion of the buffer 3-state control logic sense (output enable) is controlled by an addi- tional configuration program bit. Direct or registered output is selectable for each JOB. The register uses a positive-edge, clocked flip-flop. The clock source may be supplied (IOB pin .ok) by either of two metal lines available along each die edge. Each of these lines is driven by an invertible buffer. Increased output transition speed can be selected to improve critical timing. Slower transitions reduce capacitive load peak currents of noncritical outputs and minimize system noise. a A high-impedance pull-up resistor may be used to prevent unused inputs from floating. Summary of I/O Options a Inputs Direct Flip-flop/latch CMOS/TTL threshold (chip inputs) Pull-up resistor/open circuit w Outputs Direct/registered Inverted/not 3-state/on/off Full speed/slew limited 3-state/output enable (inverse) po ttenknalnnies Inc._ FPGA Data Book a4 ATT3000 Series FPGAs Configurable Logic Block The array of configurable logic blocks (CLBs) provides the functional elements from which the user's logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. The ATT3020 has 64 such blocks arranged in eight rows and eight columns. The ORCA Foundry Development System is used ta com- pile the configuration data for loading into the internal configuration memory to define the operation and inter- connection of each block. User definition of CLBs and their interconnecting networks may be done by auto- matic translation from a schematic capture logic dia- gram or optionally by installing library or user macros. Each CLB has a combinatorial logic section, two flip- flops, and an internal control section; see Figure 4 below. There are five logic inputs (.a, .b, .c, .d, and .e); a common clock input (.k); an asynchronous direct reset input (.rd); and an enable clock (.ec). All may be driven from the interconnect resources adjacent to the blocks. Each CLB also has two outputs (.x and .y) which may drive interconnect networks. Data input for either flip- flop within a CLB is supplied from the function F or G outputs of the combinatorial logic, or the block input, data-in (.di). Both flip-flops in each CLB share the DATA IN ax F LOGIC COMBINATORIAL VARIABLES FUNCTION G ENABLE CLOCK 1 (ENABLE) CLOCK RESET O (INHISIT) (GLOBAL RESET) asynchronous reset (.rd) which, when enabled and high, is dominant over clocked inputs. All flip-flops are reset by the active-low chip input, RESET, or during the configuration process. The flip-flops share the enable clock (.ec) which, when low, recirculates the flip-flops present states and inhib- its response to the data-in or combinatorial function inputs on a GLB. The user may enable these control inputs and select their sources. The user may also select the clock net input (.k), as well as its active sense within each logic block. This programmable inversion eliminates the need to route both phases of a clock signa! throughout the device. Flexible routing allows use of common or individual CLB clocking. The combinatorial logic portion of the logic block uses a 32 x 1 look-up table to implement Boolean functions. Variables selected from the five logic inputs and the two internal block flip-flops are used as table address inputs. The combinatorial propagation delay through the network is independent of the logic function gener- ated and is spike-free for single-input variable changes. This technique can generate two independent logic functions of up to four variables each as shown in Fig- ure 5A, or a single function of five variables as shown in Figure 5B, or some functions of seven variables as shown in Figure 5C. CLB OUTPUTS -3103(F} Figure 4. Configurable Logic Block yn 9700s 4 ATT3000 Series FPGAs FPGA Data Book Configurable Logic Block (continued) 5A. 5B. 5C. ANY FUNCTION OF UP TO 4 VARIABLES ANY FUNCTION OF UP TO4 VARIABLES ANY FUNCTION OF 5 VARIABLES A B ax ANY FUNCTION ayy | OF UP TO4 VARIABLES c UY D F M U A XILe B = ax ANY FUNCTION ay OF UP TO4 C VARIABLES D E 5C 5-3104(F) Combinatorial Logic Option 1 generates two functions of four variables each. One variable, A, must be common to both func- tions. The second and third variables can be any choice among B, C, Qx, and Qy. The fourth variable can be either D or E. Combinatorial Logic Option 2 generates any function of five variables: A, D, E, and two choices among B, C, Qx, Qy. Combinatorial Logic Option 3 allows variable E to select between two functions of four variables: both have common inputs, A and D, and any choice among B, C, Qx, and Qy for the remaining two variables. Option 3 can then implement some functions of six or seven variables. Figure 5. Combinatorial Logic Diagram Figure 6 shows a modulo 8 binary counter with parallel enable. It uses one CLB of each type. The partial func- tions of six or seven variables are implemented by using the input variable (.e) to dynamically select between two functions of four different variables. For the two functions of four variables each, the indepen- dent results (F and G) may be used as data inputs to either flip-flop or logic block output. For the single func- tion of five variables and merged functions of six or seven variables, the F and G outputs are identical. Symmetry of the F and G functions and the flip-flops allows the interchange of CLB outputs to optimize routing efficiencies of the networks interconnecting the logic and IOBs. CLOCK ENABLE PARALLEL ENABLE CLOCK TERMINAL COUNT DUAL FUNCTION OF 4 VARIABLES DO Q1 D1 FUNCTION OF 5 VARIABLES Q2 D2 FUNCTION OF 6 VARIABLES 5-3105(F) Figure 6. C8BCP Macro boo ee a tenhnnrlodes Inc.FPGA Data Book ATT3000 Series FPGAs programmable Interconnect programmable interconnection resources in the FPGA provide routing paths to connect inputs and outputs of the 1OBs and logic blocks into logical networks. Inter- connections between blocks are composed from a two- layer grid of metal segments. Specially designed pass transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the necessary connections between selected metal segments and block pins. Figure 7 is an example of a routed net. The ORCA Foundry Development System provides automatic rout- ing of these interconnections. Interactive routing is also available for design optimization. The inputs of the logic or |OBs are multiplexers which can be programmed to select an input network from the adjacent interconnect segments. Since the switch connections to block inputs are unidirectional (as are block outputs), they are usable only for block input connection and not routing. Figure 8 illustrates routing access to logic block input variables, control inputs, and block outputs. Three types of metal resources are provided to accom- modate various network interconnect requirements: a General-purpose interconnect a Direct connection = Long lines (multiplexed buses and wide-AND gates) SWITCHING MATRIX INTERCONNECT RSE rem CONFIGURABLE INTERCONNECT LOGIC BLOCK SUFFER Figure 7. Example of Routing Resources i * Le al CLB CONTROL INPUTS CLB X OUTPUT OS Ooe'oek Qe io le de abn i | Tote oo + CLB LOGIC INPUTS CLB Y OUTPUT ta oF ay oY ie FF nt A Figure 8. CLB Input and Output Routing 2-301ATT3000 Series FPGAs ye FPGA Data Book Programmable Interconnect (continued) General-Purpose Interconnect General-purpose interconnect, as shown in Figure 9, consists of a grid of five horizontal and five vertical metal segments located between the rows and col- umns of logic and |OBs. Each segment is the height or width of a logic block. Switching matrices join the ends of these segments and allow programmed interconnec- tions between the metal grid segments of adjoining rows and columns. The switches of an unprogrammed device are all nonconducting. The connections through the switch matrix may be established by automatic or interactive routing by selecting the desired pairs of matrix pins to be connected or disconnected. The legitimate switching matrix combinations for each pin are indicated in Figure 10. Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved performance of lengthy nets. The intercon- nect butfers are available to propagate signals in either direction on a given general interconnect segment. These bidirectional (bidi) buffers are found adjacent to the switching matrices, above and to the right. The other PIPs adjacent to the matrices are accessed to or from long lines. The development system automatically defines the buffer direction based on the location of the interconnection network source. The delay calculator in the ORCA Foundry Development System automatically calculates and displays the block, interconnect, and buffer delays for any paths selected. Generation of the simulation netlist with a worst-case delay model is also provided by the development system. Some of the interconnect PIPs are directional, as indicated below: a ND is a nondirectional interconnection. = D:H->V is a PIP which drives from a horizontal to a vertical line. D:V->H is a PIP which drives from a vertical to a horizontal line. = D:C->T is a T PIP which drives from a cross of a T to the tail. a D:CW is a corner PIP which drives in the clockwise direction. PO indicates the PIP is nonconducting; P1 is on. SWITCHING MATRIX i merle Pt GRID OF GENERAL INTERCONNECT METAL SEGMENTS Figure 9. FPGA General-Purpose Interconnect Figure 10. Switch Matrix Interconnection Options 1 opimant Tarhnnaliodes Inc.a4 EPGA Data Book ATT3000 Series FPGAs Programmable Interconnect (continued) Direct Interconnect Direct interconnect (shown in Figure 11) provides the most efficient implementation of networks between adjacent logic or lOBs. Signals routed from block to block using the direct interconnect exhibit minimum interconnect propagation and use no general intercon- nect resources. For each CLB, the .x output may be connected directly to the .b input of the CLB immedi- ately to its right and to the .c input of the CLB to its left. The .y output can use direct interconnect to drive the .d input of the block immediately above, and the .a input of the block below. Direct interconnect should be used to maximize the speed of high-performance portions of logic. Where logic blocks are adjacent to |OBs, direct connect is provided alternately to the [OB inputs (.i) and outputs (.0) on all four edges of the die. The right edge provides additional direct connects from CLB out- puts to adjacent !OBs. Direct interconnections of 1OBs with CLBs are shown in Figure 12. L La L i i 7 Figure 11. Direct Interconnect a ode Tr rr . a phalnainde oa 2-303- ATT3000 Series FPGAs ~ FPGA Data Book Programmable Interconnect (continued) GLOBAL BUFFER DIRECT INPUT GLOBAL BUFFER INTERCONNECT ALTERNATE BUFFER DIRECT INPUT UNBONDED IOBs (6 PLACES) Figure 12. ATT3020 Die Edge I/O Blocks with Direct Access to Adjacent CLBEPGA Data Book ATT3000 Series FPGAs Programmable Interconnect (continued) Long Lines The long lines bypass the switch matrices and are intended primarily for signals which must travel a long distance, or must have minimum skew among multiple destinations. Long lines, shown in Figure 13, run vertically and horizontally the height or width of the interconnect area. Each interconnection column has three vertical long lines, and each interconnection row has two horizontal long lines. Additionally, two long lines are located adjacent to the outer sets of switching matrices. Two vertical long lines in each column are connectable half-length lines, except on the ATT3020, where only the outer long lines serve that function. Long lines can be driven by a logic block or IOB output on a column-by-column basis. This capability provides a common low-skew control or clock line within each column of logic blocks. Interconnections of these long lines are shown in Figure 14. Isolation buffers are pro- vided at each input to a long line and are enabled auto- matically by the development system when a connection is made. GLOBAL \, wi . : = . T ro . 7 Aernt dn re. a se a P tt coo gs Jo Lote oS ON-CHIP mo: . . - PY... Tv sa B-STATE Fotelei r . F. oT. J, BUFFERS FE <: 0. ABR: JAC} ce: #4 : PULL-UP bp cp Ow Ah 1, he io RESISTORS 72 L hs to: r: FOR ON-CHIP po eT OJ bt tetas * 2 qC+ 3 OPEN-DRAIN E ooo a ey tot? : com. : 4S F 3 SIGNALS E-. NF. ~ ~ fp "2 HORIZONTAL LONG LINES TUE . BAR oy ~ (BER br: . BCR ois: #4 : Pt: feo. Pa le ote Up ore Figure 13. Horizontal and Vertical Long Lines in the FPGA Lucent Technologies Inc. 9-305ATT3000 Series FPGAs FPGA Data Book Programmable Interconnect (continued) A buffer in the upper left corner of the FPGA chip drives a global net which is available to all .k inputs of logic blocks. Using the global buffer for a clock signal pro- vides a skew-free, high fan-out, synchronized clock for use at any or all of the I/O and logic blocks. Configura- tion bits for the .k input to each logic block can select this global line, or another routing resource, as the clock source for its flip-flops. This net may also be pro- grammed to drive the die edge clock lines for OB use. An enhanced speed, CMOS threshold, offers direct access to this buffer and is available at the second pad from the top of the left die edge. A buffer in the lower right corner of the array drives a horizontal long line that can drive programmed connec- tions to a vertical long line in each interconnection column. This alternate buffer also has low skew and high fan-out. The network formed by this alternate buf- fers long lines can be selected to drive the .k inputs of the logic blocks. CMOS threshold, high-speed access to this buffer is available from the third pad from the bottom of the right die edge. * FOUR OUTER LONG LINES ARE CONNECTIBLE HALF-LENGTH LINES internal Buses A pair of 3-state buffers is located adjacent to each CLB. These buffers allow logic to drive the horizontal long lines. Logical operation of the 3-state buffer controls allows them to implement wide multiplexing functions. Any 3-state buffer input can be selected as drive for the horizontal long line bus by applying a low logic level on its 3-state control line (see Figure 15A). The user is required to avoid contention that can result from multiple drivers with opposing logic levels. Control of the 3-state input by the same signal that drives the buffer input creates an open-drain wired-AND function. A logical high on both buffer inputs creates a high impedance which represents no contention. A logical low enables the buffer to drive the long line low (see Figure 15B). Pull-up resistors are available at each end of the long line to provide a high output when all con- . nected buffers are nonconducting. This forms fast, wide gating functions. When data drives the inputs and sep- arate signals drive the 3-state control lines, these buff- ers form multiplexers (3-state buses). In this case, care must be used to prevent contention through multiple active buffers of conflicting levels on a common line. Figure 16 shows 3-state buffers, long lines, and pull-up resistors. VO BLOCK CLOCK NETS (2 PER DIE EDGE) - . ow. -. ow, ow, ~, * . on # ih te Aa f a & teh * HORIZONTAL a vf Tee opt Tyee a pee Wt LONG LINES - welt ode te. les oAhe te: ole tes : wes 3-STATE BUFFERS Figure 14. Programmable Interconnection of Long Lines 2-306 Lucent Technologies Inc-a4 FPGA Data Book ATT3000 Series FPGAs Programmable Interconnect (continued) 3 Z=Da*Da*Oce...* On 3 Da De Dc DN 5-3106(F) Figure 15A. 3-State Buffers Implement a Wired-AND Function Z=DaeA+DeB+DoeC+...+DNeN A B Cc N Figure 15B. 3-State Buffers Implement a Multiplexer 5-3107(F) BIDIRECTIONAL 3 VERTICAL LONG LINES INTERCONNECT GLOBAL a PER COLUMN BUFFERS GG GH HORIZONTAL LONG LINE PULL-UP RESISTOR HORIZONTAL LONG LINE OSCILLATOR AMPLIFIER OUTPUT DIRECT INPUT OF P47 TO AUXILIARY BUFFER CRYSTAL OSCILLATOR BUFFER 3-STATE INPUT 3-STATE CONTROL 3-STATE BUFFEA ALTERNATE BUFFER OSCILLATOR AMPLIFIER INPUT 5-3108(F) Figure 16. Lower-Right Corner of ATT3020 Lucent Technologies Inc. 2-307po ATT3000 Series FPGAs FPGA Data Book Programmable Interconnect (continued) Crystal Oscillator Figure 16 shows the location of an internal high-speed inverting amplifier which may be used to implement an on-chip crystal oscillator. It is associated with the auxil- iary buffer in the lower right corner of the die. When the oscillator is configured by MAKEBITS and connected as a Signal source, two special user IOBs are also con- figured to connect the oscillator amplifier with external crystal oscillator components as shown in Figure 17. A divide-by-two option is available to ensure symmetry. The oscillator circuit becomes active before configura- tion is complete in order to allow the oscillator to stabi- lize. Actual internal connection is delayed until completion of configuration. In Figure 17, the feedback resistor, R1, between output and input biases the amplifier at threshold. The value should be as large as is practical to minimize loading of the crystal. The inver- sion of the amplifier, together with the R-C networks and an AT cut series resonant crystal, produces the 360 phase shift of the Pierce oscillator. A series resis- tor, R2, may be included to add to the amplifier output impedance when needed for phase shift control or crystal resistance matching, or to limit the amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the ratio of C2/C1. The amplifier is designed to be used from 1 MHz to one-half the specified CLB toggle frequency. Use at frequencies below 1 MHz may require individual characterization with respect to a series resistance. Crystal oscillators above 20 MHz generally require a crystal which operates in a third overtone mode, where the fundamental frequency must be suppressed by the R-C networks. When the oscillator inverter is not used, these IOBs and their package pins are available for general user I/O. INTERNAL EXTERNAL [1 [eo L_| XTAL1 (OUT) ALTERNATE XTAL2 CLOCK BUFFER (IN) C4 Ri WAP R2 Tr C1 Y1 ---- C2 L ae 3RD OVERTONE ONLY 5-3109(F) Suggested component values: Ri~1 nO to 4a R2O kQ to 1 kQ (may be required for low frequency, phase shift, and/or compensation level for Crystal Q) C1, C210 pF to 40 pF Y11 MHz to 20 MHz AT cut series resonant Pin 44-Pin | 68-Pin | 84-Pin 100-Pin 132-Pin | 144-Pin | 160-Pin | 175-Pin | 208-Pin PLCC | PLCC | pice MQFP | Tarp | PPGA | TQFP | MQFP | PPGA | SQFP XTAL1 (OUT) 30 47 57 82 79 P13 75 82 114 110 [XTAL2 (IN) 26 43 53 76 73 M13 69 76 P15 100 Figure 17. Crystal Oscillator Inverter 2-308 bocce met Teen ntraainge Int.FPGA Data Book ATT3000 Series FPGAs Programming initialization Phase An internal power-on-reset circuit is triggered when power is applied. When Vcc reaches the voltage where portions of the FPGA begin to operate (2.5 V to3 V), the programmable I/O output buffers are disabled and a high-impedance pull-up resistor is provided for the user /O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time, the power- down mode is inhibited. The initialization state time-out (about 11 ms to 33 ms) is determined by a 14-bit counter driven by a self-generated, internal timer. This nominal 1 MHz timer is subject to variations with pro- cess, temperature, and power supply over the range of 0.5 MHz to 1.5 MHz. As shown in Table 2, five configu- ration mode choices are available, as determined by the input levels of three mode pins: MO, M1, and M2. Table 2. Configuration Modes MO; M1|}M2| Clock Mode Data 0; 0); 0 Active Master Bit Serial 0] 0; 1 Active Master Byte Wide (Address = 0000 up) Oo; 1490 _ Reserved Oo} 1 Active Master Byte Wide (Address = FFFF down) 1 0/0 Reserved _ 1 | 0] 1 | Passive | Peripheral Byte Wide 1} 170 _ Reserved _ 1) 1/1 Passive Slave Bit Serial Lucent Technologies Inc. In master-configuration modes, the FPGA becomes the source of configuration clock (CCLK). Beginning con- figuration of devices using peripheral or slave modes must be delayed long enough for their initialization to be completed. An FPGA with mode lines selecting a master configuration mode extends its initialization State using four times the delay (43 ms to 130 ms) to ensure that ail daisy-chained slave devices it may be driving will be ready, even if the master is very fast and the slave(s) very slow (see Figure 18). At the end of initialization, the FPGA enters the clear state where it clears configuration memory. The active-low, open- drain initialization signal INIT indicates when the initial- ization and clear states are complete. The FPGA tests for the absence of an external active-low RESET before it makes a final sample of the mode lines and enters the configuration state. An external wired-AND of one or more INIT pins can be used to control configuration by the assertion of the active-low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized. If a configuration has begun, a reassertion of RESET for a minimum of three internal timer cycles will be recog- nized and the FPGA will initiate an abort, returning to the clear state to clear the partially loaded configura- tion memory words. The FPGA will then resample RESET and the mode lines before re-entering the con- figuration state. A reprogram is initiated when a config- ured FPGA senses a high-to-low transition on the DONE/PROG package pin. The FPGA returns to the clear state where configuration memory is cleared and _ mode lines resampled, as for an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle. 2-309ATT3000 Series FPGAs FPGA Data Book Programming (continued) USER 1/0 PINS WITH HIGH-IMPEDANCE PULL-UP UM ( INIT SIGNAL LOW (ATT3000) HDC = HIGH POWERDOWN AL [DC = LOW NO HDC, LDC f ~ = OR PULL-UP INITIALIZATION INACTIVE POWER-ON TIME DELAY ACTIVE ACTIVE RESET POWERDOWN y NO CLEAR CONFIGURATION OPERATIONAL CONFIGURATION PROGRAM MODE MODE YES ACTIVE RESET OPERATES ON USER LOGIC LOW ON DONE/PROGRAM AND RESET 5-3110(F} Figure 18, State Diagram of Configuration Process for Powerup and Reprogram Length count control allows a system of multiple FPGAs in assorted sizes to begin operation in a syn- chronized fashion. The configuration program gener- ated by the MakePROM program of the ORCA Foundry Development System begins with a preamble of 111111110010 (binary) followed by a 24-bit length count representing the total number of configuration clocks needed to complete loading of the configuration program(s). The data framing is shown in Figure 19. All FPGAs connected in series read and shift preamble and length count in (on positive) and out (on negative) CCLK edges. An FPGA which has received the pream- ble and length count then presents a HIGH data out until it has intercepted the appropriate number of data frames. When the configuration program memory of an FPGA is full and the length count does not compare, the FPGA shifts any additional data through, as it did for preamble and length count. When the FPGA configuration memory is full and the length count compares, the FPGA will execute a syn- chronous start-up sequence and become operational (see Figure 20 on page 312). Three CCLK cycles after the completion of loading configuration data, the user /O pins are enabled as configured. As selected in MAKEBITS, the internal user-logic reset is released either one clock cycle before or after the I/O pins AYA become active. A similar timing selection is program- mable for the DONE/PROG output signal. DONE/PROG may also be programmed to be an open drain or include a pull-up resistor to accommodate wired- ANDing. The high during configuration (HDC) and low during configuration (LDC) are two user I/O pins which are driven active when an FPGA is in initialization, clear, or configure states. These signals and DONE/ PROG provide for control of external logic signals such as reset, bus enable, or PROM enable during configuration. For parallel master configuration modes, these signals provide PROM enable control and allow the data pins to be shared with user logic signals. User I/O inputs can be programmed to be either TTL or CMOS compatible thresholds. At powerup, all inputs have TTL thresholds and can change to CMOS thresh- alds at the completion of configuration, if the user has selected CMOS thresholds. The threshold of PWROWN and the direct clock inputs are fixed at a CMOS level. lf the crystal oscillator is used, it will begin operation before configuration is complete to allow time for stabilization before it is connected to the internal circuitry.vd a4 FPGA Data Book ATT3000 Series FPGAs Programming (continued) Configuration Data Configuration data to define the function and interconnection within an FPGA are loaded from an external Storage at powerup and on a reprogram signal. Several methods of automatic and controlled loading of the required data are available. Logic levels applied to mode selection pins at the start of configuration time determine the method to be used (see Table 2). The data may be either bit-serial or byte-parallel, depending on the configuration mode. Various Lucent programmable gate arrays have different sizes and numbers of data frames. For the ATT3020, con- figuration requires 14779 bits for each device, arranged in 197 data frames. An additional 40 bits are used in the header (see Figure 20). q144tti4 - DUMMY BITS* 0010 PREAMBLE CODE < 24-BIT LENGTH COUNT > CONFIGURATION PROGRAM LENGTH HEADER 114 ~ DUMMY BITS (4 BITS MINIMUM) 0 < DATA FRAME #001 > 111 FOR ATT3020 0 < DATA FRAME #002 > 111 0 <DATA FRAME #003 > 111 197 CONFIGURATION DATA FRAMES PROGRAM DATA (EACH FRAME CONSISTS OF: A START BIT (0) REPEATED FOR EACH LOGIC " - : A 71-BiT DATA FIEL CELL ARRAY IN A DAISY CHAIN 0 <DATA FRAME # 196 > 111 THREE STOP BITS 0 <DATA FRAME #197 > 111 1141 POSTAMBLE CODE (4 BITS MINIMUM} * The FPGA devices require four dummy bits minimum. Figure 19. Internal Configuration Data Structure Lucent Technoloaies Inc. 9244ATT3000 Series FPGAs FPGA Data Book Programming (continued) Table 3. ATT3000 Device Configuration Data Device ATT3020 ATT3030 ATT3042 ATT3064 ATT3090 Gates 2000 3000 4200 6400 9000 CLBs 64 100 144 224 320 (row x column) (8 x 8) (10 x 10) (12 x 12) (16 x 14) (20 x 16) IOBs 64 80 96 120 144 Flip-flops 256 360 480 688 928 Bits-per-frame 75 92 108 140 172 (with 1 start/3 stop) Frames 197 241 285 329 373 Program Data = 14779 22176 30784 46064 64160 Bits - Frames + 4 (excludes header) PROM Size (bits) = 14819 22216 30824 46104 64200 Program Data + 40-bit Headers Note: The length count produced by the MAKEBITS program = up to a multiple of 8} - (2 <K < 4) _ where K is a function of DONE and RESET timi increment is less than K. K additional clocks are needed to complete start-up after [(40-bit preamble + sum of program data + 1 per daisy-chain device) rounded ng selected. An additional 8 is added if the roundup length count is reached, POSTAMBLE DATA FRAME LAST FRAME 12}4 24 | 4 [e_ 75 -_+ m 3 tps STOP fc <a {Ca ! 4 7 Me | a | STOP 6C o \ > | PREAMBLE | LENGTH COUNT | | | DATA | | | | | | 3 | LENGTH COUNT? START START ' WEAK PULL-UP | HIGH oO ACTIVE DOUT LEAD DEVICE * The configuration data consists of a composite 40-bit Separated by 4-bit postambles. An additional final pos The length count is two less than the number of resul each be programmed to occur one cycle before or aft 2-312 1/2 CLOCK CYCLE DELAY FROM DATA INPUT fi PROGRAM A DONE INTERNAL RESET y Figure 20. FPGA Configuration and Start-Up : -3111(F) preambieflength count, followed by one or more concatenated LCA programs, tambie bit is added for each slave device, and the result rounded up to byte boundary. ting bits. Timing of the assertion of DONE and termination of the internal RESET may er the I/O outputs become active.FPGA Data Book ATT3000 Series FPGAs Programming (continued) The specific data format for each device is produced by the MAKEBITS command of the development system, and one or more of these files can then be combined and appended to a length count preamble and be transformed into a PROM format file by the MAKEPROM command of the ORCA Foundry Devel- opment System. The tie option of the MAKEBITS pro- gram defines output levels of unused blocks of a design and connects these to unused routing resources. This prevents indeterminate levels which might produce par- asitic supply currents. TIE can be omitted for quick breadboard iterations where a few additional mA of Icc are acceptable. The configuration bit stream begins with high preamble bits, a 4-bit preamble code, and a 24-bit length count. When configuration is initiated, a counter in the FPGA is set to 0 and begins to count the total number of con- figuration clock cycles applied to the device. As each configuration data frame is supplied to the FPGA, it is internally assembled into a data word. As each data word is completely assembled, it is loaded in parallel Lucent Technoloaies Inc. into one word of the internal configuration memory array. The configuration loading process is complete when the current length count equals the loaded length count and the required configuration program data frames have been written. Internal user flip-flops are held reset during configuration. Two user-programmable pins are defined in the uncon- figured FPGA: high during configuration (HDC) and low during configuration (COC), and DONE/PROG may be used as external control signals during configuration. In master mode configurations, itis convenient to use LDC as an active-low EPROM chip enable. After the last configuration data bit is loaded and the length count compares, the user I/O pins become active. Options in the MAKEBITS program allow timing choices of one clock earlier or later for the timing of the end of the internal logic reset and the assertion of the DONE sig- nal. The open-drain DONE/PROG output can be AND- tied with multiple FPGAs and used as an active-high READY, an active-low PROM enable, or a RESET to other portions of the system. The state diagram of Fig- ure 18 illustrates the configuration process. 9-313ATT3000 Series FPGAs FPGA Data Book Programming (continued) Master Mode In master mode, the FPGA automatically loads configu- ration data from an external memory device. There are three master modes which use the internal timing source to supply the configuration clock (CCLK) to time the incoming data. Serial master mode uses serial con- figuration data supplied to data-in (DIN) from a syn- chronous serial source such as the serial configuration PROM shown in Figure 19. Parallel master low and master high modes automatically use parallel data sup- plied to the D[7:0] pins in response to the 16-bit address generated by the FPGA. Figure 22 shows an example of the parallel master mode connections required. The FPGA HEX starting address is 0000 and increments for master low mode, and it is FFFF and decrements for master high mode. These two modes provide address compatibility with microprocessors which begin execution from opposite ends of memory. For master high or low, data bytes are read in parallel by each read clock (RCLK) and internally serialized by the configuration clock. As each data byte is read, the least significant bit of the next byte, DO, becomes the next bit in the internal serial configuration word. One master mode FPGA can be used to interface the configuration program-store, and pass additional concatenated configuration data to additional FPGAs in a serial daisy-chain fashion. CCLK is provided for the slaved devices, and their serialized data is supplied from DOUT to DIN, DOUT to DIN, etc. +5V DURING CONFIGURATION tT | | THE 5 kQ M2 PULL-DOWN L RESISTOR OVERCOMES THE $ - MO Mi PWRDWN INTERNAL PULL-UP, BUT IT ALLOWS M2 TO BE USER V/O. DOUT M2 rs 4 HDC GENERAL- Loc OPTIONAL PURPOSE int t IDENTICAL SLAVE USER l/O FPGAs CONFIGURED PINS 4 THE SAME : OTHER : VO PINS ATT3000 SERIES FPGA posts t ct to : PROGRAM#o| DONE/PROG ATTY700A ! CASCADED ! | ATTI700A | DIN DATA DATA MEMORY | CCLK CLK CLK LDCb+-o CE CEOP*9 CE ; ol RESET/OE i RESET/OE 1 I Poo 4 (HIGH RESETS THE ADDRESS POINTER) -3112(C) Note:The serial configuration PROM supports automatic loading of configuration programs up to 36/64/128 Kbits. Multiple devices can be cascaded to support additional FPGAs. An early DONE inhibits the data output one CCLK cycle before the FPGA /O becomes active. Figure 21. Master Serial Mode DIA-4 FPGA Data Book ATT3000 Series FPGAs Programming (continued) o~ +5V USER CONTROL OF HIGHER ORDER FROM ADDRESS BITS CT CAN BE USED TO SELECT FROM = ALTERNATIVE CONFIGURATIONS MO M1 PWRDWN 5kQ L_ <_| DOUT * i | | m2 CCLK KH} > HDC GENERAL- AtS eee t USER AG < d RCL A14 eee eROM PINS | diNiT M3teeel Dxes TI Ato ee e| ORLARGER) 5 | | OTHER VO PINS Att eee NX At0 A10 RESET _d RESET Ag Ag Feca =sA 8 AB yor AT AZ D7 7-06 A6 AG D6 Vale A5 AS DS 14 A4 Ad Day 7-193 A3 A3 D3 1] |] 02 A2 A2 Der, 01 At At DIR | D0 AO AO DOTA | LDC PT OE D/P CE 8 q+ DATA BUS -3113(F) Figure 22. Master Parallel Mode Lucent Technologies Inc. 9-315ATT3000 Series FPGAs FPGA Data Book Programming (continued) Peripheral Mode Peripheral mode provides a simplified interface through which the device may be loaded byte-wide, as a processor peripheral. Figure 23 shows the peripheral mode connections. Processor write cycles are decoded from the com- mon assertion of the active-low write strobe (WS), and two active-low and one active-high chip selects (CS0, CST, CS2). If all these signals are not available, the unused inputs should be driven to their respective active levels. The FPGA will accept 1 byte of tonfiguration data on the D[7:0] inputs for each selected processor write cycle. Each byte of data is loaded into a buffer register. The FPGA generates a CCLK from the internal timing generator and serializes the parallel input data for internal framing or for succeeding slaves on data out (DOUT). An output HIGH on READY/BUSY pin indicates the completion of loading for each byte when the input register is ready for a new byte. As with master modes, peripheral mode may also be used as a lead device for a daisy-chain of slave devices. + e +5V CONTROL ADDRESS DATA SIGNALS BUS BUS 8 = 5kQ MO M1 PWRDWN DI7:0] D(7:0] CCLK > * \ | DOUT }-} ~-L + ADDRESS \ DECODE P-4 CSO M2 |- LOGIC Hoc | +5V LDC b GENERAL- __ PURPOSE KN CS1 USER VO \ cs2 |} e ~ _d OTHER e WS VO PINS e RDY/BUSY _ -d INIT REPROGRAM _ io [o> D/P ~d RESET -3114(F) Figure 23. Peripheral Mode 2-316 . BSFPGA Data Book ATT3000 Series FPGAs Programming (continued) Slave Mode Slave mode provides a simple interface for loading the FPGA configuration as shown in Figure 24. Serial data are supplied in conjunction with a synchronizing input clock. Most slave mode applications are in daisy-chain configu- rations in which the data input is supplied by the previous FPGAs data out, while the clock is supplied by a lead device in master or peripheral mode. Data may also be supplied by a processor or other special circuits. +5V [ Mo Mi PWAOWN MICROCOMPUTER 5 KO STAB CCLK M2 ~\ * Do DIN pout} | + ort Hoc +} _ FPGA p} COC bp |, GENERAL + PURPOSE VO PORT pst USER 1/0 p4t+- ps}- $ OTHER : VO PINS : D6I~ ~ / D7}- INIT RESET -4 AESET -3115(F) Figure 24. Slave Mode Lucent Technologies Inc. 2-317ATT3000 Series FPGAs FPGA Data Book Programming (continued) Daisy Chain The ORCA Foundry for ATT3000 development system is used to create a composite configuration bit stream for selected FPGAs including a preamble, a length count for the total bit stream, multiple concatenated data programs, a postamble, plus an additional fill bit per device in the serial chain. After loading and passing on the preamble and length count to a possible daisy chain, a lead device will load its configuration data frames while providing a high DOUT to possible down- stream devices as shown in Figure 25. Loading contin- ues while the lead device has received its configuration program and the current length count has not reached the full value. Additional data are passed through the lead device and appear on the data out (DOUT) pin in serial form. The lead device also generates the CCLK to synchronize the serial output data and data in of downstream FPGAs. Data is read in on DIN of slave devices by the positive edge of CCLK and shifted out the DOUT on the negative edge of CCLK.A parallel master mode device uses its internal timing generator to produce an internal CCLK of eight times its EPROM address rate, while a peripheral mode device produces a burst of eight CCLKs for each chip select and write- Strobe cycle. The internal timing generator continues to operate for general timing and synchronization of inputs in all modes. Ci +5V +5V +5V +5V = [Mo M1 PWRDWN MO M1 PWRDWN Mo M1 PWRDWN 5kQ S 5kQ 5kQ CCLK CCLK CCLK M2 DOUT DIN DOUT SS DIN DOUT THC M2 M2 +~- GENERAL- | 4RCLK AIS AIS SUAVE #1 SLAVE in PURPOSE | At4 A14 Meer OCT | GENERAL- USER WO EPROM LDC b\ GENERAL- LDC b-\ PURPOSE : Ata At3 _ PURPOSE / USER VO _ e | USER VO Ai2 Ai2 OTHER e OTHER e OTHER VO PINS . V0 PINS ) | $ VOPINS At Att ) A10 Ato r DIP a r] DIP _ __ __ recA AS AS -daeser INT -d RESET INIT P MASTER 4, AB 707 A7 A7 D7 a D6 AG AG D6 rN 4 Ds AS A5 DS ln D4 A4 Ad D4 rm |-{ 03 Ag AS D3; |} D2 Ag A2 D2] i D1 Al Al D1 PY | D0 AO AQ DOT, DP LDC Te OE | -d RESET int P cE +5V 8 5 kQ EACH OPEN COLLECTOR REPROGRAM p 5S SYSTEM} 0 s5 RESET [eget 5c 5S -3116(F) Figure 25. Master Mode with Daisy-Chained Slave Mode Devices 2-318FPGA Data Book s4 ATT3000 Series FPGAs Special Configuration Functions The configuration data includes control over several special functions in addition to the normal user logic functions and interconnects: Input thresholds a Readback enable a DONE pull-up resistor n DONE timing a RESET timing Oscillator frequency divided by two Each of these functions is controlled by configuration data bits which are selected as part of the normal development system bit stream generation process. Input Thresholds Prior to the completion of configuration, all FPGA input thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS compatible as programmed. The use of the TTL threshold option requires some additional supply current for threshold shifting. The exception is the threshold of the PWRDWN input and direct clocks which always have a CMOS input. Prior to the completion of configuration, the user I/O pins each have a high- impedance pull-up. The configuration program can be used to enable the IOB pull-up resistors in the opera- tional mode to act either as an input load or to avoid a floating input on an otherwise unused pin. Readback The contents of an FPGA may be read back if it has been programmed with a bit stream in which the read- back option has been enabled. Readback may be used for verification of configuration and as a method for determining the state of internal logic nodes. There are three options in generating the configuration bit stream: = Never will inhibit the readback capability. = One-time will inhibit readback after one readback has been executed to verify the configuration. On-command will allow unrestricted use of read- back. Lucent Technologies Inc. Readback is accomplished without the use of any of the user I/O pins; only MO, M1, and CCLK are used. The initiation of readback is produced by a low-to-high transition of the MO/RTRIG (read trigger) pin. Once the readback command has been given, the input CCLK is driven by external logic to read back each data bit ina format similar to loading. After two dummy bits, the first data frame is shifted out, in inverted sense, on the M1/ RDATA (read data) pin. All data frames must be read back to complete the process and return the mode select and CCLK pins to their normal functions. The readback data includes the current state of each internal logic block storage element, and the state of the (.i and .ri) connection pins on each IOB. The data is imbedded into unused configuration bit positions during readback. This state information is used by the FPGA development system in-circuit verifier to provide visibil- ity into the internal operation of the logic while the Ssys- tem is operating. To read back a uniform time sample of all storage elements, it may be necessary to inhibit the system clock. Reprogram The FPGA configuration memory can be rewritten while the device is operating in the user's system. To initiate a reprogramming cycle, the dual-function pack- age pin DONE/PROG must be given a high-to-low tran- Sition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the FPGAs internal timing gen- erator. When reprogram begins, the user-programma- ble I/O output buffers are disabled and high-impedance pull-ups are provided for the package pins. The device returns to the clear state and clears the configuration memory before it prompts INITIALIZED. Since this clear operation uses chip-individual internal timing, the master might complete the clear operation and then Start configuration before the slave has completed the clear operation. To avoid this, wire-AND the slave INIT pins and use them to force a RESET on the master (see Figure 25). Reprogram control is often implemented by using an external open-collector driver which pulls DONE/PROG low. Once it recognizes a stable request, the FPGA will hold a low until the new configuration has been completed. Even if the reprogram request is externally held low beyond the configuration period, the FPGA will begin operation upon completion of configu- ration. 2-319a4 ATT3000 Series FPGAs FPGA Data Book Special Configuration Functions (continued) DONE Pull-Up DONE/PROG is an open-drain I/O pin that indicates the FPGA is in the operational state. An optional internal pull-up resistor can be enabled by the user of the devel- opment system when MAKEBITS is executed. The DONE/PROG pins of multiple FPGAs in a daisy chain may be connected together to indicate that all are DONE or to direct them all to reprogram. DONE Timing The timing of the DONE status signal can be controlled by a selection in the MAKEBITS program to occur a CCLK cycle before, or after, the timing of outputs being activated (see Figure 20). This facilitates control of external functions, such as a PROM enable or holding a system in a wait-state. 2-320 RESET Timing As with DONE timing, the timing of the release of the internal RESET can be controlled by a selection in the MAKEBITS program to occur a CCLK cycle before, or after, the timing of outputs being enabled (see Figure 20). This reset maintains all user-programmable flip-flops and latches in a zero state during configura- tion. Crystal Oscillator Division A selection in the MAKEBITS program allows the user to incorporate a dedicated divide-by-two flip-flop in the crystal oscillator function. This provides higher assur- ance of a symmetrical timing signal. Although the frequency stability of crystal oscillators is high, the symmetry of the waveform can be affected by bias or feedback drive. {inant Tarknainngiosc Inc.FPGA Data Book ATT3000 Series FPGAs Performance Device Performance The high performance of the FPGA is due in part to the manufacturing process, which is similar to that used for high-speed CMOS static memories. Performance can be measured in terms of minimum propagation times for logic elements. The parameter which traditionally describes the overall performance of a gate array is the toggle frequency of a flip-flop. The configuration for determining the toggle performance of the FPGA is shown in Figure 26. The flip-flop output Q is fed back through the combinatorial logic as Q to form the toggle flip-flop. Yy CLOCK -3117(F) Figure 26. Toggle Flip-Flop FPGA performance is determined by the timing of critical paths, including both the fixed timing for the logic and storage elements in that path, and the timing associated with the routing of the network. Examples of internal worst-case timing are included in the CLOCK TO performance data to allow the user to make the best use of the capabilities of the device. The ORCA Foundry Development System timing calculator or ORCA Foundry-generated simulation models should be used to calculate worst-case paths by using actual impedance and loading information. Figure 27 shows a variety of elements which are involved in determining system performance. Table 20 gives the parameter values for the different speed grades. Actual measurement of internal timing is not practical, and often only the sum of component timing is relevant as in the case of input to output. The relationship between input and output timing is arbi- trary, and only the total determines performance. Timing components of internal functions may be deter- mined by the measurement of differences at the pins of the package. A synchronous logic function which involves a clock to block-output and a block-input to clock setup is capable of higher-speed operation than a logic configuration of two synchronous blocks with an extra combinatorial block level between them. System clock rates to 60% of the toggle frequency are practical for logic in which an extra combinatorial level is located between synchronized blocks. This allows implementa- tion of functions of up to 25 variables. The use of the wired-AND is also available for wide, high-speed functions. OUTPUT COMBINATORIAL SETUP | | | ; TcKo | Tito ICK OP CLB CLB CLB |OB LOGIC LOGIC PAD {K) {K) CLOCK ioB! | [+ Texo | PAD > p) ro ~ ToKoP | 5-3118(F) Figure 27. Examples of Primary Block Speed Factors oo 2 aT. Behe Rl nnnws Inn 2-321ATT3000 Series FPGAs FPGA Data Book Performance (continued) Logic Block Performance Logic block performance is expressed as the propaga- tion time from the interconnect point at the input of the combinatorial logic to the output of the block in the interconnect area. Combinatorial performance is inde- pendent of the specific logic function because of the table look-up based implementation. Timing is different when the combinatorial logic is used in conjunction with the storage element. For the combinatorial logic func- tion driving the data input of the storage element, the critical timing is data setup relative to the clock edge provided to the flip-flop element. The delay from the clock source to the output of the logic block is critical in the timing of signals produced by storage elements. Loading of a logic block output is limited only by the resulting propagation delay of the larger interconnect network. Speed performance of the logic block is a function of supply voltage and temperature (see Figures 28 and 29). Interconnect Performance Interconnect performance depends on the routing resource used to implement the signal path. As dis- cussed earlier, direct interconnect from block to block provides a fast path for a signal. The single metal 9.299 segment used for long lines exhibits low resistance from end to end, but relatively high capacitance. Signals driven through a programmable switch will have the additional impedance of the switch added to their normal drive impedance. General-purpose interconnect performance depends on the number of switches and segments used, the presence of the bidirectional repowering buffers, and the overall loading on the signal path at all points along the path. In calculating the worst-case timing for a general interconnect path, the timing calculator portion of the ORCA Foundry Development System accounts for all of these elements. As an approximation, interconnect timing is propor- tional to the summation of totals of local metal seg- ments beyond each programmable switch. In effect, the time is a sum of R-C time each approximated by an R times the total C it drives. The R of the switch and the C of the interconnect are functions of the particular device performance grade. For a string of three local interconnects, the approxi- mate time at the first segment after the first switch resistance would be three unitsan additional two units after the next switch plus an additional unit after the last switch in the chain. The interconnect R-C chain terminates at each repowering buffer. The capacitance of the actual block inputs is not significant; the capaci- tance is in the interconnect metal and switches. Figure 30 illustrates this. lucent Technologies inc.a? ; 4 FPGA Data Book ATT3000 Series FPGAs Performance (continued) 1 3b cbeteeeeeeee eee eee Loheeeee: ooo 12 pete Qe [eon e cn eeedeneeeeees preeeneeed teen AR beyevdereeeee toceeeceeeesees fe oon a ro 1 = ( : ' : tw 1 , t ' ' oO 4 1 t Noo dA pvteraprretne porters mo doc decsents es ro WW Pte eee \ eee eee dece eee eee Lecce eee dees 2 _ ot oe ; oo Ss 10-+4 t < ; oc , 1 ' > ' 1 ' 1 O tt th x ; ; ZAP ote Monn pw nnn an tea aan 9 ~ 1 ' ' ' t , Zz L t ; > tt tt & 10-4 Pate we enn baw seeeen diese Z 08h 1-1 X---- posse decceeeee dee decee tee onan % ws 4 tt ; id ; ; a 1 1 1 , ' 1 t 1 1 O.7 Arr nrert rcpt pases an a ; ; 0.6 b-t--eeneoo ee posses perenne fevdecteeeeeteneood 0.9 Poorprrrn poor pees ee wo i | (4 l | \ -55 40 0 ~=.30 70 85 125 4.0 4.5 5.0 5.5 6.0 TEMPERATURE (C) Vcc -3119(F) 5-3120(F) Figure 28. Change in Speed Performance Figure 29. Speed Performance of a CMOS Device ef arr No ertttt AWN + eo ween 3 \ooeeeee baeseee i REPOWERING BUFFER CLB TF Oy F TIMING: INCREMENTAL A1(C1 +C2 +C3) + R2(C2 + C3) +A3+C3 RC + BUFFER IF R1 = A2=A3=RANDC1=C2=C3=C, T1=3RC T2=3AC+2RC = 13=3AC +2RC+RC THEN CUMULATIVE TIMING = 3RC = 5AC = 6RC 5.a121(F) Figure 30. Interconnection Timing Example re 2-323ATT3000 Series FPGAs FPGA Data Book Power Power Distribution Power for the FPGA is distributed through a grid to achieve high noise immunity and isolation between logic and I/O. Inside the FPGA, a dedicated Vcc and ground ring surrounding the logic array provides power to the I/O drivers (see Figure 31 below). An indepen- dent matrix of Vcc and ground lines supplies the inte- rior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the external package power pins are all connected and appropriately decoupled. Typically a 0.1 F capacitor connected near the Vcc and ground pins of the package will provide adequate decoupling. Output buffers which drive the specified 4 mA loads under worst-case conditions may drive 25 to 30 times this amount under best-case process conditions. Noise can be reduced by minimizing external load capaci- tance and reducing simultaneous output transitions in the same direction. It may also be beneficial to locate heavily loaded output buffers near the ground pads. The IOB output buffers have a slew-limited mode which should be used where output rise and fall times are not speed critical. Slew-limited outputs maintain their dc drive capability but generate less external reflections and internal noise. More than 32 fast outputs should not be switch- ing in the same direction simultaneously. GROUND ANDO .d-- Vcc RING FOR Veco [J |_-~ VO DRIVERS - ] Vcc Co LOGIC POWER GRID -3122(F} Figure 31. FPGA Power Distribution bocce tTrarnkhwmninnine Inc.FPGA Data Book ae ATT3000 Series FPGAs Power (continued) Power Dissipation The FPGA exhibits the low power consumption charac- teristic of CMOS ICs. For any design, the user can use Figure 32 to calculate the total power requirement based on the sum of the capacitive and de loads both external and internal. The configuration option of TTL chip input threshold requires power for the threshold reference. The power required by the static memory cells which hold the configuration data is very low and may be maintained in a powerdown mode. Typically, most of power dissipation is produced by externa! capacitive loads on the output buffers. This load and frequency dependent power is 25 pW/pF/MHz per output. Another component of 1/O power is the de loading on each output pin by devices driven by the FPGA. Internal power dissipation is a function of the number and size of the nodes, and the frequency at which they change. In an FPGA, the fraction of nodes changing on a given clock is typically low (10% to 20%). For example, in a large binary counter, the average clock cycle produces changes equal to one CLB output at the clock frequency. Typical global clock buffer power is between 1.7 mW/MHz for the ATT3020 and 3.6 mW/ MHz for the ATT3090. The internal capacitive load is more a function of interconnect than fan-out. With a typical load of three general interconnect segments, each configurable logic block output requires about 0.4 mW per MHz of its output frequency: Total Power = Vcc + Icco + External (dc + Capacitive) + Internal (CLB + 1OB + Long Line + Pull-up) lo oc ke bore eke elinrnewIAn Because the control storage of the FPGA is CMOS static memory, its cells require a very low standby cur- rent for data retention. In some systems, this low data retention current characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA has built-in powerdown logic which, when activated, will disable normal opera- tion of the device and retain only the configuration data. All internal operation is suspended and output buffers are placed in their high-impedance state with no pull- ups. Powerdown data retention is possible with a sim- ple battery backup circuit, because the power require- E ment is extremely low. For retention at 2.4 V, the required current is typically on the order of 50 nA. To force the FPGA into the powerdown state, the user must pull the PWRDWN pin low and continue to supply a retention voltage to the Vcc pins of the package. When normal power is restored, VCC is elevated to its normal operating voltage and PWRDWN is returned to a high. The FPGA resumes operation with the same internal sequence that occurs at the conclusion of configuration. Internal I/O and logic block storage ele- ments will be reset, the outputs will become enabled and the DONE/PROG pin will be released. No configu- ration programming is involved. When the power supply is removed from a CMOS device, it is possible to supply some power from an input signal. The conventional electrostatic input pro- tection is implemented with diodes to the supply and ground. A positive voltage applied to an /O will cause the positive protection diode to conduct and drive the power pin. This condition can produce invalid power conditions and should be avoided. A large series resis- tor might be used to limit the current or a bipolar buffer may be used to isolate the input signal. 2-325FPGA Data Book ATT3000 Series FPGAs Power (continued) < E Boon eo eo eo oO anonnonnst O N = ~-MDOoOn Ww wt oO N - m7mon~ O WY * oo N rer Oooo oO a Oo Q Qo Oo t v , 1 t t ' t , ' ' t ' ' wD PIN Eb : : Pe bb 3 PN oo rrr alae a ee poor eee + ror brs ; He ye ee NS weed ee ee ee ee eee ee eee ee ee Ne rrr tetra rr NN tr see rae er crs c rec ae ccs se eo ee rt ttn a wopcns er comes rece Nee nr er | DN ' pec cbc cb ecbe ches Ne secs denecrs ss esce tes tee bee feo eben eee ete Ngee root tert tec toe teccdess sss ss bonne eect ne 8 roNGp ors a \ por Pb ENE N\ to Pp EN ee ee OO ne Po o t r r c 7? ' r t _ Pb btoiN ; propor ors _ ropoporot ; ot 3 robor obo bop pop d = rr aw ' tot S por ob op bt pore > PL Qe eee NOL bb NE ENS bee o 8 ee a bate Moet bebo} Pye ek tot Poa wy ee ee ee Jee XQ ocb bebe yhe bb went ee cbeceee see eoe * G ' , , ' t 1 1 1 t ' 1 1 . uw por bbs ; pop bor NG toro. , ' book 1 1 ' ac Poth eee bbe bee eden eee ee qeseeeee- Nib bag! wenden ee ee ede eee eee ee dee ete eben dee de ede eee Nee bene eee eee om & mops rece oe 4 rome reps ee oo AR pore pop or port iN iN t 1 4 , i v ' 1 t I t A J 1 U 1 1 por p G NY hort ON 1 pote heehee betes ee eee Meee eee LN ecb ee be bee eee ede eee ee eee eee dee Lt ete eden eee eb Nee eee ee ou ror bg roror bobo rot Ph bP PEE NG | I Ht pooh rr port ror ror rs ee ON \ port ee ee ee ee Beebe eb eee dw eee ee a ho teoech eee Roe be-bk ee ete ee ee eK! teow ee yee ee ew ew = Je e-bws rr ; EEN roo Xt - por bor ps poror ob ON Port a porob bor rg Port FAG ee : Pog : \ NY ot 5ae 7 ee PE bP NS ett Sue , ' ' ' ot 1 ' oN 6 > t 1 1 1 1 1 oe Fe t 1 1 1 ' 2a4IZ po : a pop SS PN o ouze 8 34 S wo t is] al - a OfRrS OW OW 3&7 va crue 5 bE SHEEES Og = ae az Ookese5 az = rs ks I 2S- Su aS e a) oma Qa Of om n HONE Tw 20 I a SONDr oO oO Oo on oO o O ow w N 2 o 5-3123(F) Note: Total chip power is the sum of VCC x ICCO plus effective internal and external values of frequency-dependent capacitive charging currents and duty-factor-dependent resistive loads. Figure 32. FPGA Power Consumption by Element me Ita4 FPGA Data Book ATT3000 Series FPGAs Pin Information Table 4. Permanently Dedicated Pins Symbol Name/Description fo rn Vcc Two to eight (depending on package type) connections to the nominal +5 V supply voltage. All must be connected. GND Two to eight (depending on package type) connections to ground. All must be connected. PWRDWN | A low on this CMOS compatible input stops all internal activity to minimize Vcc power, and puts all output buffers in a high-impedance state; configuration is retained. When the PWROWN pin returns high, the device returns to operation with the same sequence of buffer enable and DONE/PROG as at the completion of configuration. All internal storage elements are reset. If not used, PWROWN must be tied to VCc. RESET This is an active-low input which has three functions: Prior to the start of configuration, a LOW input will delay the start of the configuration process. An internal circuit senses the application of power and begins a minimal time-out cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configura- tion begins. = If RESET is asserted during a configuration, the FPGA is reinitialized and will restart the con- figuration at the termination of RESET. |f RESET is asserted after configuration is complete, it will provide an asynchronous reset of all OB and CLB storage elements of the FPGA. CCLK Configuration Clock. During configuration, this is an output of an FPGA in master mode or peripheral mode. FPGAs in slave mode use it as a clock input. During a readback operation, it is a clock input for the configuration data being filtered out. DONE/ DONE Output. Configurable as open drain with or without an internal pull-up resistor. At the PROG completion of configuration, the circuitry of the EPGA becomes active in a synchronous order, and DONE may be programmed to occur one cycle before or after that occurs. Once configura- tion is done, a high-to-low transition of this pin will cause an initialization of the FPGA and start a reconfiguration. Mo Mode 0. This input, M1, and M2 are sampled before the start of configuration to establish the configuration mode to be used. loinant Tarknalinaciae Ince 2-327vw i a ATT3000 Series FPGAs FPGA Data Book Pin Information (continued) Table 5. /O Pins with Special Functions Symbol Name/Description ja M2 Mode 2. This input has a passive pull-up during configuration. Together with MO and M1, it is sampled before the start of configuration to establish the configuration mode to be used. After configuration, this pin becomes a user-programmable I/O pin. HDC High During Configuration. HDC is held at a high level by the FPGA until after configuration. It is available as a control output indicating that configuration is not yet completed. After configuration, this pin is a user |/O pin. | OQ Oy Low During Configuration. This active-low signal is held at a low level by the FPGA until after configuration. It is available as a control output indicating that configuration is not yet completed. It is particularly useful in master mode as a low enable for an EPROM. After configuration, this pin is a user I/O pin. If used as a low EPROM enable, it must be programmed as a high after configuration. Zz +f This is an active-low, open-drain output which is held low during the power stabilization and internal clearing of the configuration memory. It can be used to indicate status to a configuring microprocessor or, as a wired-AND of several slave mode devices, a hold-off signal for a master mode device. After configuration, this pin becomes a user-programmable /O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (auxiliary buffer) in the lower right corner. XTL1 This user I/O pin can be used to operate as the output of an amplifier driving an external crystal and bias circuitry. XTL2 This user /O pin can be used as the input of an amplifier connected to an external crystal and bias circuitry. The I/O block is left unconfigured. The oscillator configuration is activated by routing a net from the oscillator buffer symbol output and by the MAKEBITS program. CS0, CST, | These four inputs represent a set of signals, three active-low and one active-high, which are CS2, WS __| used in the peripheral mode to control configuration data entry. The assertion of all four generates a write to the internal data buffer. The removal of any assertion clocks in the D[7:0] data present. In the master parallel mode, WS and CS2 are the AO and A1 outputs. After configuration, the pins are user-programmable I/O pins. ~~ ArT y oe tte eke pnlanae INC.FPGA Data Book ATT3000 Series FPGAs Pin Information (continued) Table 5. VO Pins with Special Functions (continued) Symbol Name/Description | RCLK During master parallel mode configuration, RCLK represents a read of an external dynamic memory device (normally not used). RDY/BUSY | During peripheral parallel mode configuration, this pin indicates when the chip is ready for another byte of data to be written to it. After configuration is complete, this pin becomes a user- programmed I/O pin. D[7:0] This set of eight pins represents the parallel configuration byte for the parallel master and peripheral modes. After configuration is complete, they are user-programmed I/O pins. A[15:0] This set of 16 pins presents an address output for a configuration EPROM during master parallel mode. After configuration is complete, they are user-programmed (/O pins. DIN This user I/O pin is used as serial data input during slave or master serial configuration. This pin is data zero input in master or peripheral configuration mode. DOUT This user I/O pin is used during configuration to output serial configuration data for daisy- chained slaves data in. TCLKIN This is a direct CMOS level input to the global clock buffer. /O Input/Output (Unrestricted). May be programmed by the user to be input and/or output pin following configuration. Some of these pins present a high-impedance pull-up (see next page) or perform other functions before configuration is complete (see above). Lucent Technologies Inc. 2-329ATT3000 Series FPGAs 4? FPGA Data Book Pin Information (continued) Table 6A. ATT3000 Family Configuration (44-, 68-, and 84-PLCC; 100-MQFP; and 100-TQFP) Configuration Mode (M2:M1:M0Q) | 44 84 100 100 User Slave |Master-Serial| Peripheral | Master-High | Master-Low | picc* 68 PLCC pcect | mare | TaFP Operation (4:1:1) (0:0:0) (1:0:1) (1:1:0) (1:0:0) PWROWN | PWROWN PWRDWN PWRDWN PWROWN 7 10 12 29 26 PWRDWN | Vcc vec Vcc vec Vcc 12 18 22 41 38 Vcc M1 (High) M1 (Low) M1 (Low) M1 (High) M1 (Low) 16 25 31 52 49 RDATA MO (High) MO (Low) Mo (Low) MO (High) MO (Low) 17 26 32 54 51 RTRIG | M2 (High) | M2 (Low) M2 (High) | M2 (High) M2 (Low) 18 27 33 56 53 VO HDC (High) | HDC (High) | HDC (High) | HDC (High) | HDC (High) 19 28 34 57 54 VO | [DC (Low) ; LDC (Low) LOC (Low} CDC (Low) LDC (Low) 20 30 36 59 56 vO INIT INIT INIT t INIT INIT 22 34 42 65 62 VO GND GND GND GND GND 23 35 43 66 63 GND ae 26 43 53 76 73 XTL2-l/O RESET RESET RESET RESET RESET 27 44 54 78 75 RESET | DONE DONE DONE DONE DONE 28 45 55 80 77 PROG : a SS OTe DI 2 D7. 46 56 81 78 VO Hes Bice coe PREPS Mo 30 47 57 82 79 XTL1-I/O DE os D6." DE. 48 58 83 80 vO 2DS DS DS. 49 60 87 84 vO CS = 50 61 88 85 vO DAs D4 D4 _ 54 62 89 86 vO vec | vec Vcc VCC Vcc 34 52 64 91 88 VCC i 3 SE DOs DS: DO _ 53 65 92 89 vO eS ee 54 66 93 90 /O ee DR be Dee bere DAO 55 67 94 91 ie) oe eee ee ee 56 70 98 95 vO ESE RDY/BUSY RCLK RCLK _ 57 71 99 96 vO DN |. DN = [> DO = ID DOTS De Be 58 72 100 97 vO DOUT DOUT DOUT DOUT DOUT 39 59 73 1 98 vO CCLK CCLK CCLK CCLK CCLK 40 60 74 2 99 CCLK : OS oWS. AO AO _ 61 75 5 2 VO CS20 0 Al Al _ 62 76 6 3 VO ores A2 A2 _ 63 77 8 5 fe) A3 A3 _ 64 78 9 6 VO A1t5 A15 _ 65 81 12 9 vO A4 A4 66 82 13 10 VO Al4 Al4 _ 67 83 14 11 VO 25) AS A5 _ 68 84 15 12 0 GND GND GND GND GND 1 1 1 16 13 GND at A13 Ai3 _ 2 2 17 14 VO A6 A6 _ 3 3 18 15 Vo Al2 A12 4 4 19 16 VO A7 A7 _ 5 5 20 17 VO | Atl Alt _ 6 8 23 20 VO AB AB 7 9 24 21 vO | Ai0 A10 8 10 25 22 VO AQ Ag _ 9 om 26 23 VO __]Represents a 50 kQ to 100 kQ pull-up. * Peripheral mode and master parallel mode are not supported in the 44-PLCC package: see Table 7. t Pin assignments for the ATT3064/ATT3090 differ from those shown; see page 2-261. * NIT is an open-drain output during configuration. 2-330 Lucent Technologies Inc.FPGA Data Book ATT3000 Series FPGAs Pin Information (continued) Table 6B. ATT3000 Family Configuration (132-PPGA, 144-TQFP, 160-MQFP, 175-PPGA, 208-SQFP) Configuration Mode (M2:M1:MO0) 132 144 160 175 208 User Slave |Master-Serial| Peripheral | Master-High | Master-Low | ppGa | TQFP | MQFP | PPGA | SQFP | Operation (4:1:1) (0:0:0) (1:0:1) (1:1:0) (1:0:0) PWROWN PWROWN PWROWN PWROWN PWADWN Al 1 159 B2 3 PWRDWN vec VCC vec vec Vcc C8 19 20 Dg 26 Vcc M1 (High) M1 (Low) M1 (Low) M1 (High) M1 (Low) B13 36 40 B14 48 RDATA MO (High) MO (Low) Mo (Low) MO (High) MO (Low) Al4 38 42 B15 50 RTRIG M2 (High) M2 (Low) Me (High) M2 (High} M2 (Low) C13 40 44 C15 56 0 HDC (High) | HDC (High) | HDC (High) | HDC (High) | HDC (High) B14 44 45 E14 57 vO CDC (Low) | (LOC (Low) COC (Low) LBC (Low) CDC (Low) Di4 45 49 DI6 61 vO INIT * INIT * INIT * INIT * INIT * G14 53 59 H15 77 vO GND GND GND GND GND H12 $5 19 Ji4 25 GND . Bie 8 Q : M13 69 76 P15 100 XTL2-VO RESET RESET RESET RESET RESET P14 71 78 Rid 102 RESET DONE DONE DONE DONE DONE N13 73 80 R14 107 PROG EM D7: DF 2 DT es Mi2 74 84 N13 109 VO eS an P13 75 82 T14 110 XTL1-V/0 oe -DE: DE. D N11 78 86 P12 115 VO ee DB cp Poe DS: 05 M9 84 g2 TI 122 1/0 G80 ce eh oes NQ 85 93 R10 123 vO ae D4 D4 pee D4 N8 88 98 Rg 128 VO vec | Vcc vec VCC voc M8 90 100 Ng 130 vec : 203. SDS a. N7 92 102 P8 132 /O ae P6 93 103 R8 133 0 D2. M6 96 108 R7 138 vO oe DES M5 102 114 RS 145 VO = ee Bee RCLK N4 103 115 PS 146 YO ee DIN Pee DING ep DO: ne 2 DO. N2 106 119 R3 151 WO DOUT DOUT DOUT DOUT DOUT M3 107 120 N4 152 Vo CCLK CCLK CCLK CCLK CCLK P41 108 121 R2 153 CCLK Bee AWS. AO AO M2 111 124 P2 161 /0 Al Al Ni 112 125 M3 162 V/O A2 A2 L2 115 128 PI 165 vO A3 A3 L1 116 129 N1 166 ie) Ai5 A15 K4 119 132 M1 172 vO A4 A4 J2 120 133 L2 173 VO Ai4 Al4 H1 123 136 K2 178 vO ee ee AS AS H2 124 137 K1 179 VO GND GND GND GND GND H3 126 139 J3 182 GND me eh EE Os AI3 A13 G2 128 141 H2 184 ie) AS A6 G1 129 142 Hi 185 VO A12 Al2 F2 133 147 F2 192 vO A?7 A7 E1 134 148 E1 193 0 Ait All D1 137 151 D1 199 0 A8 A8 D2 138 152 Ct 200 vO A10 A10 BI 144 155 E3 203 vO oe ee ce e Ag Ag C2 142 156 C2 204 He) [ ]Represents a 50 kQ to 100 kQ pull-up. * [NIT is an open-drain output during configuration. | ucrent Technologies Inc. 2-331ATT3000 Series FPGAs FPGA Data Book Pin Assignments Table 7. ATT3030 44-Pin PLCC Pinout Pin No. Function Pin No. Function f GND 23 GND 2 /O 24 /O 3 /O 25 VO 4 vO 26 XTL2-1/0 5 0 27 RESET 6 vO 28 DONE-PROG 7 PWRDWN 29 VO 8 TCLKIN-VO 30 XTL1-BCLKIN-I/O 9 vO 31 vO 10 VO 32 He) 11 ie) 33 VO 12 Vcc 34 Vec 13 VO 35 /0 14 vO 36 /O 15 VO 37 /0 16 M1RDATA 38 DIN-I/O 17 MORTRIG 39 DOUT-1/O 18 M2-V/O 40 CCLK 19 HDC-I/O 41 VO 20 LDC-1/O 42 /O 21 0 43 /0 22 INIT-1/O 44 /O Notes: Peripheral mode and master parallel mode are not supported in the M44 package. Parallel address and data pins are not assigned. YN ANAND lisrrant Tarkhnalaniac Ines PGA Data Book ATT3000 Series FPGAs in Assignments (continued) able 8. ATT3020, ATT3030, and ATT3042; 68-PLCC and 84-PLCC Pinout Pin Numbers Pin Numbers 68 84 Function 68 84 Function PLCC | PLCC PLCC | PLCC 10 12 PWROWN 38 46 /O 11 13 TCLKIN-1/O 39 47 0 14 yor 40 48 vO 12 15 0 41 49 ie) 13 16 VO 50 vot 17 ie) 51 ot 14 18 VO 42 52 0 15 19 vO 43 53 XTL2-/O 16 20 VO 44 54 RESET 17 21 0 45 55 DONE-PROG 18 22 Vcc 46 56 D7-/0 19 23 vO 47 57 XTL1-BCLKIN-l/O 24 VO 48 58 D6-I/O0 20 25 VO 59 VO 21 26 vO 49 60 D5-1/0 22 27 VO 50 61 CS0-1/0 28 vO 54 62 D4-/0 23 29 0 63 VO 24 30 VO 52 64 Vcc 25 31 M1RDATA 53 65 D3-/0 26 32 MO-RTRIG 54 66 CST-V/O 27 33 M2-1/O 55 67 D2-/0 28 34 HDC-I/O 68 VO 29 35 VO 69 vot 30 36 LDC-V/O 56 70 Di-/0 31 37 vO 57 71 RDY/BUSY-RCLK-1/O 38 vot 58 72 DO-DIN-I/O 32 39 VO 59 73 DOUT-I/O 33 40 /O 60 74 CCLK 44 vot 61 75 AO-WS-I/O 34 42 INIT-V/O 62 76 A1-CS2-/0 35 43 GND 63 77 A2-1/0 36 44 0 64 78 A3-/0 37 45 vO 79 ot * Unpragrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused |OBs. Programmed outputs are default slew-limited. + Indicates unconnected package pins for the ATT3020. mm $$ Trakhrnnlianing Inn 2-3337 a4 ATT3000 Series FPGAs FPGA Data Book Pin Assignments (continued) Table 8. ATT3020, ATT3030, and ATT3042; 68-PLCC and 84-PLCC Pinout (continued) Pin Numbers Pin Numbers 68 84 Function 68 84 Function PLCC | PLCC PLCC | PLCC 80 ot 4 4 A12-/0 65 81 A15-1/O 5 5 A7-I/O 66 82 A4-I/0 _ 6 vot j 67 83 A14-l/0 7 yor 68 84 A5-1/0 6 8 A11-l/0 1 1 GND 7 9 A8-V/0 2 2 A13-I/0 8 10 A10-I/O 3 3 A6-/O 9 11 A9-I/O * Unprogrammed |OBs have a default pull-up; this prevents an undefined pad tevel for unbonded or unused 1OBs. Programmed outputs are default slew-limited. + Indicates unconnected package pins for the ATT3020. Note: Table 8 describes the pin assignments for three different chips in two different packages. The function column lists 84 of the 118 pads on the ATT3042 and 84 of the 98 pads on the ATT3030. Ten pads (indicated by an asterisk) do not exist on the ATT3020, which has 74 pads, therefore, the corresponding pins on the 84-pin packages have no connections to an ATT3020. bt Te emhbemaelrnmnime IneFPGA Data Book ATT3000 Series FPGAs Pin Assignments (continued) Table 9. ATT3064 and ATT3090 84-PLCC Pinout Lc C Function ote c Function ote C Function 12 PWRDWN 40 /O 68 D2-1/0* 13 TCLKIN-I/O 41 INIT/O* 69 /O 14 VO 42 Vcc" 70 D1-V/O 15 /0 43 GND 71 RDY/BUSY-RCLK-1/O 16 V/O 44 /O 72 DO-DINI/O 17 0 45 /O0 73 DOUT-V/O 18 /O 46 /O 74 CCLK 19 /O 47 VO 75 AO-WS-I/O / 20 /0 48 /0 76 A1-CS2-l/0 21 GND* 49 vO 77? A2-/0 22 Vcc 50 /O 78 A3-V/0 23 VO 51 /0 79 \/0* 24 vO 52 /O 80 i/O* 25 VO ; 53 XTL2-I/O 81 A15-W/0 26 vO 54 RESET 82 A4-I/0 27 /O 55 DONE-PROG 83 A14-1/0 28 VO 56 D7-/O 84 A5-1/O 29 /O 57 XTL1-BCLKIN-I/O 1 GND 30 0 58 D6-V/O 2 Vcc* 31 M1RDATA 59 VO 3 A13-1/0* 32 MO-RTRIG 60 D5-I/0 4 A6-1/O* 33 M2-I/O 61 cs0-1/O 5 At21/O* 34 HDC-I/O 62 D4-l/0 6 A7-1/0* 35 V/O 63 vO 7 /O 36 LDC-1/O 64 Vcc 8 A11-I/O 37 VO 65 GND* 9 A8-1/O 38 VO 66 D3-1/0* 10 A10-1/0 39 vO 67 CSi-1/O* 11 A9-1/O * Different pin definition than ATT3020/ATT3030/AT T3042 PC84 package. Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad jevel for unbonded or unused IOBs. Programmed outputs are default slew-limited. biurant Tachnoaloniac inc 2-335ATT3000 Series FPGAs a 4 FPGA Data Book Pin Assignments (continued) Table 10. ATT3020, ATT3030, and ATT3042 100-MQFP Pinout | MorP Function MOrP Function orp Function 16 GND 50 /O* 84 /O* 17 A13-V/O 51 VO" 85 VO" 18 A6-I/0 52 M1RDATA 86 /O 19 Ai2-/0 53 GND* 87 D5-1/0 20 A7-/O 54 MO-RTRIG 88 CS0-1/0 24 VO" 55 Vcc* 89 D4-1/0 22 VO" 56 M2-1/O 90 VO 23 A11-I/0 57 HDC-I/O 91 Vcc 24 A8-1/O 58 0 92 D3-/O 25 A10-/0 59 [DG-1/0 93 CSi-1/0 26 A9-1/0 60 /O* 94 D2~1/O 27" Vcc 61 /0* 95 VO 28 GND 62 /0 96 VO" 29 PWRDOWN 63 VO 97 VO" 30 TCLKIN-V/O 64 VO 98 D1-/0 31 VO" 65 INIT-/O 99 | RCLK-RDY/BUSY-1/0 32 VO" 66 GND 100 DO-DIN-I/O | 33 /0* 67 0 1 DOUT-I/O | 34 /O 68 VO 2 CCLK 35 VO 69 vO 3 Voc* 36 VO 70 VO 4 GND* 37 VO 71 VO 5 AO-WS-I/O 38 VO 72 /O 6 A1-CS2-1/O0 39 0 73 VO 7 VO** 40 /O 74 /O* 8 A2-V/0 44 Vcc 75 0" 9 A3-/0 42 VO 76 XTL2V/O 10 0" 43 VO 77" GND 11 0" 44 VO 78 RESET 12 A15-1/0 45 VO 79 Vcc* 13 A4-/0 46 VO 80 DONE-PROG 14 A14-I/0 | 47 VO 81 D7-V/O 15 A5-V/O | 48 VO 82 | XTLI-BCLKIN-V/O || _ | 49 0 83 D6-1/0 lOBs. Programmed outputs are default slew-limited. Mn Aaam * Only 100 of the 118 pads on the ATT3042 are connected to the 100 package pins. Two pads, indicated by double asterisks, do not exist on the ATT3030, which has 98 pads; therefore, the corresponding pins have no connections. Twenty-six pads, indicated by single or double asterisks, do not exist on the ATT3020, which has 74 pads; therefore, the corresponding pins have no connections. Note: Unprogrammed !OBs have a default pull-up; this prevents an undefined pad level for unbonded or unused cme. Teak entnannes inn-PGA Data Book ATT3000 Series FPGAs in Assignments (continued) able 11. ATT3030, ATT3042, and ATT3064 100-TQFP Pinout rarP Function rorP Function TOP Function 13 GND 47 ie) 81 1/0 14 A13-I/0 48 VO 82 /O 15 A6-I/O 49 M1RDATA 83 VO 16 A12-I/0 50 GND 84 D5-/0 17 A7-W/O 51 MO-RTRIG 85 CsSo-I/0 18 VO 52 Vcc 86 D4-1/0 19 /O 53 M2-l/O 87 /0 20 Ai1-I/O 54 HDC-1/0 88 Vcc 21 A8-I/O 55 /O 89 D3-V/O 22 A10-I/O 56 LDC-l/O 90 csi-l/O 23 A9-1/0 57 vO 91 D2-V/O 24 Vcc 58 VO 92 /O 25 GND 59 /0 93 /0 26 PWRDWN 60 0 94 0 27 TCLKIN-I/O 61 V/O 95 D1-1/O 28 /O* 62 INIT-1/O 96 | RCLK-RDY/BUSY-1I/O 29 V/O 63 GND 97 DO-DIN-I/O 30 /0 64 /O 98 DOUT-1/O 31 V/O 65 /O 99 CCLK 32 VO 66 1/0 100 Vcc 33 VO 67 0 1 GND 34 vO 68 VO 2 A0-WS-I/O 35 /O 69 fe) 3 A1CS2-1/0 36 VO 70 /O 4 1/0" 37 VO 71 VO 5 A2-I/0 38 Vcc 72 VO 6 A3-l/0 39 VO 73 XTL2-V/0 7 vO 40 VO 74 GND 8 vO 41 ie) 75 RESET 9 A15-l/0 42 VO 76 Vcc 10 A4-l/0 43 /0 77 DONE-PROG 114 A14-1/0 44 /O 78 D7-I/0 12 A5-l/0 45 ie) 79 | XTLI-BCLKIN-V/O |}; 46 /O 80 D6-/0 * Indicates unconnected package pins for the ATT3030. Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused {OBs. Programmed outputs are default slew-limited. 1 mmnt Tarnhnnlanioge ine 2-3374 ATT3000 Series FPGAs FPGA Data Book Pin Assignments (continued) Table 12. ATT3042 and ATT3064 132-PPGA Pinout ope. A Function oPaA Function ppc Function C4 GND F12 VO N6 /0* Al PWRDWN E14 /O P5 (O* C3 TCLKIN I/O F13 VO M6 D2-1/0 B2 VO Fi4 VO N5 VO B3 VO G13 vO P4 0 A2 /O* G14 INIT-l/O P3 VO | B4 0 G12 voc M5 D1-l/O C5 0 H12 GND N4 RACLK-RDY/BUSYI/O A3 O* H14 /O P2 ie A4 /O H13 VO N3 VO B5 VO J14 vO N2 DO-DIN-I/O C6 vO J13 VO M3 DOUT-I/O A5 0 K14 ie) Pt CCLK B6 vO J12 0 M4 VCC A6 0 K13 0 L3 GND B7 0 L14 /O* M2 A0-WS-1/O C7 GND L13 VO Ni A1CS2-1/0 C8 VCC K12 0 M1 0 A7 vO M14 0 K3 0 B8 VO N14 0 L2 A2-/0 AB VO M13 XTL2-I/0 4 A3-/0 AQ 0 L12 GND K2 VO B9 0 P14 RESET J3 VO C9 0 M11 Vcc K1 A15-I/0 A10 0 N13 DONE-PROG J2 A4I/0 B10 VO M12 D7-/0 J VO* Alt VO" P13 XTL1-BCLKIN-I/O H1 A14-l/0 C10 VO N12 vO H2 A5-1/0 B11 VO P12 /O H3 GND A12 /O* Nit D6-I/O G3 Vcc B12 0 M10 VO G2 A13-1/0 A13 O* P11 /O* G1 A6-I/0 C12 VO N10 VO F1 O* B13 M1RDATA P10 VO F2 A12-1/0 C11 GND M9 D5-I/0 Et A7VO Al4 MO-RTRIG NQ CS0-/0 F3 vO Di2 VCC Pg O* E2 V0 C13 M2-I/O Pg /O* D1 A11-I/O Bi4 HDC-1/O N8 D4-0 D2 A8-/O C14 0 P7 VO E3 vO E12 ie) M8 VCC C1 ie D13 vO M7 GND B1 A10-I/O D14 LDC-1/0 N7 D3-1/O C2 A9-1/0 E13 VO* P6 CS1-l/0 D3 Vcc * Indicates unconnected package pins for the ATT3030. Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-limited. DAn5 losrant Tarhnatanniac IneFPGA Data Book ATT3000 Series FPGAs Pin Assignments (continued) Table 13. ATT3042 and ATT3064 144-TQFP Pinout rorP Function tarp Function torP Function rorP Function 1 PWRDWN 37 GND 73 DONEPROG 109 Voc 2 TCLKINI/O 38 MORTRIG 74 D7-1/0 110 GND 3 /O* 39 Vcc 75 XTL1-BCLKIN-I/O 111 AO-WS-I/O 4 V/O 40 M2-1/O 76 /0 112 A1-CS2-/O 5 /O 41 HDC-I/O 77 VO 113 VO 6 V/O* 42 VO 78 D6-1/0 114 VO 7 He) 43 /O 79 VO 115 A2-V/O 8 VO 44 /O 80 (/O* 116 A3-1/0 9 /O* 45 Ldcl/O 81 /O 117 Ke) - 10 VO 46 /0* 82 VO 118 /O VO 47 VO 83 1/O* 119 A15-W/O0 i 12 VO 48 /O 84 D51/O 120 A4-I/O | 13 VO 49 VO 85 CS0-I/O 121 /O* 14 /O 50 /O* 86 1/O* 122 /0* 15 V/O* 51 /O 87 /O* 123 A14-/0 16 vO 52 /O 88 D4-I/O 124 A5-V/O |_17 /0 53 INIT1/O 89 VO 125 ; 18 GND 54 Vcc 90 Vcc 126 GND ' 19 Vcc 55 GND 91 GND 127 Voc a) VO 56 VO 92 D3I/O 128 A13-V/0 i VO 57 /O 93 CcSiV/O 129 A6-V/O 22 V/O 58 /O 94 /O* 130 V/O* 23 /O 59 vO 95 /O* 131 24 /O 60 VO 96 D2V/O 132 V/O* 25 VO 61 /O 97 vO 133 A12-l/O 26 /0 62 0 98 VO 134 A7-l/0 27 V/O 63 /O* 99 /O* 135 VO 28 /O* 64 /O* 100 VO 136 /O 29 vO 65 VO 101 VO* 137 A1i1-I/O 30 /O 66 vO 102 DiV/O 138 A8-l/O 31 V/O* 67 VO 103 | RCLKBUSY/RDY1/O|| 139 VO 32 /O* 68 vO 104 /0 140 /O 33 /O 69 XTL2VO 105 vO 141 A10-I/O 34 /O* 70 GND 106 DODINI/O 142 A9-V/0 35 0 71 RESET 107 DOUT-I/O 143 Vcc 36 M1RDATA 72 Vcc 108 CCLK 144 GND * Indicates unconnected package pins for the ATT3042. Note: Unprogrammed !OBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-limited. l rant Tarhnolaciac inc 2-339ATT3000 Series FPGAs FPGA Data Bc Pin Assignments (continued) Table 14. ATT3064 and ATT3090 160-MQFP Pinout uo ep Function Mo ep Function MorP Function wo - Function 1 1/0" 44 GND B1 D7-/O 121 CCLK V/O* . 42 MORTRIG 82 XTL1-BCLKINI/O || 122 Vcc 3 (/O* 43 Vcc 83 /O* 123 GND 4 VO 44 M2-I/O 84 /O 124 A0-WS-I/O 5 iO 45 HDC-1/0 85 VO 125 A1-CS2-1/0 /O 46 VO 86 D6/O 126 V/O 7 He) 47 VO 87 VO 127 VO 8 0 48 VO 88 vO 128 A21/O 9 vO 49 CDc-V/O 89 VO 129 A3-1/0 10 vO 50 /O* 90 VO 130 VO 11 VO 51 /O* 91 iO 131 VO 12 VO 52 V/O 92 D5-/O 132 A15-1/0 13 V/O 53 VO 93 CSO0- 1/0 133 A4-|/O 14 /O 54 ie) 94 i/O* 134 VO 15 /O 55 /O 95 /O* 135 V/O 16 VO 56 vO 96 /O 136 A14-I/0 17 VO 57 /O 97 VO 137 A5-I/0 18 VO 58 /O 98 D4-1/0 138 /0* 19 GND 59 INTT I/O 99 vO 139 GND 20 Voc 60 Vcc 100 Voc 140 Vcc 21 V/O* 61 GND 101 GND 141 A13-1/O 22 /O 62 /O 102 D3-I/O 142 A6-V/O 23 V/O 63 VO 103 cst-V/O 143 /O* 24 VO 64 VO 104 vO 144 /O* 25 V/O 65 VO 105 /O 145 VO 26 vO 66 0 106 /O* 146 V/O 27 V/O 67 0 107 /O* 147 A12-1/0 28 . YO 68 ie) 108 D2-/0 148 A7-I/O 29 VO 69 /O 109 VO 149 VO 30 /O 70 vO 110 vO 150 V/O 31 /O 71 vO 111 /O 151 Ai1-I/O 32 /O 72 VO 112 V/O 152 A8-I/O 33 vO 73 VO 113 vO 153 /O 34 VO 74 VO 114 D1-1/0 154 VO 35 VO 75 VO* 115 |RCLK-RDY/BUSY-1/O}| 155 A10-I/O 36 /O 76 XTL21/O 116 /O 156 A9-1/0 37 VO 77 GND 117 vO 157 Vcc 38 /O* 78 RESET 118 VO* 158 GND 39 /O* 79 Vcc 119 DO-DIN-/O 159 PWRDWN 40 M1RDATA 80 DONE PROG 120 DOUT-I/O 160 TCLKIN-I/O * Indicates unconnected package pins for the ATT3064. Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused !OBs. Programmed outpu' are default slew-limited. 9.2AN fparant Toarhnalagqinae4 PGA Data Book ATT3000 Series FPGAs in Assignments (continued) able 15. ATT3000 Family 175-PPGA Pinout POA Function mPOA Function opGA Function open Function B2 PWRDWN D13 /O R14 DONE-PROG R3 DO-DIN-I/O D4 | TCLKIN-I/O |} B14 M1--RDATA N13 D7-1/0 N4 DOUT-I/O B3 /O C14 GND T14 XTL1-BCLKIN-I/O R2 CCLK C4 ie) B15 MORTRIG P13 VO P3 Vcc B4 VO D14 Vcc R13 VO N3 GND A4 /O C15 M2-W/0 713 /0 P2 A0-WS-|/O D5 VO E14 HDC-I/O N12 /O M3 A1-CS2-l/0 C5 VO B1i6 vO P12 D-I/O R11 VO B5 VO D15 VO R12 vO N2 ie) A5 VO C16 VO T12 /0 P1 A2-V/O C6 VO D16 LDC-/O P14 vO Nd A3-l/O D6 /O F14 /O N41 VO L3 /O B6 VO E15 VO R11 VO M2 Ke) A6 ie) F16 VO Tt D5-1/O M1 A15-V/O B7 /O Fi5 VO R10 CcSo-H/O L2 A4-1/0 C7 /O F16 VO P10 YO Lt VO D7 /O G14 /0 N10 V/O K3 YO A7 VO G15 V/O T10 0 K2 A14-1/0 A8 ie) G16 VO T9 vO K1 A5-/0 B8 VO H16 vO R9 D4-I/0 J1 VO C8 /O H15 INIT-1/O Pg VO J2 /O D8 GND H14 VCC N9 Voc J3 GND D9 Vcc J14 GND N8 GND H3 Vcc cg VO J15 /O P8 D3-1/0 H2 A13-l/O B9 VO J16 VO R8 cs1-l/O H1 A6-I/O AY VO K16 /O T8 /O G1 VO A10 VO K15 VO T7 VO G2 V/O D10 VO K14 VO N7 VO G3 VO C10 VO L16 vO P7 VO F1 /O Bi0 /0 L15 /O R7 D2-/0 F2 At2-1/0 Alt VO M16 vO T6 /O E1 A7-/0 B11 VO M15 VO R6 VO E2 VO D11 VO L14 Ke) N6 /O F3 VO C11 vO N16 VO P6 /O D1 A11i-1/0 Al2 VO P16 VO T5 V/O C1 A8-I/O B12 VO N15 VO R5 Di-V/O D2 VO C12 VO R16 vO P5 | RDY/BUSY-RCLK-I/O || Bi /O D12 VO M14 /0 N5 vO E3 A10-1/0 A13 VO P15 XTL2-I/0 T4 /O C2 AQ-1/0 B13 VO N14 GND R4 vO D3 Vcc C13 /O R15 RESET P4 | /O C3 GND A14 /O P14 Vcc Vote: Unprogrammed |OBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-limited. Pins A2, A3, A15, A16, 71, 72, T3, T15, and T16 are not connected. Pin Al does not exist. rrant Tacknningiac Inco 2-341yA? | ATT3000 Series FPGAs FPGA Data Book Pin Assignments (continued) Table 16. ATT3000 Family 208-SQFP Pinout . 208 208 208 208 SQFP! Function ||SQFP Function SQFP Function SQFP Function 1 53 105 _ 157 2 GND 54 106 VCC 158 3 PWRDWN 55 VCC 107 DONE -PROG 159 4 TCLKIN-I/O 56 M2-1/0 108 160 GND 5 vO 57 HDC-1/O 109 D7-/O 161 AO-WS-I/O 6 V0 58 VO 110 XTL1-BCLKINI/O 162 Ai-CS2-1/0 7 /0 59 vO 111 vO 163 vO 8 0 60 /O 112 /0 164 /O 9 i/0 61 LDC -I/0 113 VO 165 A2-VO 10 VO 62 VO 114 vO 166 A3-V/O 11 vO 63 VO 115 D6-/0 167 vO 12 vO 64 116 0 168 VO 13 vO 65 117 VO 169 14 vO 66 118 /0 170 15 vO 67 119 171 16 VO 68 vO 120 VO 172 A15-/0 17 /O 69 vO 121 /0 173 A4-VO 18 VO 70 VO 422 D5-I/0 174 VO 19 vO 71 vO 123 CS0-1/0 175 VO 20 vO 72 124 vO 176 21 /0 73 125 /O 177 22 VO 74 vO 126 vO 178 Ai4-V/O 23 0 75 vO 127 VO 179 A5-V/O 24 0 76 VO 128 D4-/0 180 vO 25 GND 77 INIT-1/O 129 vO 181 vO 26 Wee 78 Vcc 130 VCC 182 GND 27 V/O 79 GND 131 GND 183 vec 28 VO 80 VO 132 D3-/0 184 A13-1/0 29 VO 81 VO 133 CS1-/0 185 A6-1/0 30 vO 82 vO 134 /O 186 /O 31 VO 83 135 i/0 187 /O 32 vO 84 136 /0 188 33 vO 85 vO 137 vO - 189 34 vO 86 VO 138 D2-/0 190 vO 35 VO 87 vO 139 VO 194 VO 36 VO 88 VO 140 vO 192 A12-/0 37 89 VO 144 /O 193 A7-V/O 38 VO 90 142 194 39 vO 91 143 VO 195 40 /O 92 144 VO 196 41 /O 93 VO 145 D1-V/O 197 vO 42 0 94 vO 146 | RDY/BUSY-RCLK-I/O || 198 vO 43 0 95 vO 147 vO 199 A11-1/0 44 VO 96 vO 148 VO 200 A81/0 45 VO 97 vO 149 vO 201 vO 46 /O 98 VO 150 vO 202 vO 47 VO 99 vO 151 DO-DIN-I/O 203 A10-1/0 48 M1RDATA 100 XTL2-V/O 152 DOUT-I/O 204 A9-V/O 49 GND 101 GND 153 CCLK 205 Vcc 50 MO-RTRIG 102 RESET 154 VCC 206 51 103 _ 155 = 207 52 104 156 208 Note: Unprogrammed IOBs have a default pull-up; this prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are default slew-limited. 9-RAD lL eirnant Tarhknninniac Ine4 FPGA Data Book ATT3000 Series FPGAs Package Thermal Characteristics When silicon die junction temperature is below the rec- ommended junction temperature of 125 C, the temperature-activated failure mechanisms are mini- mized. There are four major factors that affect the ther- mal resistance value: silicon device size/paddle size, board mounting configuration (board density, multilayer nature of board), package type and size, and system airflow over the package. The values in the table below reflect the capability of the various package types to dissipate heat at given airflow rates. The numbers rep- resent the delta C/W between the ambient tempera- ture and the device junction temperature. To test package thermal characteristics, a single pack- age containing a 0.269 in. sq. test IC of each configura- tion is mounted at the center of a printed-circuit board (PCB) measuring 8 in. x 13 in. x 0.062 in. The assem- bled PCB is mounted vertically in the center of the rect- angular test section of a wind tunnel. The walls of the wind tunnel simulate adjacent boards in the electronic rack and can be adjusted to study the effects of PCB spacing. Forced air at room temperature is supplied by a pair of push-pull blowers which can be regulated to supply the desired air velocities. The air velocity is measured with a hot-wire anemometer at the center of the channel, 3 in. upstream from the package. A typical test consists of regulating the wind tunnel blowers to obtain the desired air velocity and applying power to the test IC. The power to the IC is adjusted until the maximum junction temperature (as measured by its diodes) reaches 115 C to 120 C. The thermal resistance Qua (C/W) is computed by using the power supplied to the IC, junction temperature, ambient tem- perature, and air velocity: ltirent Technologies Inc. TJ-TA QJA = Qc where: Tu = peak temperature on the active surface of the IC TA = ambient air temperature Qc = IC power The tests are repeated at several velocities from 0 fpm (feet per minute) to 1000 fpm. The definition of the junction to case thermal resistance Quc is: Tu-Te OJC = Oc where: Tc = temperature measured to the thermocouple at the top dead center of the package The actual @sc measurement performed at Lucent, OJ-ToC, uses a different package mounting arrange- ment than the one defined for Ouc in MIL-STD-883D and SEMI standards. Please contact Lucent for a dia- gram. The maximum power dissipation for a package is cal- culated from the maximum junction temperature, maxi- mum operating temperature, and the junction to ambient characteristic Qua. The maximum power dissi- pation for commercial grade ICs is calculated as fol- lows: max power (watts) = (125 C ~ 70 C) x (1/ua), where 125 C is the maximum junction temperature. Table 17 lists the ATT3000 plastic package thermal characteristics. 2-343ATT3000 Series FPGAs i, 4 FPGA Data Bool Package Thermal Characteristics (continued) Table 17. ATT3000 Plastic Package Thermal Characteristics Package Oya (C) Quc Max Power Ofpm | 200fpm! 400fpm| (C/W) (70 C0 fpm) 44-Pin PLCC 49 41 40 _ 1.12W 68-Pin PLCC 43 38 35 4 1.28 W 84-Pin PLCC 40 35 32 9 1.38 W 100-Pin MQFP 81 67 64 im 0.68 W 100-Pin TQFP 61 49 46 6 0.90 W 132-Pin PPGA 22 18 16 _ 2.50 W 144-Pin TQFP 52 39 36 4 1.06 W 160-Pin MQFP 40 36 32 8 1.38 W 175-Pin PPGA 23 20 17 _ 2.39 W 208-Pin SQFP 37 33 29 8 1.49W Package Coplanarity bounce noise and inductive crosstalk noise. Three The coplanarity of Lucent Technologies postmolded packages is 4 mils. The coplanarity of selected pack- ages is scheduled to be reduced to 3.1 mils. All Lucent ATT3000 Series FPGA ceramic packages are through- hole mount. Package Parasitics The electrical performance of an IC package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. Table 18 lists eight parasitics associated with the ATT3000 packages. These parasit- ics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. Four inductances in nH are listed: Lw and LL, the self- inductance of the lead; and Law and LML, the mutual inductance to the nearest neighbor lead. These parameters are important in determining ground 2-344 capacitances in pF are listed: Cm, the mutual capaci- tance of the lead to the nearest neighbor lead; and C1 and C2, the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). These parameters are important in determining capaci- tive crosstalk and the capacitive loading effect of the lead. The parasitic values in Table 18 are for the circuit madel of bond wire and package lead parasitics. If the mutual capacitance value is not used in the designer's model, then the value listed as mutual capacitance should be added to each of the C1 and C2 capacitors. The PGAs contain power and ground planes that will make the inductance value for power and ground leads the minimum value listed. The PGAs also have a signif- icant range of parasitic values. This is due to the large variation in internal trace lengths and is also due to two signal metal layers that are separated from the ground plane by different distances. The upper signal layer is more inductive but less capacitive than the closer, lower signal layer. Lucent Technologies Inc.FPGA Data Book ATT3000 Series FPGAs Package Parasitics (continued) Table 18. Package Parasitics Package Type Lw Mw Rw Ci C2 CM LL ML 44-Pin PLCC 3 1 140 05 05 0.3 56 | 225 68-Pin PLCC 3 1 140 05 0.5 0.4 69 34 84-Pin PLCC 3 1 140 1 1 05 711 | 3-6 100-Pin MFP 3 1 160 1 1 05 79 | 4-5 100-Pin TOQFP 3 1 150 05 05 0.4 46 23 132-Pin PPGA 3 1 150 1 1 025 | 4-10 | 051 144-Pin TOFP 3 1 140 1 1 0.6 4-6 | 2-25 160-Pin MOFP 4 15 180 15 15 1 10-13 | 6-8 175-Pin PPGA 3 1 150 1 1 0.3 511 | 1-15 208-Pin SQFP 4 2 200 { 1 i 710 | 4-6 * Leads designated as ground (power) can be connected to the ground plane, reducing the trace inductance to the minimum value listed. CIRCUIT Lw Rw LL BOARD PAD PAD N PADN +1 5-3862(C)} Figure 33. Package Parasitics Lucent Technologies Inc. 2-345ATT3000 Series FPGAs FPGA Data Book Absolute Maximum Ratings Stresses in excess of the Absolute Maximum Ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to Absolute Maximum Ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Supply Voltage Relative to GND Vcc -0.5 7.0 V Input Voltage Relative to GND VIN 0.5 0.5 V Voltage Applied to 3-state Output VTS -0.5 0.5 V Storage Temperature (ambient) Tstg -65 150 C Maximum Soldering Temperature TSOL 260 C (10 seconds at 1/16 in.) Junction Temperature TU _ 125 C 2-346 l uaceeant Tachnoloniec Incra 4 FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics Table 19. dc Electrical Characteristics Over Operating Conditions Commercial: Vcc = 5.0V+5%:0C <Ta<70 C; Industrial: Vcc = 5.0 + 10%, -40 C < Ta < +85 C. -50, -70, -100, -125, and 3-4 and -5 Parameter/Conditions Symbol 7150 MHz Vo Unit Min Max Min Max High-level Input Voltage CMOS Level VIHC 70% 100% 70% 100% V TTL Level VIHT 2.0 Vcc 2.0 Vcc Vv Low-level input Voltage CMOS Level VILC 0 20% 0 20% V TTL Level VILT 0 0.8 ) 0.8 V Output Voltage High (IOH = -4 mA) VOH 3.86 _ V (IOH = -8 mA) VOH 3.86 ~ V Low (lOL = 4 mA) VOL 0.40 _ V (IOL = 8 mA) VOL _ 0.40 V Input Signal Transition Time TIN 250 _ 250 ns Powerdown Supply Current ICCPD ATT3020 _ 50 50 LA ATT3030 80 _ 80 LA ATT3042 120 120 pA ATT3064 170 170 LA ATT3090 250 250 LA Quiescent FPGA Supply Current Icco (in addition to ICCPD) CMOS Inputs _ 10 mA ATT3020 500 LA ATT3030 500 LA ATT3042 500 pA ATT3064 500 LA ATT3090 500 pA TTL Inputs 10 20 mA Leakage Current lik -10 10 ~10 10 LA Input Capacitance CIN All Packages Except 175-PGA: All Pins Except XTL1/XTL2 _ 10 10 pF XTL1 and XTL2 _ 15 15 pF 175-PGA Package: All Pins Except XTL1/XTL2 15 15 pF XTL1 and XTL2 20 20 pF Pad Pull-up* (when selected) IRIN (at VIN = OV) 0.02 0.17 0.02 0.17 mA Horizontal Long Line Pull-up (when ALL selected) at Logic LOW 0.2 25 0.2 2.8 mA * Sample tested. Note: With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a MAKEBITS tie option. See FPGA power chart for additional activity-dependent operating components. AA? Liuiceant Technningniac Inex4 ATT3000 Series FPGAs FPGA Data Book Electrical Characteristics (continued) Table 20. CLB Switching Characteristics (-50, -70, -100, -125, and -150) Commercial: Vec = 5.0 V+5%:0 C <Ta<70 C; Industrial: Voc = 5.0 + 10%, 40 C < Ta < +85 C. -50 -70 -100 125 -150 Description Symbol Units Min | Max | Min | Max | Min | Max | Min Max | Min | Max Combinatorial Delay 1]; TLO | | 140] | go> Trvof 5.5 | | 46] ns Sequential Delay Clock K to Outputs x or y 8; TCKO | 1120) ~ | 60} | 59] 45] | 401] ns Clock K to Outputs x or y when Q | Talo | | 23.0} 1130] ~ |190/ 8.0; | 6.7] ns Returned Through Function Generators F or G to Drives x or y Setup Time Logic Variables 2} TICK |120} |80/ } 70] ~/] 55] 46 | | ns Data In 4; TDICK| 80} |} 50} | 40] 3.0; | 20] | ns Enable Clock 6 | TECCK} 10.0] | 70/{}50/]45] 40! | ns Reset Direct Active |TROCK; 10; |} 10) ~ |} 10! ]10] 10); { ns Hold Time Logic Variables 3} TcK 1 10; !} 0} } of} ~]} go J Oo | | ns Data In 5; TCKDI} 60} |} 40} |] 20; ~]J4i5] 12); |] ns Enable Clock 7 |TCKEC] O Oo}; 0 _ 0 _ 0 | ns Clock High Time* 11) TCH | 90} ;50/ ]40/}/ 1] 30] 2.5 | | ns Low Time* 12; TcL | 9.0} /|50/ 1/40] 3.0; ~ | 251 |] ns Flip-flop Toggle Rate* ~| FetkK | 50 | ~ | 70 |} | 100] | 425) 150 | | MHz Reset Direct (rd) rd Width 13) TRPW /} 12.0; | 80] |70]/ |] 60/ 5.0 | | ns Delay from rd to Outputs x, y 9} TRIO | |120; / 80] i 70] 6.0 | | 5.0] ns Master Reset (MR) MR Width | TMRW] 30 | | 25 | | 21] | a9 | 19 | | ns Delay from MR to Outputs x, y | TMRQ| | 27} ~ | 23 | ~ | ig | 17 |} | 17 ns * These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%. Note: The CLKB K to Q output delay (TCKO#8) of any CLB, plus the shortest possible interconnect delay, is always longer than the data in hold time requirement (T: CKDI#5) of any CLB on the same die. 2.242FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics (continued) Table 21. CLB Switching Characteristics (-3, -4, and -5) Commercial: Vcc = 5.0 V + 5%; 0 C < Ta < 70 C; Industrial: Vcc = 5.0 + 10%, 40 C < Ta < +85 C. Description Symbol 3 Units Min Max Min Max Min Max Combinatorial Delay | TILO 41 _ 3.3 2.7 ns | Sequential Delay Clock K to Outputs x or y 8 TCKO 3.1 _ 2.9 2.4 ns Clock K to Outputs x or y when Q Returned | | TQLo _ 6.3 _ 5.2 43 ns Through Function Generators F or G to Drives x or y Setup Time Logic Variables 2 TICK 3.1 _ 2.5 _ 2.1 _ ns Data In 4 TDICK 2.0 _ 1.6 1.4 _ ns Enabie Clock 6 | TECCK 3.8 _ 3.2 2.7 _ ns Reset Direct Active | TRDCK 1.0 1.0 1.0 ns Hold Time Logic Variables 3 TCKI 0 0 _ 0 _ ns Data In 5 TCKDI 1.2 1.0 _ 0.9 ns Enable Clock 7 | TCKEC 1.0 _ 0.8 0.7 ns Clock High Time* 11 TCH 2.4 2.0 _ 1.6 ns Low Time* 12 TCL 2.4 2.0 1.6 _ ns Flip-flop Toggle Rate* FCLK 190 _ 230 270 _ MHz Reset Direct (rd) rd Width 13} TRPW 3.8 3.2 2.7 _ ns Delay from rd to Outputs x, y 9 TRIO 4.4 _ 3.7 _ 3.1 ns Master Reset (MR) MR Width | TMRW 18.0 _ 15.0 _ 13.0 ns Delay from MR to Outputs x, y | TMRQ 17.0 14.0 12.0 ns * These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%. Note: The CLKB K to Q output delay (TCKO#8) of any CLB, plus the shortest possible interconnect delay, is always longer than the data in hold time requirement (TCKDI#5) of any CLB on the same die. Lucent Technologies Inc. 2-349ATT3000 Series FPGAs FPGA Data Book Electrical Characteristics (continued) CLB OUTPUT (X,Y) (COMBINATORIAL) + (1) Tio CLB INPUT (A, B, C, D, E) CLB CLOCK / j G2)Te ToH (4)To1ck }4___ (5) Tcxor CLB INPUT (DIRECT IN) @Teccx+l. @Texec = CLB INPUT (ENABLE CLOCK) | ) Texo CLB OUTPUT (FLIP-FLOP) CLB INPUT (RESET DIRECT) CLB OUTPUT (FLIP-FLOP) -3124(F) Figure 34. CLB Switching Characteristics 9-207a 4 FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics (continued) Table 22. {OB Switching Characteristics (-50, -70, -100, -1 25, and -150) Commercial: Vcc = 5.0 V + 5%; 0 C < Ta < 70 C: Industrial: Vec = 5.0 + 10%, -40 C < Ta $ +85 C. -50 -70 -100 -125 -150 Description Symbol Units Min | Max | Min | Max | Min | Max | Min | Max | Min Max Input Delays | Pad to Direct In 3] TPID 9.0 _ 6.0 _ 4.0 _ 3.0 _ 2.8 ns Pad to Registered In | TPTG {| 94.0) | 210} | 170}; | 160] | 15.0] ns Clock to Registered In 4] TIKRI | 110) 5.5 4.0 3.0 2.8 | ns Setup Time (Input): Clock Setup Time 1 | TPICK | 300; | 200} | 170] | 160} | 145] ns Output Delays Clock to Pad Fast 7} TOKPO; | 180/ | 130); | 100} ~ 9.0 7.0 ns Slew-rate Limited 7 | TOKPO | | 43.0} / 33.0 | 270) | 240} | 220] ns Output to Pad Fast 10} TOPF | 15.0} 9.0 _ 6.0 _ 5.0 _ 4.5 ns Slew-rate Limited 10; TOPS | 400; | 290; | 230} | 200] | 15.01 ns 3-state to Pad Hi-Z Fast 9} TTSHZ | | 100) 8.0 8.0 7.0 7.0 ns Slew-rate Limited 9] TTSHZ | 37.0} | 280; | 250} | 240} | 220] ns 3-state to Pad Valid Fast 8) TTSON; | 200} | 140} | 120] | 11.0] | i101] ns Slew-rate Limited 8 | TTSON| | 450; | 340) | 290] | 270] ~ |} 2601! ns Setup and Hold Times (output) Clock Setup Time 5} TOCK | 150; | 100} 9.0 8.0 _ 7.0 ns Clock Hold Time 6 | TOKO 0 _ 0 0 _ 0 0 ns Clock High Time* 11) TCH 9.0 _ 5.0 _ 4.0 _ 3.0 _ 2.5 _ ns Low Time* 12] TCL 9.0 _ 5.0 4.0 _ 3.0 2.5 ns Max. Flip-flop Toggle | FCLK 50 _ 70 _ 100 125 _ 150 | MHz Master Reset Delays RESET to: Registered In 13] TRRI _ 35 25 _ 24 23 20 ns Output Pad (fast) 15} TRPO 50 35 _ 33 29 25 ns Output Pad (slew- 15|} TRPO 68 _ 53 45 42 40 ns rate limited) "These parameters are for clock pulses within an FPGA device. For externally applied clock, increase values by 20%. Notes: Timing is measured at pin threshold with 50 pF external capacitive loads (including test fixture). Typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pF of additional load. Typical slew-rate limited output rise/fall times are approximately 4 times longer. A maximum total external capacitive load for simultaneous fast mode switching in the same direction is 200 pF per power/ground pin pair. For slew-rate limited outputs, this total is 4 times larger. Exceeding this maximum capacitive load can result in ground bounce of >1.5 V amplitude and < ns duration, which may cause problems when the [CA drives clocks and other asynchronous signals. Voltage levels of unused (bonded and unbonded) pads must be valid lagic levels. Each can be configured with the internal pull-up resistor ar alternatively configured as a driven output or driven from an external source. Input pad setup time is specified with respect to the internal clock (ik). To calculate system setup time, subtract clock delay (pad to ik) from the input pad setup time value. Input pad hald time with respect to the internal clock (ik) is negative. This means that pad levels changed immediately before the internal clock edge (ik) will not be recagnized. Lucent Technologies Inc. 9.351ATT3000 Series FPGAs FPGA Data Bo Electrical Characteristics (continued) Table 23. 10B Switching Characteristics (-3, -4, and -5) Commercial: Vcc = 5.0 V + 5%; 0 C < Ta < 70 C; Industrial: Vcc = 5.0 + 10%, 40C < Tas +85 C. 5 4 -3 Description Symbol Units Min Max Min Max Min Max Input Delays Pad to Direct In 3 TPID 2.8 _ 2.5 _ 2.2 ns Pad to Registered In _ TPTG _ 16.0 _ 15.0 13.0 ns Clock to Registered In 4 TIKRI 2.8 _ 2.5 2.2 ns Setup Time (Input): Clock Setup Time 1 TPICK 15.0 14.0 12.0 _ ns Output Delays Clock to Pad Fast 7 TOKPO 5.5 _ 5.0 4.4 ns Slew-rate Limited 7 TOKPO 14.0 _ 12.0 10.0 ns Output to Pad Fast 10 TOPF 4.1 3.7 3.3 ns Slew-rate Limited 10 TOPS 13.0 11.0 9.0 ns 3-state to Pad Hi-Z Fast 9 TTSHZ 6.9 _ 6.2 5.5 ns Slew-rate Limited 9 TTSHZ 21.0 _ 19.0 17.0 ns 3-state to Pad Valid Fast 8 TTSON _ 12.0 _ 10.0 _ 9.0 ns Slew-rate Limited 8 TTSON 20.0 17.0 15.0 ns Setup and Hold Times (output) Clock Setup Time 5 TOCK 6.2 5.6 _ 5.0 ns Clock Hold Time 6 TOKO 0 0 0 ns Clock High Time* 11 TIOH 2.4 2.0 1.6 ns Low Time* 12 TCL 2.4 2.0 1.6 ns Max. Flip-flop Toggle* _ FCLK 190 230 270 MHz Master Reset Delays RESET to: Registered In 13 TARI 18 _ 15 13 ns Output Pad (fast) 15 TRPO 24 _ 20 _ 17 ns Output Pad (slew- 15 TRPO _ 32 27 _ 23 ns rate limited) * These parameters are for Clock pulses within an FPGA device. For externally applied clock, increase values by 20%, Notes: Timing is measured at pin threshold with 50 pF external capacitive loads (including test fixture). Typical fast mode output rise/fall times are 2 ns and will increase approximately 2%/pF of additional load. Typical slew-rate limited output rise/fall times are approximately 4 times longer. A maximum total external Capacitive load for simultaneous fast mode Switching in the same direction is 200 pF per Power/ground pin pair. Fo: and <5 ns duration, which may Cause problems when the LCA drives clocks and other asynchronous signals. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven Output or driven from an external source, Input pad Setup time is specified with respect to the internal clock (ik). To calculate System setup time, subtract clock delay (pad to ik) from the input pad setup time value. Input pad hold time with respect to the inte nal clock (ik) is negative. This means that pad levels changed immediately before the internal clock edge (ik) will not be recognized. 2-352FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics (continued) VO BLOCK (I) A (3)Teo VO PAD INPUT (4) Trick rL @Tikes VO CLOCK (IK/OK} GATiow + ()Tion VO BLOCK (RI) A 1 + @ Tika ) TPRI RESET l | om | /O BLOCK (0) (10)Tor | | VO PAD OUTPUT (DIRECT) | @)TokPo (0 PAD OUTPUT (REGISTERED) VO PAD TS TTSON TrsHz J VO PAD OUTPUT 5-3126(F) Figure 35. OB Switching Characteristics Lucent Technologies inc. 9.964ATT3000 Series FPGAs | Electrical Characteristics (continued) Table 24. Buffer (Internal) Switching Characteristics FPGA Data Book Commercial: Vcc = 5.0V+5%:0C <Ta<70 C; Industrial: Vcc = 5.0 + 10%, -40 C < Ta < +85 C. -50 | -70 | -100} -125/) -150/ -5 4 +3 Description Symbol Unit Max | Max | Max} Max! Max} Max | Max Max Global and Alternate Clock Distribution: Either Normal IOB Input Pad to Trio | 10.0} 8.0} 7.5] 7.0; 68) 68 6.5} 5.6] ns Clock Buffer Input Or Fast (CMOS only) Input Pad to TPipc 8.0; 65) 6.0) 5.7) 55} 5.4) 54 4.3) ns Clock Buffer Input TBUF Driving a Horizontal Long Line (LL)*: | to LL While T Is Low (buffer active) Tio 8.0} 5.0) 4.7| 45) 4411 44) 3.71 3.4] ns TJ to LL Active and Valid with Ton | 12.0; 11.0} 10.0] 9.0} 56! 56! 50] 4.2] ns Single Pull-up Resistor TL to LL Active and Valid with Ton 14.0; 12.0) 11.0] 10.0) 7.4] 7.4 6.5; 5.7] ns Pair of Pull-up Resistors TT to LL High with Single Pull-up Tpus | 42.0) 24.0] 22.0) 17.0] 15.6} 15.6) 13.5! 11.4 ns Resistor TT to LL High with Pair of Pull-up Tpur | 22.0] 17.0] 15.0] 12.0 12.0! 12.0] 105 8.8) ns Resistors Bidirectional Buffer Delay TBIDI 6.0) 2.0) 1.8) 1.7| 1.4] 1.4) 1.2) 1.00 ns * Timing is based on the ATT3042; for other devices, see timing calculator. 2-3542 4 FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics (continued) (4)Twaw CC RESET ~ (2)Tr @)TAm MO/M1/M2 eo VALID }+ (6) Tew DONE/PROG | (Trai INIT USER STATE CLEAR STATE / CONFIGURE (OUTPUT) <5 PWRDWN \ / je See > Voc (VALID) Vs 5-3124(6) * At powerup, VCC must rise from 2 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by halding RESET low until VCC has reached 4V,A very long VCC rise time of >100 ms ora nonmonotonically rising VCC may require a >1 tts high level on RESET, followed by a >6 LS low level on RESET and DONE/PAOG after VCC has reached 4 V. Figure 36. General FPGA Switching Characteristics Testing of the switching characteristics is modeled after testing specified by MIL-M-38510/605. Devices are 100% functionally tested. Actual worst-case timing is provided by the timing calculator or simulation. Table 25. General FPGA Switching Characteristics Signal Description Symbol Min Max Unit RESET MO, M1, and M2 Setup Time TMR (2) 1 us MO, M1, and M2 Hold Time TRM (3) 1 us RESET Width (LOW) Required for Abort TMAW (4) 6 Ls DONE/PROG | Width Low Required for Reconfiguration TPaw (5) 6 us INIT Response after DONE/PROG Is Pulled Low TPai (6) 7 Ls Vect Powerdown Vcc (commercial/industrial) VCCPD 2.3 _ V * REET timing relative to valid mode lines (MO, M1, M2) is relevant when AESET is used to delay configuration. t PWROWN transitions must occur while VCC > 4 Vv. Lucent Technologies Inc.rad x ATT3000 Series FPGAs FPGA Data Book Electrical Characteristics (continueg) CCLK (OUTPUT) TcKps }+ (1) Toscx | SERIAL DATA IN LX SERIAL DOUT (OUTPUT) Figure 37. Master Serial Mode Switching Characteristics 5-3127(F) Table 26. Master Serial Mode Switching Characteristics Signal Description Symbol Min Max Unit CCLK Data-In Setup 1 TDSCK 60 _ ns Data-In Hold 2 TCKDS 0 ns Notes: At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET low until VCC has reached 4.0 V.A very long VCC rise time of >100 ms, ora nonmonotonically rising VCC may require a >1 ps high level on RESET, followed by >6 us low level on RESET and D/P after VCC has reached 4.0 V. Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high. Master serial mode timing is based on slave mode testing. 2-356FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics (continued) A[15:0} xX ADDRESS FOR BYTE N ADDRESS FOR BYTE N +1 C Om 9 OOOOC omen (2) Tore w ~ Le (3) Taco RCLK (OUTPUT) j 7 CCLKs -14 __ ccLK CCLK (OUTPUT) DOUT (OUTPUT) . Xx D6 xX D7 BYTEN-1 5-3128(F) Note: The EPROM requirements in this timing diagram are extremely relaxed; EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements. Figure 38. Master Parallel Mode Switching Characteristics Table 27. Master Parallel Mode Switching Characteristics Signal Description Symbol Min Max Unit RCLK To Address Valid 1 TRAC 0 200 ns To Data Setup 2 TDRC 60 _ ns To Data Hold 3 TRCD 0 ns RCLK High _ TRCH 600 ns RCLK Low TRCL 4.0 us Notes: At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, or a nonmonotonically rising VCC may require a >1 js high level on RESET, followed by >6 1s low level on RESET and D/P atter VCC has reached 4.0 V. Configuration can be controlled by holding RESET low with or until after the INIT of all daisy-chain slave mode devices is high. Lucent Technologies Inc. 9.357ATT3000 Series FPGAs a FPGA Data Book Electrical Characteristics (continued) CS1/CS0 CS2 D[7:0] CCLK RDY/BUSY DOUT Note: The requirements in this timing diagram are extremel within 60 ns after the end of WS. BUSY will Stay activ _ ___/ GROUP OF 8 CCLKs XXX 5-3129(F} y relaxed; data need not be held beyond the rising edge of WS. BUSY will go active e for several microseconds. WS may be asserted immediately after the end of BUSY. Figure 39. Peripheral Mode Switching Characteristics Table 28. Peripheral Mode Programming Switching Characteristics Signal Description Symbol Min Max Unit Write Signal | Effective Write Time Required (CSO x CST x CS2 x WS) 1 TCA 100 ns D[7:0] DIN Setup Time Required 2 Toc 60 ns DIN Hold Time Required 3 TcD 0 ns RDY/BUSY RDY/BUSY Delay after End of WS 4 TWTRB ns Earliest Next WS after End of BUSY 5 TRBWT f) 60 ns BUSY Low Time Generated 6 TBUSY 2 9 CCLK L Periods Notes: At powerup, VCC must rise fram 2.0 V to VCC minimum in| low until VCC has reached 4.0 V. A very long VCC rise tim RESET, followed by >6 us low level on AESET and DF aft Configuration must be delayed until the INIT of all LCAs is high. Time from end of WS to CCLK cycle for the new internat timing generator for CCLK. CCLK and DOUT timing is tested in slave mode. 2-358 ess than 25 ms. ff this is not possible, configuration can be delayed by holding RESET e@ of >100 ms, ora nonmonotonically risin er VCC has reached 4.0 V. g VCC may require a >1 ws high level on byte of data depends on completion of-previous byte processing and the phase of thea 4 FPGA Data Book ATT3000 Series FPGAs Electrical Characteristics (continued) DIN BIT N BITN+4 () Tocce +++ 2) Teen ()Tect CCLK WA XN | ee NL (4)TccH be (3) Toco > DOUT (OUTPUT) BITN-1 BITN 5-3130(F) Figure 40. Slave Mode Switching Characteristics Table 29. Slave Mode Switching Characteristics Commercial: Vcc = 5.0 V + 5%; 0 C < Ta < 70 C: Industrial: Vec = 5.0 + 10%, 40 C < Ta < +85 C. Signal Description Symbol Min Max Unit CCLK To DOUT 3 Tcco 100 ns DIN Setup 1 Tocc 60 ns DIN Hold 2 Teco ) _ ns HIGH Time 4 TCCH 0.05 us LOW Time 5 TCCL 0.05 5.0 Us Frequency Fcc _ 10.0 MHz Notes: The maximum limit of CCLK LOW time is caused by dynamic circuitry inside the LCA device. Configuration must be delayed until the INIT of all LCAs is high. At powerup, VCC must rise from 2.0 V to VCC minimum in less than 25 ms. If this is not possible, configuration can be delayed by holding RESET low until VCC has reached 4.0 V. A very long VCC rise time of >100 ms, ora nonmonotonically rising VCC, may require a >1 us high level on RESET, followed by >6 us low level on RESET and D/P after Voc has reached 4.0 V. Lucent Technologies Inc. 9.256ATT3000 Series FPGAs FPGA Data Book Electrical Characteristics (continuea) DONE/PROG (QUTPUT) RTRIG (Mo) t \ =f @ Tecro RDATA (OUTPUT) VALID 5-3131(F) Figure 41. Program Readback Switching Characteristics Table 30. Program Readback Switching Characteristics Commercial: Vcc = 5.0 V+5%: 0 C < Ta < 70 C; Industrial: Vcc = 5.0 + 10%, 40C <Ta< +85 C, Signal _ Description Symbol Min Max Unit RTRIG RTRIG HIGH 1 TRTH 250 ns CCLK RTRIG Setup 2 TRTCC 200 ns RDATA Delay 3 TCCRD 100 ns HIGH Time 5 TCCH 0.05 _ us LOW Time 4 TCCL 0.05 5.0 us Notes: During readback, CCLK frequency may not exceed 1 MHz. RTRIG (MO positive transition) must not be done until after one clock following active I/O pins. Readback should not be initiated until after configuration is complete. 2-360FPGA Data Book ATT3000 Series FPGAs Ordering Information The ATT3000 Series includes standard and high-performance FPGAs. The part nomenclature uses two different suffixes for speed designation. The lower-speed ATT3000 Series devices use a flip-flop toggle rate (-50, -70, -100, -125, -150), which corresponds to XC3000 Series nomenclature. The ATT3000 Series High-Performance FPGAs use a suffix which is an approximation of the look-up table delay (-5, -4, and -3), which corresponds to XC3100 nomenclature. For burn-in diagrams and/or package assembly information call 1-800-EASY-FPG(A) or 1-800-327-9374. Example: ATT3020, 100 MHz, 68-Lead PLCC, Industrial Temperature ATT3020-100 M 6 8 | DEVICE __ | TYPE TOGGLE TEMPERATURE PACKAGE NUMBER OF TYPE PINS Example: ATT3020, 270 MHz, 68-Lead PLCC, Commercial Temperature ATT3020-3 M 68 DEVICE __] | P " * OGGLE TEMPERATURE RATE RANGE PACKAGE NUMBER OF TYPE PINS Note: For availability of device types or packaging options, please contact your Lucent Technologies Sales Representative or an authorized distributor. Table 31. FPGA Temperature Options Symbol Description Temperature (Blank) Commercial 0C to 70C | Industrial 40 C to +85 C Table 32. FPGA Package Options Symbol Description H Plastic Pin Grid Array J Metric Quad Flat Pack M Plastic Leaded Chip Carrier S Shrink Quad Fiat Pack T Thin Quad Flat Pack Lucent Technologies Inc. 9.961Series FPGAs FPGA Data Book | Information (continued) [T3000 Package Matrix 44-Pin Speed | PLCC 68-Pin PLCC M68 84-Pin PLCC M84 Ch 100-Pin 132-Pin | 144-P MQFP | TOFP | PPGA | TOFP J100 T100 H132 T7144 Choe Spe ee Cle 160-Pin MQFP J160 175-Pin | 208-Pin PPGA | SQFP H175 $208 Cl C C ercial, | = industrial,a4 microelectronics group Lucent Technologies Bell Labs Innovations ATT3000 Series Cross-Reference Guide Cross-Referencing ATT3000 Series FPGAs with Xilinx XC3000, XC3000A, XC3100, and XC3100A FPGAs Xilinx XC3000 and XC3100 The Lucent Technologies ATT3000 family is a direct second-source replacement for the Xilinx XC3000 family. The devices are 100% I/O and bitstream com- patible. In general, a Xilinx part number corresponds with an associated ATT3000 part number. However, certain identifiers in each part number vary in mean- ing. For example, identifiers AA, BBB, and DDD in Figure 1 represent the same values in both the Xilinx and Lucent parts. However, identifier CC (package type) in the Xilinx part number is related to identifier YY in the Lucent part number. Also, identifier E in the Xilinx part number relates to identifier Z in the Lucent part number (see Figure 1 and Table 1). In January 1993, Xilinx changed the nomenclature for their XC3000 series, moving away from the -70, -125, etc. speed grade ratings and creating the XC3100 series with a -3, and -4 type rating. As with the XC3000, the XC3100 series and ATT3000 series of FPGAs are identical in 1/O and are bitstream com- patible. The family identifiers in each part number vary in the same manner described for the XC3000 series above and as illustrated in Figure 1. XC3n AA-BBB CC DDD E DEVICE TYPE T_ temperature GATE CoUNTJ NUMBER OF PINS SPEED GRADE PACKAGE TYPE Xilinx XC3000 and XC3100 Series Part Numbers ATT30AA-BBB YY DDD Z DEVICE TYPE _ | | TEMPERATURE GATE COUNT NUMBER OF PINS SPEED GRADE PACKAGE TYPE Lucent ATT3000 Series Part Numbers Figure 1. Xilinx and Lucent Part Numbers Compared Lucent Technologies Inc. Table 1. Lucent/Xilinx Package Options Lucent! Xilinx Description M PC Plastic Leaded Chip Carrier (PLCC) J PQ Quad Flat Package (QFP) H PP Plastic Pin Grid Array (PPGA) S PQ | Shrink Quad Flat Package (SQFP) T TQ Thin Quad Flat Package (TQFP) Table 2. Lucent/Xilinx Temperature Options Lucent Xilinx Description (Blank) Cc Commercial | | Industrial XC3000A and XC3100A The "A" revision to Xilinxs 3000 and 3100 families involved the addition of minimal routing resources. These devices are not directly crossable to ATT3000 devices, but can be cross-referenced under two con- ditions: 1. The design may have been created as a standard XC3000 or XC3100 device. The bill of materials may call out an A" part due to lower pricing or availability issues. "A" devices are backward com- patible with earlier bitstreams. If a device was originally created as a "non-A" device, the compa- rable ATT3000 device can be dropped-in, just as with the other XC3000 devices. 2. If the bitstream originally targeted the "A" family, it is necessary to retarget the original design to the ATT3000 family and change the bitstream on the PWB. This can usually be accomplished with min- imal effort using the ORCA Foundry suite of tools. Because the ORCA.Foundry tools have superior routing algorithms, an ATT3000 design can usu- ally succeed, regardless of results obtained with Xilins XACT software. 9-363