LMC6041
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SNOS610E –DECEMBER 1994–REVISED MARCH 2013
LMC6041 CMOS Single Micropower Operational Amplifier
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1FEATURES DESCRIPTION
Ultra-low power consumption and low input-leakage
2• Low Supply Current: 14 μA (Typ) current are the hallmarks of the LMC6041. Providing
• Operates from 4.5V to 15.5V Single Supply input currents of only 2 fA typical, the LMC6041 can
• Ultra Low Input Current: 2 fA (Typ) operate from a single supply, has output swing
extending to each supply rail, and an input voltage
• Rail-to-Rail Output Swing range that includes ground.
• Input Common-Mode Range Includes Ground The LMC6041 is ideal for use in systems requiring
ultra-low power consumption. In addition, the
APPLICATIONS insensitivity to latch-up, high output drive, and output
• Battery Monitoring and Power Conditioning swing to ground without requiring external pull-down
• Photodiode and Infrared Detector Preamplifier resistors make it ideal for single-supply battery-
powered systems.
• Silicon Based Transducer Systems
• Hand-Held Analytic Instruments Other applications for the LMC6041 include bar code
reader amplifiers, magnetic and electric field
• pH Probe Buffer Amplifier detectors, and hand-held electrometers.
• Fire and Smoke Detection Systems This device is built with TI's advanced Double-Poly
• Charge Amplifier for Piezoelectric Transducers Silicon-Gate CMOS process.
See the LMC6042 for a dual, and the LMC6044 for a
quad amplifier with these features.
Connection Diagrams
Top View
Figure 1. 8-Pin SOIC or PDIP Package
See Package Number D0008A or P0008E
Figure 2. Low-Leakage Sample and Hold
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 1994–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMC6041
SNOS610E –DECEMBER 1994–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Differential Input Voltage ±Supply Voltage
Supply Voltage (V+−V−) 16V
Output Short Circuit to V−See(3)
Output Short Circuit to V+See(4)
Lead Temperature (Soldering, 10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 110°C
ESD Tolerance(5) 500V
Current at Input Pin ±5 mA
Current at Output Pin ±18 mA
Current at Power Supply Pin 35 mA
Voltage at Input/Output Pin (V+) + 0.3V, (V−)−0.3V
Power Dissipation See(6)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating conditions indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and test
conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 110°C. Output currents in excess of ±30 mA over long term may adversely
affect reliability.
(4) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.
(5) Human body model, 1.5 kΩin series with 100 pF.
(6) The maximum power dissipation is a function of TJ(max),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(max) −TA)/θJA.
Operating Ratings
Temperature Range LMC6041AI, LMC6041I −40°C ≤TJ≤+85°C
Supply Voltage 4.5V ≤V+≤15.5V
Power Dissipation See(1)
Thermal Resistance (θJA)(2) 8-Pin PDIP package 101°C/W
8-Pin SOIC package 165°C/W
(1) For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD= (TJ−TA)/θJA.
(2) All numbers apply for packages soldered directly into a PC board.
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Electrical Characteristics
Unless otherwise specified, all limits ensured for TA= TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V,
V−= 0V, VCM = 1.5V, VO= V+/2, and RL> 1M unless otherwise specified. LMC6041AI LMC6041I Units
Parameter Test Conditions Typical(1) Limit(2) Limit(2) (Limit)
VOS Input Offset Voltage 1 3 6 mV
3.3 6.3 max
TCVOS Input Offset Voltage 1.3 μV/°C
Average Drift
IBInput Bias Current 0.002 pA
4 4 max
IOS Input Offset Current 0.001 pA
2 2 max
RIN Input Resistance >10 TeraΩ
CMRR Common Mode Rejection 0V ≤VCM ≤12.0V 75 68 62 dB
Ratio V+= 15V 66 60 min
+PSRR Positive Power Supply 5V ≤V+≤15V 75 68 62 dB
Rejection Ratio VO= 2.5V 66 60 min
−PSRR Negative Power Supply 0V ≤V−≤ −10V 94 84 74 dB
Rejection Ratio VO= 2.5V 83 73 min
CMR Input Common-Mode V+= 5V and 15V −0.4 −0.1 −0.1 V
Voltage Range for CMRR ≥50 dB 0 0 max
V+−1.9V V+−2.3V V+−2.3V V
V+−2.5V V+−2.4V min
AVLarge Signal Voltage Gain RL= 100 kΩ(3) Sourcing 1000 400 300 V/mV
300 200 min
Sinking 500 180 90 V/mV
120 70 min
RL= 25 kΩ(3) Sourcing 1000 200 100 V/mV
160 80 min
Sinking 250 100 50 V/mV
60 40 min
VOOutput Swing V+= 5V 4.987 4.970 4.940 V
RL= 100 kΩto V+/2 4.950 4.910 min
0.004 0.030 0.060 V
0.050 0.090 max
V+= 5V 4.980 4.920 4.870 V
RL= 25 kΩto V+/2 4.870 4.820 min
0.010 0.080 0.130 V
0.130 0.180 max
V+= 15V 14.970 14.920 14.880 V
RL= 100 kΩto V+/2 14.880 14.820 min
0.007 0.030 0.060 V
0.050 0.090 max
V+= 15V 14.950 14.900 14.850 V
RL= 25 kΩto V+/2 14.850 14.800 min
0.022 0.100 0.150 V
0.150 0.200 max
(1) Typical Values represent the most likely parametric norm.
(2) All limits are ensured at room temperature (standard type face) or at operating temperature extremes (bold face type).
(3) V+= 15V, VCM = 7.5V and RLconnected to 7.5V. For Sourcing tests, 7.5V ≤VO≤11.5V. For Sinking tests, 2.5V ≤VO≤7.5V.
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Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for TA= TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V,
V−= 0V, VCM = 1.5V, VO= V+/2, and RL> 1M unless otherwise specified. LMC6041AI LMC6041I Units
Parameter Test Conditions Typical(1) Limit(2) Limit(2) (Limit)
ISC Output Current Sourcing, VO= 0V 22 16 13 mA
V+= 5V 10 8 min
Sinking, VO= 5V 21 16 13 mA
8 8 min
ISC Output Current Sourcing, VO= 0V 40 15 15 mA
V+= 15V 10 10 min
Sinking, VO= 13V(4) 39 24 21 mA
8 8 min
ISSupply Current VO= 1.5V 14 20 26 μA
24 30 max
V+= 15V 18 26 34 μA
31 39 max
(4) Do not connect output to V+when V+is greater than 13V or reliability may be adversely affected.
AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TA= TJ= 25°C. Boldface limits apply at the temperature extremes. V+= 5V,
V−= 0V, VCM = 1.5V, VO= V+/2, and RL> 1M unless otherwise specified. LMC6041AI LMC6041I Units
Parameter Test Conditions Typ(1) (Limit)
Limit(2) Limit(2)
SR Slew Rate See(3) 0.02 0.015 0.010 V/μs
0.010 0.007 min
GBW Gain-Bandwidth Product 75 kHz
φmPhase Margin 60 Deg
enInput-Referred Voltage Noise F = 1 kHz 83 nV/√Hz
inInput-Referred Current Noise F = 1 kHz 0.0002 pA/√Hz
THD Total Harmonic Distortion F = 1 kHz, AV=−5 0.01 %
RL= 100 kΩ, VO= 2 Vpp
±5V Supply
(1) Typical Values represent the most likely parametric norm.
(2) All limits are ensured at room temperature (standard type face) or at operating temperature extremes (bold face type).
(3) V+= 15V. Connected as Voltage Follower with 10V step input. Number specified in the slower of the positive and negative slew rates.
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Typical Performance Characteristics
VS= ± 7.5V, TA= 25°C unless otherwise specified
Supply Current Offset Voltage
vs vs
Supply Voltage Temperature of Five Representative Units
Figure 3. Figure 4.
Input Bias Current Input Bias Current
vs vs
Temperature Input Common-Mode Voltage
Figure 5. Figure 6.
Input Common-Mode Voltage Range
vs Output Characteristics
Temperature Current Sinking
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
VS= ± 7.5V, TA= 25°C unless otherwise specified
Input Voltage Noise
Output Characteristics vs
Current Sourcing Frequency
Figure 9. Figure 10.
Power Supply Rejection Ratio CMRR
vs vs
Frequency Frequency
Figure 11. Figure 12.
CMRR Open-Loop Voltage Gain
vs vs
Temperature Temperature
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
VS= ± 7.5V, TA= 25°C unless otherwise specified
Gain and Phase Responses
Open-Loop vs
Frequency Response Load Capacitance
Figure 15. Figure 16.
Gain and Phase Responses Gain Error (VOS
vs vs
Temperature VOUT)
Figure 17. Figure 18.
Common-Mode Error Non-Inverting Slew Rate
vs vs
Common-Mode Voltage of Three Representative Units Temperature
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
VS= ± 7.5V, TA= 25°C unless otherwise specified
Inverting Slew Rate Non-Inverting Large
vs Signal Pulse Response
Temperature (AV= +1)
Figure 21. Figure 22.
Non-Inverting Small Inverting Large-Signal
Signal Pulse Response Pulse Response
Figure 23. Figure 24.
Stability
Inverting Small Signal vs
Pulse Response Capacitive Load (AV= +1)
Figure 25. Figure 26.
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Typical Performance Characteristics (continued)
VS= ± 7.5V, TA= 25°C unless otherwise specified Stability
vs
Capacitive Load (AV= ±10)
Figure 27.
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APPLICATIONS HINTS
AMPLIFIER TOPOLOGY
The LMC6041 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing
even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage
is taken directly from the internal integrator, which provides both low output impedance and large gain. Special
feed-forward compensation design techniques are incorporated to maintain stability over a wider range of
operating conditions than traditional micropower op-amps. These features make the LMC6041 both easier to
design with, and provide higher speed than products typically found in this ultra-low power class.
COMPENSATING FOR INPUT CAPACITANCE
It is quite common to use large values of feedback resistance with amplifiers with ultra-low input current, like the
LMC6041.
Although the LMC6041 is highly stable over a wide range of operating conditions, certain precautions must be
met to achieve the desired pulse response when a large feedback resistor is used. Large feedback resistors and
even small values of input capacitance, due to transducers, photodiodes, and circuits board parasitics, reduce
phase margins.
When high input impedance are demanded, guarding of the LMC6041 is suggested. Guarding input lines will not
only reduce leakage, but lowers stray input capacitance as well. (See Printed-Circuit-Board Layout for High
Impedance Work.)
Figure 28. Cancelling the Effect of Input Capacitance
The effect of input capacitance can be compensated for by adding a capacitor. Adding a capacitor, Cf, around
the feedback resistor (as in Figure 28 ) such that:
(1)
or R1CIN ≤R2Cf(2)
Since it is often difficult to know the exact value of CIN, Cfcan be experimentally adjusted so that the desired
pulse response is achieved. Refer to the LMC660 and the LMC662 for a more detailed discussion on
compensating for input capacitance.
CAPACITIVE LOAD TOLERANCE
Direct capacitive loading will reduce the phase margin of many op-amps. A pole in the feedback loop is created
by the combination of the op-amp's output impedance and the capacitive load. This pole induces phase lag at the
unity-gain crossover frequency of the amplifier resulting in either an oscillatory or underdamped pulse response.
With a few external components, op amps can easily indirectly drive capacitive loads, as shown in Figure 29.
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Figure 29. LMC6041 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads
In the circuit of Figure 29, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency
component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the
overall feedback loop.
Capacitive load driving capability is enhanced by using a pull up resistor to V+(Figure 30 ). Typically a pull up
resistor conducting 10 μA or more will significantly improve capacitive load responses. The value of the pull up
resistor must be determined based on the current sinking capability of the amplifier with respect to the desired
output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical
Characteristics).
Figure 30. Compensating for Large
Capacitive Loads with a Pull Up Resistor
PRINTED-CIRCUIT-BOARD LAYOUT
FOR HIGH-IMPEDANCE WORK
It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires
special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the
LMC6041, typically less than 2fA, it is essential to have an excellent layout. Fortunately, the techniques of
obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board,
even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or
contamination, the surface leakage will be appreciable.
To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6041's inputs
and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's
inputs, as in Figure 31. To have a significant effect, guard rings should be placed on both the top and bottom of
the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifer
inputs, since no leakage current can flow between two points at the same potential. For example, a PC board
trace-to-pad resistance of 1012Ω, which is normally considered a very large resistance, could leak 5 pA if the
trace were a 5V bus adjacent to the pad of the input. This would cause a 100 times degradation from the
LMC6041's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a
resistance of 1011Ωwould cause only 0.05 pA of leakage current. See Figure 34 for typical connections of guard
rings for standard op-amp configurations.
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Figure 31. Example of Guard Ring
in P.C. Board Layout
Figure 32. Inverting Amplifier
Figure 33. Follower
Non-Inverting Amplifier
Figure 34. Typical Connections of Guard Rings
The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few
circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the
amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an
excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but
the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 35.
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(Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.)
Figure 35. Air Wiring
Typical Single-Supply Applications
(V+= 5.0 VDC)
The extremely high input impedance, and low power consumption, of the LMC6041 make it ideal for applications
that require battery-powered instrumentation amplifiers. Examples of these type of applications are hand-held pH
probes, analytic medical instruments, magnetic field detectors, gas detectors, and silicon based pressure
transducers.
Figure 36. Two Op-Amp Instrumentation Amplifier
The circuit in Figure 36 is recommended for applications where the common-mode input range is relatively low
and the differential gain will be in the range of 10 to 1000. This two op-amp instrumentation amplifier features an
independent adjustment of the gain and common-mode rejection trim, and a total quiescent supply current of less
than 28 μA. To maintain ultra-high input impedance, it is advisable to use ground rings and consider PC board
layout an important part of the overall system design (see Printed-Circuit-Board Layout for High Impedance
Work). Referring to Figure 36, the input voltages are represented as a common-mode input VCM plus a
differential input VD.
Rejection of the common-mode component of the input is accomplished by making the ratio of R1/R2 equal to
R3/R4. So that where,
(3)
A suggested design guideline is to minimize the difference of value between R1 through R4. This will often result
in improved resistor tempco, amplifier gain, and CMRR over temperature. If RN = R1 = R2 = R3 = R4 then the
gain equation can be simplified:
(4)
Due to the “zero-in, zero-out” performance of the LMC6041, and output swing rail-rail, the dynamic range is only
limited to the input common-mode range of 0V to VS–2.3V, worst case at room temperature. This feature of the
LMC6041 makes it an ideal choice for low-power instrumentation systems.
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A complete instrumentation amplifier designed for a gain of 100 is shown in Figure 37. Provisions have been
made for low sensitivity trimming of CMRR and gain.
Figure 37. Low-Power Two-Op-Amp Instrumentation Amplifier
Figure 38. Low-Leakage Sample and Hold
Figure 39. Instrumentation Amplifier
Figure 40. 1 Hz Square-Wave Oscillator
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REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMC6041AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMC60
41AIM
LMC6041AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60
41AIM
LMC6041AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60
41AIM
LMC6041IM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60
41IM
LMC6041IMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMC60
41IM
LMC6041IN/NOPB ACTIVE PDIP P 8 40 Green (RoHS
& no Sb/Br) CU SN Level-1-NA-UNLIM -40 to 85 LMC60
41IN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMC6041AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMC6041IMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMC6041AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMC6041IMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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