bq30z554-R1
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SLUSBD4 –OCTOBER 2013
2-Series, 3-Series, and 4-Series Li-Ion Battery Pack Manager
Check for Samples: bq30z554-R1
1FEATURES DESCRIPTION
The bq30z554-R1 device is a fully integrated
2• Fully Integrated 2-Series, 3-Series, and 4- Impedance Track™ gas gauge and analog monitoring
Series Li-Ion or Li-Polymer Cell Battery Pack single-package solution that provides protection and
Manager and Protection monitoring with authentication for 2-series, 3-series,
• High Side N-CH Protection FET Drive and 4-series cell Li-Ion battery packs. The bq30z554-
R1 device incorporates sophisticated algorithms that
• Impedance Track™ Gas Gauging offer cell balancing while charging or at rest.
• Integrated Cell Balancing While Charging or At
Rest The device communicates via an SBS v1.1 interface,
providing high accuracy cell parameter reporting and
• PF Snapshot and Black Box Technology control of battery pack operation, and can be
Analyze Returned Packs designed into systems that require AC peak power
• AC Peak Power Information Capability (TURBO mode), using a method to ensure that
(TURBO Mode) system performance is not disrupted.
• SBS v1.1 Interface An optimum balance of quick response hardware-
• Low Power Modes based protection along with intelligent CPU control
delivers an ideal pack solution. The device has
– Low Power: < 180 μAflexible user-programmable settings of critical system
– Sleep < 76 μAparameters, such as voltage, current, temperature,
• Complete Set of Advanced Protections: and cell imbalance, among other conditions.
– Internal Cell Short The bq30z554-R1 device has advanced charge
– Cell Imbalance algorithms, including JEITA support, enhanced cell
charging, and adaptive charging compensating
– Cell Voltage charge losses, enabling faster charging. In addition,
– Overcurrent the bq30z554-R1 device can monitor critical
– Temperature parameters over the life of the battery pack, tracking
usage conditions.
– FET Protection
• Sophisticated Charge Algorithms A general purpose output is used for power
interruption, employing an external push button
– JEITA switch.
– Enhanced Charging The advanced snapshot and black box functionality
– Adaptive Charging show critical information for analysis of returned
– Cell Balancing While Charging or At Rest battery packs.
• General Purpose Output for Power Interrupt SHA-1 authentication with secure memory for
• Diagnostic Lifetime Data Monitor authentication keys enables identification for genuine
• SHA-1 Authentication battery packs beyond doubt.
• Small Package: TSSOP
APPLICATIONS
• Notebook/Netbook PCs
• Medical and Test Equipment
• Portable Instrumentation
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Impedance Track is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Not Recommended for New Designs
bq30z554-R1
SLUSBD4 –OCTOBER 2013
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION ORDERING INFORMATION(1)
PACKAGE PACKAGE
TAPART NUMBER PACKAGE DESIGNATOR MARKING TUBE(2) TAPE AND REEL(3)
–40°C to 85°C bq30z554-R1 TSSOP–30 DBT bq30z554-R1 bq30z554DBT-R1 bq30z554DBTR-R1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of the document, or see the TI
website at www.ti.com.
(2) A single tube quantity is 50 units.
(3) A single reel quantity is 2000 units.
THERMAL INFORMATION bq30z554-R1
THERMAL METRIC(1) TSSOP UNITS
30 PINS
θJA, High K Junction-to-ambient thermal resistance(2) 73.1
θJC(top) Junction-to-case(top) thermal resistance (3) 17.5
θJB Junction-to-board thermal resistance (4) 34.5 °C/W
ψJT Junction-to-top characterization parameter (5) 0.3
ψJB Junction-to-board characterization parameter (6) 30.3
θJC(bottom) Junction-to-case(bottom) thermal resistance (7) n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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CHG
DSG
BAT
PACK
3MΩ
10kΩ
5.1kΩ
3MΩ
VC1
VC2
VC3
VC4
5mΩ
VSS SRNSRP
PACK+
PACK–
PRES
SMBC
SMBD
SMBD
SMBC
PRES
PTC
TS1
FUSE
1kΩ
1kΩ
1kΩ
1kΩ
10kΩ
1kΩ
5.1kΩ
5.1kΩ
VB
VL
VMOUT
VDD
GND
VCC
0.1μF0.1μF 0.1μF
VH
CD
10kΩ
TS2
10kΩ
10kΩ
100Ω
100Ω200Ω
100Ω200Ω
REG33
REG25
Cell
Balancing
Current
Protections
Voltage
Protections
High Side
N-CH FET
Drive
FUSE
Control
Voltage
Protections
2.5V LDO
3.3V LDO
Internal Cell
Short
Detection
Lifetime
Data
Collection
Impedance
Track
Gauging
16-bit
Voltage
Sensing
16-bit
Current
Sensing
16-bit
Temperature
Sensing
Black Box
Recorder
JEITA
Charging
Algorithm
SHA-1
Authenti-
cation
¯¯¯¯¯
¯¯¯¯¯
SMBus 1.1
SBD 1.1
bq30z554-R1
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SLUSBD4 –OCTOBER 2013
TYPICAL IMPLEMENTATION
Figure 1. bq30z554-R1 Implementation
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TERMINAL FUNCTIONS
PIN NAME PIN NUMBER TYPE DESCRIPTION
CHG 1 O Discharge N-FET gate drive
BAT 2 P Alternate power source
VC1 3 I Sense input for positive voltage of the top-most cell in the series, and cell balancing input for the
top-most cell in the series
VC2 4 I Sense input for positive voltage of the third lowest cell in the series, and cell balancing input for
the third lowest cell in the series
VC3 5 I Sense input for positive voltage of the second lowest cell in the series, and cell balancing input
for the second lowest cell in the series
VC4 6 I Sense input for positive voltage of the lowest cell in the series, and cell balancing input for the
lowest cell in the series
VSS 7 P Device ground
TS1 8 AI Temperature sensor 1 thermistor input
SRP 9 AI Differential coulomb counter input
TS2 11 AI Temperature sensor 2 thermistor input
SRN 10 AI Differential coulomb counter input
PRES 12 I Host system present input
SMBD 13 I/OD SBS 1.1 data line
NC 14 — Not connected, connect to VSS
SMBC 15 I/OD SBS 1.1 clock line
GPIO 16 I/OD General Purpose Input-Output
NC 17,18,19,20 — Not connected
RBI 21 P RAM backup
REG25 22 P 2.5-V regulator output
VSS 23 P Device ground
REG33 24 P 3.3-V regulator output
PTC 25 — Test pin connect to VSS
FUSE 26 O Fuse drive
VCC 27 P Power supply voltage
GPOD 28 I/OD High voltage general purpose I/O
PACK 29 P Alternate power source
DSG 30 O Charge N-FET gate drive
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Power FET Drive
BAT
CHG
VCC
DSG
PACK
Charge Pump
Charge Pump
GPOD
GPOD
1DSG
2
CHG
PACK
3
BAT
4
VC1 GPOD
VCC
5
VC2
6
VC3 FUSE
7
VC4
8
VSS
PTC
REG33
9
10
TS1
30
VSS
28
11
SRP
12
27
REG25
26
RBI
13
SRN
14
25
NC
24
NC
15
TS2
23
22
SMBD
NC
21
20
SMBC
29
NC
NC
GPIO
19
18
17
16
¯¯¯¯¯
PRES
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SLUSBD4 –OCTOBER 2013
PINOUT DIAGRAM
Figure 2. bq30z554-R1 Pinout Diagram
PIN EQUIVALENT DIAGRAMS
Figure 3. Pin Equivalent Diagram 1
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BAT
VCC
CHG Charge
Pump
Regulator
FUSE,
PTC
Power Supply
REG33
REG25 Regulator
FUSE
PTC
BAT
FUSE
SMB
SMBC
SMBD
TSx ADC
REG25
18kΩ
80Ω
1MΩ 1MΩ
Thermistor input
SBS
Engine
PTC
PACK
PACK DSG
Charge-
pump
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Figure 4. Pin Equivalent Diagram 2
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PRESV1, V2, V3, V4
V1, V2,
V3, V4
180kΩ
PRES
880kΩ
ADC MUX
V4
V3
V2
V1
VSS
Cell Balancing
SRN, SRP
SRN
SRP
SC, OL
comparator
Coulomb
Counter
RBI
REG25
RBI
REG25
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Figure 5. Pin Equivalent Diagram 3
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ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range (unless otherwise noted)(1)
DESCRIPTION PINS VALUE
Supply voltage range, VMAX VCC, PTC, PACK w.r.t. Vss –0.3 V to 34 V
VVC2 – 0.3 V to VVC2 + 8.5 or 34 V, whichever is
VC1, BAT lower
VC2 VVC3 – 0.3 V to VVC3 + 8.5 V
VC3 VVC4 – 0.3 V to VVC4 + 8.5 V
Input voltage range, VIN VC4 VSRP– 0.3 V to VSRP + 8.5 V
SRP, SRN –0.3 V to 0.3 V
SMBC, SMBD VSS – 0.3 V to 6.0 V
TS1, TS2, PRES, GPIO –0.3 V to VREG25 + 0.3 V
–0.3 V to VPACK + 20 V or VSS + 34 V, whichever
DSG is lower
–0.3 V to VBAT + 20 V or VSS+ 34 V, whichever
CHG is lower
Output voltage range, VOGPOD, FUSE –0.3 V to 34 V
RBI, REG25 –0.3 V to 2.75 V
REG33 –0.3 V to 5.0 V
Maximum VSS current, ISS 50 mA
Current for cell balancing, ICB 10 mA
ESD Rating HBM, VCx Only 1 kV
Functional Temperature, TFUNC –40 to 110 °C
Storage temperature range, TSTG –65 to 150 °C
Lead temperature (soldering, 10 s), TSOLDER 300 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Typical values stated where TA= 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted) MIN TYP MAX UNIT
VCC, PACK 25 V
Supply voltage BAT 3.8 VVC2 + 5.0
VSTARTUP Start up voltage at PACK 3.0 5.5 V
VC1, BAT VVC2 VVC2 + 5.0
VC2 VVC3 VVC3 + 5.0
VC3 VVC4 VVC4 + 5.0 V
VC4 VSRP VSRP + 5.0
VIN Input voltage range VCn – VC(n+1), (n=1, 2, 3, 4) 0 5.0
PACK 25
PTC 0 2 V
SRP to SRN –0.2 0.2 V
CREG33 External 3.3-V REG capacitor 1 µF
CREG25 External 2.5-V REG capacitor 1 µF
TOPR Operating temperature –40 85 °C
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ELECTRICAL CHARACTERISTICS: Supply Current
Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Normal CHG on, DSG on, no Flash write 410 µA
Sleep CHG off, DSG on, no SBS 129 µA
Communication
CHG off, DSG off, no SBS 83 µA
Communication
Shutdown 1 µA
ELECTRICAL CHARACTERISTICS: Power On Reset (POR)
Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT– Negative-going voltage input At REG25 1.9 2.0 2.1 V
VHYS POR Hysteresis At REG25 65 125 165 mV
ELECTRICAL CHARACTERISTICS: WAKE FROM SLEEP
Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VWAKE = 1.2 mV 0.2 1.2 2.0 mV
VWAKE = 2.4 mV 0.4 2.4 3.6
VWAKE VWAKE Threshold VWAKE = 5 mV 2.0 5.0 6.8
VWAKE = 10 mV 5.3 10 13
Temperature drift of VWAKE
VWAKE_TCO 0.5 %/°C
accuracy
Time from application of current
tWAKE 0.2 1 ms
and wake of bq30z554-R1
ELECTRICAL CHARACTERISTICS: RBI RAM Backup
Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VRB > V(RB)MIN, VCC < VIT 20 1100 nA
I(RBI) RBI data-retention input current VRB > V(RB)MIN, VCC < VIT, 500
TA= 0 °C to 70 °C
V(RBI) RBI data-retention voltage 1 V
ELECTRICAL CHARACTERISTICS: 3.3-V Regulator
Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
3.8 V < VCC or BAT ≤5 V, 2.4 3.5 V
ICC ≤4 mA
5 V < VCC or BAT ≤6.8 V,
VREG33 Regulator output voltage 3.1 3.3 3.5 V
ICC ≤13 mA
6.8 V < VCC or BAT ≤20 V, 3.1 3.3 3.5 V
ICC ≤30 mA
IREG33 Regulator Output Current 2 mA
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ELECTRICAL CHARACTERISTICS: 3.3-V Regulator (continued)
Typical values stated where TA = 25 °C and VCC = 14.4 V, Min/Max values stated where TA= –40 °C to 85 °C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Regulator output change with VCC or BAT = 14.4 V,
V(VDDTEMP) 0.2 %
temperature IREG33 = 2 mA
VCC or BAT = 14.4 V,
ΔV(VDDLINE) Line regulation 1 13 mV
IREG33 = 2 mA
VCC or BAT = 14.4 V,
ΔV(VDDLOAD) Load regulation 5 18 mV
IREG33 = 2 mA
VCC or BAT = 14.4 V, 70 mA
REG33 = 3 V
I(REG33MAX) Current limit VCC or BAT = 14.4 V, 33
REG33 = 0 V
ELECTRICAL CHARACTERISTICS: 2.5-V Regulator
Typical values stated where TA= 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREG25 Regulator output voltage 2.35 2.5 2.55 V
IREG25 = 10 mA
IREG25 Regulator Output Current 3 mA
Regulator output change with VCC or BAT = 14.4 V,
ΔV(VDDTEMP) 0.25 %
temperature IREG25 = 2 mA
VCC or BAT = 14.4 V,
ΔV(VDDLINE) Line regulation 1 4 mV
IREG25 = 2 mA
VCC or BAT = 14.4 V,
ΔV(VDDLOAD) Load regulation 20 40 mV
IREG25 = 2 mA
VCC or BAT = 14.4 V, 65 mA
REG25 = 2.3 V
I(REG33MAX) Current limit VCC or BAT = 14.4 V, 23
REG25 = 0 V
ELECTRICAL CHARACTERISTICS: PRES, SMBD, SMBC, GPIO
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input PRES, SMBD, SMBC, GPIO 2.0 V
PRES, SMBD, SMBC, GPIO
VIL Low-level input 0.8 V
IL = –0.5 mA
VOL Low-level output voltage SMBD, SMBC, GPIO, IL = 7 mA 0.4 V
CIN Input capacitance PRES, SMBD, SMBC, GPIO 5 pF
ILKG Input leakage current PRES, SMBD, SMBC, GPIO 1 μA
IWPU Weak Pull Up Current PRES, GPIO, VOH = VREG25 – 0.5 V 60 120 μA
RPD(SMBx) SMBC, SMBD Pull-Down TA= –40 ˚C to 100 ˚C 550 775 1000 kΩ
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ELECTRICAL CHARACTERISTICS: CHG, DSG FET Drive
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VO(FETONDSG) = V(DSG) – VPACK,
VGS connect 10 MΩ, VCC 3.8 V to 8.0 9.7 12 V
8.4 V
VO(FETONDSG) = V(DSG) – VPACK,9.0 11 12 V
Output voltage, charge, and VGS connect 10 MΩ, VCC > 8.4 V
V(FETON) discharge FETs on VO(FETONCHG) = V(CHG) – VBAT, VGS 8.0 9.7 12 V
connect 10 MΩ, VCC 3.8 V to 8.4 V
VO(FETONCHG) = V(CHG) – VBAT, VGS 9.0 11 12 V
connect 10 MΩ, VCC > 8.4 V
VO(FETOFFDSG) = V(DSG) – VPACK –0.4 0.4 V
Output voltage, charge and
V(FETOFF) discharge FETs off VO(FETOFFCHG) = V(CHG) – VBAT –0.4 0.4 V
CL= 4700 pF
RG= 5.1 kΩ
VCC <8.4 800 1400 μs
VDSG: VBAT to VBAT + 4 V,
VCHG: VPACK to VPACK + 4 V
trRise time CL= 4700 pF
RG= 5.1 kΩ
VCC >8.4 200 500 μs
VDSG: VBAT to VBAT + 4 V,
VCHG: VPACK to VPACK + 4 V
CL= 4700 pF
RG= 5.1 kΩ
VDSG: VBAT+ VO(FETONDSG) to VBAT +
tfFall time 80 200 μs
1 V
VCHG: VPACK + VO(FETONCHG) to
VPACK + 1 V
ELECTRICAL CHARACTERISTICS: GPOD
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VPU_GPOD GPOD Pull Up Voltage VCC V
VOL_GPOD GPOD Output Voltage Low IOL = 1 mA 0.3 V
ELECTRICAL CHARACTERISTICS: FUSE
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA = –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 3.8 V to 9 V 2.4 8.5 V
VOH(FUSE) High Level FUSE Output VCC = 9 V to 25 V 7 8 9 V
2.8 V
VIH(FUSE) Ensured by design. Not production
Weak Pull Up Current in off state 100 nA
tested.
CL= 1 nF, VCC = 9 V to 25V,
tR(FUSE) FUSE Output Rise Time 5 20 μs
VOH(FUSE) = 0 V to 5 V
ZO(FUSE) FUSE Output Impedance 2 5 kΩ
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ELECTRICAL CHARACTERISTICS: PTC Thermistor Support
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VPTC = 0 to 2 V,
RPTC PTC TA= –40 °C to 110 °C 1.3 2 2.7 MΩ
VPTC = 0 to 2 V
IO(PTC) PTC TA= –40 °C to 110 °C –450 –370 –230 nA
tPTC PTC Blanking Delay TA= –40 °C to 110 °C 60 80 110 ms
ELECTRICAL CHARACTERISTICS: COULOMB COUNTER
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range SRP – SRN –0.20 0.25 V
Conversion time Single conversion 250 ms
Resolution (no missing codes) 16 bits
Effective resolution Single conversion, signed 15 bits
VIN Offset error Post Calibrated 10 µV
Offset error drift 0.3 0.5 µV/°C
Full-scale error –0.8% 0.2% 0.8%
Full-scale error drift 150 PPM/°C
Effective input resistance 2.5 MΩ
ELECTRICAL CHARACTERISTICS: VC1, VC2, VC3, VC4
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VC4 – VC3, VC3 – VC2, VC2 –
Input voltage range –0.20 8 V
VC1, VC1 – VSS
Conversion time Single conversion 32 ms
VIN Resolution (no missing codes) 16 bits
Effective resolution Single conversion, signed 15 bits
RDS(ON) for internal FET at VDS > VDS = VC4 – VC3, VC3 – VC2, 200 310 430 Ω
2 V VC2 – VC1, VC1 – VSS
R(BAL) RDS(ON) for internal FET at VDS > VDS = VC4 – VC3, VC3 – VC2, 60 125 230 Ω
4 V VC2 – VC1, VC1 – VSS
ELECTRICAL CHARACTERISTICS: TS1, TS2
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R Internal Pull Up Resistor 16.5 17.5 19.0 KΩ
Internal Pull Up Resistor Drift from
RDRIFT 200 PPM/°C
25 °C
RPAD Internal Pin Pad resistance 84 Ω
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ELECTRICAL CHARACTERISTICS: TS1, TS2 (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.8×VREG2
Input voltage range TS1 – VSS, TS2 – VSS –0.20 V
5
Conversion Time 16 ms
VIN Resolution (no missing codes) 16 Bits
Effective resolution 11 12 Bits
ELECTRICAL CHARACTERISTICS: Internal Temperature Sensor
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Temperature sensor voltage –1.9 –2.0 –2.1 mV/°C
Conversion Time 16 ms
V(TEMP) Resolution (no missing codes) 16 Bits
Effective resolution 11 12 Bits
ELECTRICAL CHARACTERISTICS: Internal Thermal Shutdown
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TMAX Maximum REG33 temperature 125 175
TRECOVER Recovery hysteresis temperature 10 °C
tPROTECT Protection time 5 µs
ELECTRICAL CHARACTERISTICS: High Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(OSC) Operating frequency of CPU Clock 4.194 MHz
TA= –20 °C to 70 °C –2% ±0.25% 2%
f(EIO) Frequency error(1)(2) TA= –40 °C to 85 °C –3% ±0.25% 3%
t(SXO) Start-up time(3) TA= –25 °C to 85 °C 3 6 ms
(1) The frequency error is measured from 4.194 MHz.
(2) The frequency drift is included and measured from the trimmed frequency at VREG25 = 2.5 V, TA= 25°C.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3% when the device is already powered.
ELECTRICAL CHARACTERISTICS: Low Frequency Oscillator
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f(LOSC) Operating frequency 32.768 kHz
TA= –20 °C to 70 °C –1.5% ±0.25% 1.5%
f(LEIO) Frequency error(1)(2) TA= –40 °C to 85 °C –2.5% ±0.25% 2.5%
t(LSXO) Start-up time(3) TA= –25 °C to 85 °C 100 μs
(1) The frequency drift is included and measured from the trimmed frequency at VCC = 2.5 V, TA= 25 °C.
(2) The frequency error is measured from 32.768 kHz.
(3) The startup time is defined as the time it takes for the oscillator output frequency to be ±3 %.
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ELECTRICAL CHARACTERISTICS: Internal Voltage Reference
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VREF Internal Reference Voltage 1.215 1.225 1.230 V
TA= –25 °C to 85 °C ±80 PPM/°C
VREF_DRIFT Internal Reference Voltage Drift TA= 0 °C to 60 °C ±50 PPM/°C
ELECTRICAL CHARACTERISTICS: Flash
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER(1) TEST CONDITIONS MIN TYP MAX UNIT
Data retention 10 Years
Data Flash 20k Cycles
Flash programming write-cycles Instruction Flash 1k Cycles
ICC(PROG_DF) Data Flash-write supply current TA= –40°C to 85°C 3 4 mA
ICC(ERASE_DF) Data Flash-erase supply current TA= –40°C to 85°C 3 18 mA
(1) Assured by design. Not production tested.
ELECTRICAL CHARACTERISTICS: OCD Current Protection
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSNS = 0 50 200 mV
OCD detection threshold voltage
V(OCD) range, typical RSNS = 1 25 100 mV
RSNS = 0 10 mV
OCD detection threshold voltage
ΔV(OCDT) program step RSNS = 1 5 mV
V(OFFSET) OCD offset –10 10 mV
V(Scale_Err) OCD scale error –10 10 %
t(OCDD) Overcurrent in Discharge Delay 1 31 ms
t(OCDD_STEP) OCDD Step options 2 ms
VSRP – SRN = VTHRESH +
t(DETECT) Current fault detect time 160 µs
12.5 mV
Overcurrent and Short Circuit
tACC Accuracy of typical delay time –20 20 %
delay time accuracy
ELECTRICAL CHARACTERISTICS: SCD1 Current Protection
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSNS = 0 100 450 mV
SCD1 detection threshold voltage
V(SDC1) range, typical RSNS = 1 50 225 mV
RSNS = 0 50 mV
SCD1 detection threshold voltage
ΔV(SCD1T) program step RSNS = 1 25 mV
V(OFFSET) SCD1 offset –10 10 mV
V(Scale_Err) SCD1 scale error –10 10 %
AFE.STATE_CNTL[SCDDx2] = 0 0 915 µs
t(SCD1D) Short Circuit in Discharge Delay AFE.STATE_CNTL[SCDDx2] = 1 0 1830 µs
AFE.STATE_CNTL[SCDDx2] = 0 61 µs
t(SCD1D_STEP) SCD1D Step options AFE.STATE_CNTL[SCDDx2] = 1 122 µs
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ELECTRICAL CHARACTERISTICS: SCD1 Current Protection (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t(DETECT) Current fault detect time VSRP-SRN = VTHRESH + 12.5 mV 160 µs
Overcurrent and Short Circuit
tACC Accuracy of typical delay time –20 20 %
delay time accuracy
ELECTRICAL CHARACTERISTICS: SCD2 Current Protection
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSNS = 0 100 450 mV
SCD2 detection threshold voltage
V(SDC2) range, typical RSNS = 1 50 225 mV
RSNS = 0 50 mV
SCD2 detection threshold voltage
ΔV(SCD2T) program step RSNS = 1 25 mV
V(OFFSET) SCD2 offset –10 10 mV
V(Scale_Err) SCD2 scale error –10 10 %
AFE.STATE_CNTL[SCDDx2] = 0 0 458 µs
t(SCD1D) Short Circuit in Discharge Delay AFE.STATE_CNTL[SCDDx2] = 1 0 915 µs
AFE.STATE_CNTL[SCDDx2] = 0 30.5 µs
t(SCD2D_STEP) SCD2D Step options AFE.STATE_CNTL[SCDDx2] = 1 61 µs
VSRP – SRN = VTHRESH +
t(DETECT) Current fault detect time 160 µs
12.5 mV
Overcurrent and Short Circuit
tACC Accuracy of typical delay time –20 20 %
delay time accuracy
ELECTRICAL CHARACTERISTICS: SCC Current Protection
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RSNS = 0 –100 –300 mV
SCC detection threshold voltage
V(SCCT) range, typical RSNS = 1 –50 –225 mV
RSNS = 0 –50 mV
SCC detection threshold voltage
ΔV(SCCDT) program step RSNS = 1 –25 mV
V(OFFSET) SCC offset –10 10 mV
V(Scale_Err) SCC scale error –10 10 %
t(SCCD) Short Circuit in Charge Delay 0 915 ms
t(SCCD_STEP) SCCD Step options 61 ms
VSRP – SRN = VTHRESH +
t(DETECT) Current fault detect time 160 µs
12.5 mV
Overcurrent and Short Circuit
tACC Accuracy of typical delay time –20 20 %
delay time accuracy
ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SLAVE mode, SMBC 50% duty
fSMB SMBus operating frequency 10 100 kHz
cycle
MASTER mode, no clock low slave
fMAS SMBus master clock frequency 51.2 kHz
extend
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ELECTRICAL CHARACTERISTICS: SBS Timing Characteristics (continued)
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Bus free time between start and
tBUF 4.7 µs
stop
tHD:STA Hold time after (repeated) start 4.0 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4.0 µs
tHD:DAT Data hold time 300 ns
tSU:DAT Data setup time 250 ns
tTIMEOUT Error signal/detect See (1) 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period See (2) Disabled
tHIGH Clock high period See (2) 4.0 50 µs
Cumulative clock low slave extend
tLOW:SEXT See (3) 25 ms
time
Cumulative clock low master
tLOW:MEXT See (4) 10 ms
extend time
tFClock/data fall time See (5) 300 ns
tRClock/data rise time See (6) 1000 ns
(1) The bq30z554-R1 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH, Max, is the minimum bus idle time. SMBC = 1 for t > 50 µs causes reset of any transaction involving bq30z554-R1 in progress.
This specification is valid when the THIGH_VAL = 0. If THIGH_VAL = 1 then the value of THIGH is set by THIGH_1,2 and the timeout is
not SMBus standard.
(3) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5) Rise time tR = VILMAX – 0.15) to (VIHMIN + 0.15)
(6) Fall time tF = 0.9 VDD to (VILMAX – 0.15)
ELECTRICAL CHARACTERISTICS: SBS XL Timing Characteristics
Typical values stated where TA = 25°C and VCC = 14.4 V, Min/Max values stated where TA= –40°C to 85°C and VCC =
3.8 V to 25 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fSMBXL SMBus XL operating frequency SLAVE mode 40 400 kHz
Bus free time between start and
tBUF 4.7 µs
stop
tHD:STA Hold time after (repeated) start 4.0 µs
tSU:STA Repeated start setup time 4.7 µs
tSU:STO Stop setup time 4.0 µs
tTIMEOUT Error signal/detect See (1) 5 20 ms
tLOW Clock low period 20 µs
tHIGH Clock high period See (2) 20 µs
(1) The bq30z554-R1 times out when any clock low exceeds tTIMEOUT.
(2) tHIGH, Max, is the minimum bus idle time.
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SMBC
SMBD
SMBC
SMBD
SMBC
SMBD
S
tSU(STA)
SP
T(BUF)
tSU(STOP)
tRtF
SMBC
SMBD
t(TIMEOUT)
tW(H)
tW(L)
tFtR
tHD(DATA) tSU(DATA)
tDH(STA)
bq30z554-R1
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SLUSBD4 –OCTOBER 2013
Figure 6. SMBus Timing Diagram
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FEATURE SET
Protections Safety Features
The bq30z554-R1 supports a wide range of battery and system protection features that can easily be configured.
The Protections safety features include:
• Cell Undervoltage Protection
• Cell Undervoltage I*R Compensated Protection
• Cell Overvoltage Protection
• Overcurrent in Charge Protection 1 and 2
• Overcurrent in Discharge Protection 1 and 2
• Overload in Discharge Protection
• Short Circuit in Charge Protection
• Short Circuit in Discharge Protection 1 and 2
• Overtemperature in Charge Protection
• Overtemperature in Discharge Protection
• Overtemperature FET protection
• SBS Host Watchdog Protection
• Precharge Timeout Protection
• Fast Charge Timeout Protection
• Overcharge Protection
• Overcharging Current Protection
• Overcharging Voltage Protection
Permanent Fail Safety Features
The FUSE pin can be used to blow an in-line fuse to permanently disable the battery pack from charging or
discharging. Upon a Permanent Fail event trigger, critical system information is written to non-volatile memory to
simplify failure analysis. In addition, the black box stores the sequence of safety events also into non-volatile
memory to simplify failure analysis. The Permanent Fail safety features include:
• Cell Undervoltage Protection
• Cell Overvoltage Protection
• Copper Deposition
• Overtemperature Cell
• Overtemperature FET
• QMAX Imbalance
• Cell Balancing
• Capacity Degradation
• Impedance
• Voltage Imbalance at Rest
• Voltage Imbalance Active
• Charge FET and Discharge FET
• Thermistor
• Chemical FUSE
• AFE Register
• AFE Communication
• 2nd-Level Protection
• PTC
• Instruction Flash
• Open Cell Tab Connection
• Data Flash
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Charge Control Features
The bq30z554-R1 Charge Control features include:
• Supports JEITA temperature ranges T1, T2, T3, T4, T5, T6. Reports charging voltage and charging current,
according to the active temperature range.
• Handles more complex charging profiles. Allows for splitting the standard temperature range into two sub-
ranges, and allows for varying the charging current according to the cell voltage.
• Reports the appropriate charging current needed for constant current charging and the appropriate charging
voltage needed for constant voltage charging to a smart charger using SMBus broadcasts.
• Determines the chemical state of charge of each battery cell using Impedance Track and can reduce the
charge difference of the battery cells in a fully charged state of the battery pack, gradually using the cell
balancing algorithm during rest and charging. This prevents fully charged cells from overcharging and causing
excessive degradation, and also increases the usable pack energy by preventing premature charge
termination.
• Supports precharging/zero-volt charging
• Supports charge inhibit and charge suspend if the battery pack temperature is out of temperature range.
• Reports charging fault and also indicates charge status via charge and discharge alarms.
Gas Gauging
The bq30z554-R1 uses the Impedance Track technology to measure and calculate the available charge in
battery cells. The achievable accuracy is better than 1% error over the lifetime of the battery and there is no full
charge or discharge learning cycle required. See the Theory and Implementation of Impedance Track Battery
Fuel-Gauging Algorithm application report (SLUA364B) for further details.
Lifetime Data Logging Features
The bq30z554-R1 offers extended lifetime data logging where important measurements are stored for warranty
and analysis purposes. The data monitored includes lifetime:
• Maximum cell voltage cell0, cell1, cell2, cell3
• Minimum cell voltage cell0, cell1, cell2, cell3
• Maximum cell voltage delta
• Maximum charge and discharge current
• Maximum average discharge current
• Maximum average discharge power
• Maximum cell temperature
• Minimum cell temperature
• Maximum cell temperature delta
• Maximum device temperature
• Minimum device temperature
• Maximum FET temperature
• Total accumulated safety events and last safety event in term of charging cycle
• Total accumulated charging events and charging events
• Total accumulated gauging events and gauging events
• Total accumulated cell balancing time cell0, cell1, cell2, cell3
• Total device firmware runtime
• Accumulated runtime in JEITA undertemperature range
• Accumulated runtime in JEITA low temperature range
• Accumulated runtime in JEITA standard temperature range
• Accumulated runtime in JEITA recommended temperature range
• Accumulated runtime in JEITA high temperature range
• Accumulated runtime in JEITA overtemperature range
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Authentication
• The bq30z554-R1 supports authentication by the host using SHA-1.
• SHA-1 authentication by the gas gauge is required for unsealing and full access.
Power Modes
The bq30z554-R1 supports five power modes to reduce power consumption:
• In NORMAL mode, the bq30z554-R1 performs measurements, calculations, protection decisions, and data
updates in 0.25-s intervals. Between these intervals, the bq30z554-R1 is in a reduced power stage. In
addition, the device will provide information for peak TURBO mode power operation.
• The bq30z554-R1 supports a TURBO mode operation by providing information to the host MCU about the
battery pack's ability to deliver peak power. The method of operation is based on the host MCU reading
register 0x59 (TURBO_POWER) to determine if the selected power level for TURBO mode operation of the
MCU is below the max power reported by the gas gauge. Additionally, the device reports current information
during the power pulse by reading register 0x5E (TURBO_CURRENT). The information reported by these two
registers allows the MCU to determine if the selected TURBO mode operation is safe and will not cause any
system reset due to transient power pulses.
• In SLEEP mode, the bq30z554-R1 performs measurements, calculations, protection decisions, and data
updates in adjustable time intervals. Between these intervals, the bq30z554-R1 is in a reduced power stage.
The bq30z554-R1 has a wake function that enables exit from SLEEP mode when current flow or failure is
detected.
• In SHUTDOWN mode, the bq30z554-R1 is completely disabled.
• In SHIP mode, the bq30z554-R1 enters a low-power mode with no voltage, current, and temperature
measurements, the FETs are turned off, and the MCU is in a halt state. The device wakes up upon SMBus
communication detection.
NOTE
For a detailed description of the SBS Commands and Data Flash (DF) Registers, refer to
the bq30z554-R1 Technical Reference Manual (SLUUA79).
Configuration
System Present Operation
The bq30z554-R1 checks the PRES pin periodically (1 s). If PRES input is pulled to ground by the external
system, the bq30z554-R1 detects this as system present.
Battery Power Interrupt Operation
The bq30z554-R1 can interrupt the battery power by using an external push-button switch and detecting a low-
level threshold signal on the GPIO terminal (pin should be configured with an internal pull-up). Once the push
button is pressed, there is a delay of 1 s (default) for debounce to detect the low-level threshold. There is also a
data flash command for the battery power interrupt timeout. The default value is 30 minutes. If the push-button
switch is selected before this timeout, the battery power is restored based on this action.
Timeout Configuration
The timeout feature allows the battery power to be restored once the timer expires. Alternatively, if the value is
set to 0, this feature is disabled.
Subclass
Class Subclass Offset Name Type Min Max Default Unit
ID
Power 248 Power Off 0 Timeout U2 0 65535 30 min
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BATTERY PARAMETER MEASUREMENTS
Charge and Discharge Counting
The bq30z554-R1 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement,
and a second delta-sigma ADC for individual cell and battery voltage and temperature measurements.
The integrating delta-sigma ADC measures the charge/discharge flow of the battery by measuring the voltage
drop across a small-value sense resistor between the SR1 and SR2 pins. The integrating ADC measures bipolar
signals from –0.25 V to 0.25 V. The bq30z554-R1 detects charge activity when VSR = V(SRP) – V(SRN) is positive,
and discharge activity when VSR = V(SRP) – V(SRN) is negative. The bq30z554-R1 continuously integrates the
signal over time, using an internal counter. The fundamental rate of the counter is 0.65 nVh.
Voltage
The bq30z554-R1 updates the individual series cell voltages at 0.25-s intervals. The internal ADC of the
bq30z554-R1 measures the voltage, and scales and calibrates it appropriately. This data is also used to
calculate the impedance of the cell for the Impedance Track gas gauging.
Current
The bq30z554-R1 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge
current using a 5-mΩto 20-mΩtyp. sense resistor.
Auto Calibration
The bq30z554-R1 provides an auto-calibration feature to cancel the voltage offset error across SRN and SRP for
maximum charge measurement accuracy. The bq30z554-R1 performs auto-calibration when the SMBus lines
stay low continuously for a minimum of 5 s.
Temperature
The bq30z554-R1 has an internal temperature sensor and inputs for four external temperature sensors. All five
temperature sensor options are enabled individually and configured for cell or FET temperature. Two
configurable thermistor models are provided to allow the monitoring of cell temperature in addition to FET
temperature, which may be of a higher temperature type.
CELL BALANCING
The device supports cell balancing by bypassing the current of each cell during charging or at rest. If the device
internal bypass is used, up to 10 mA can be bypassed and multiple cells can be bypassed at the same time.
Higher cell balance current can be achieved by using an external cell balancing circuit. In EXTERNAL CELL
BALANCING mode, only one cell at a time can be balanced.
The cell balancing algorithm determines the amount of charge needed to be bypassed to balance the capacity of
all cells.
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RVC
RVC
RVC
RVC
VC1
VC2
VC3
VC4
VSS
RB
RB
RB
RB
RVC
RVC
RVC
RVC
VC1
VC2
VC3
VC4
VSS
bq30z554-R1
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Internal Cell Balancing
When internal cell balancing is configured, the cell balance current is defined by the external resistor RVC at the
VCx input.
External Cell Balancing
When internal cell balancing is configured, the cell balance current is defined by RB. Only one cell at a time can
be balanced.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
BQ30Z554DBT-R1 NRND TSSOP DBT 30 60 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ30Z554
BQ30Z554DBTR-R1 NRND TSSOP DBT 30 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ30Z554
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
BQ30Z554DBTR-R1 TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Sep-2014
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
BQ30Z554DBTR-R1 TSSOP DBT 30 2000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Sep-2014
Pack Materials-Page 2
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